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Linux/arch/powerpc/include/asm/hydra.h

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Diff markup

Differences between /arch/powerpc/include/asm/hydra.h (Architecture m68k) and /arch/sparc/include/asm-sparc/hydra.h (Architecture sparc)


  1 /*                                                  1 
  2  *  include/asm-ppc/hydra.h -- Mac I/O `Hydra'    
  3  *                                                
  4  *  Copyright (C) 1997 Geert Uytterhoeven         
  5  *                                                
  6  *  This file is based on the following docume    
  7  *                                                
  8  *      Macintosh Technology in the Common Har    
  9  *      Apple Computer, Inc.                      
 10  *                                                
 11  *      © Copyright 1995 Apple Computer, Inc.    
 12  *                                                
 13  *  It's available online from https://www.cpu    
 14  *  You can obtain paper copies of this book f    
 15  *  writing Morgan Kaufmann Publishers, Inc.,     
 16  *  Francisco, CA 94104. Reference ISBN 1-5586    
 17  *                                                
 18  *  This file is subject to the terms and cond    
 19  *  License.  See the file COPYING in the main    
 20  *  for more details.                             
 21  */                                               
 22                                                   
 23 #ifndef _ASMPPC_HYDRA_H                           
 24 #define _ASMPPC_HYDRA_H                           
 25                                                   
 26 #ifdef __KERNEL__                                 
 27                                                   
 28 struct Hydra {                                    
 29     /* DBDMA Controller Register Space */         
 30     char Pad1[0x30];                              
 31     u_int CachePD;                                
 32     u_int IDs;                                    
 33     u_int Feature_Control;                        
 34     char Pad2[0x7fc4];                            
 35     /* DBDMA Channel Register Space */            
 36     char SCSI_DMA[0x100];                         
 37     char Pad3[0x300];                             
 38     char SCCA_Tx_DMA[0x100];                      
 39     char SCCA_Rx_DMA[0x100];                      
 40     char SCCB_Tx_DMA[0x100];                      
 41     char SCCB_Rx_DMA[0x100];                      
 42     char Pad4[0x7800];                            
 43     /* Device Register Space */                   
 44     char SCSI[0x1000];                            
 45     char ADB[0x1000];                             
 46     char SCC_Legacy[0x1000];                      
 47     char SCC[0x1000];                             
 48     char Pad9[0x2000];                            
 49     char VIA[0x2000];                             
 50     char Pad10[0x28000];                          
 51     char OpenPIC[0x40000];                        
 52 };                                                
 53                                                   
 54 extern volatile struct Hydra __iomem *Hydra;      
 55                                                   
 56                                                   
 57     /*                                            
 58      *  Feature Control Register                  
 59      */                                           
 60                                                   
 61 #define HYDRA_FC_SCC_CELL_EN    0x00000001        
 62 #define HYDRA_FC_SCSI_CELL_EN   0x00000002        
 63 #define HYDRA_FC_SCCA_ENABLE    0x00000004        
 64 #define HYDRA_FC_SCCB_ENABLE    0x00000008        
 65 #define HYDRA_FC_ARB_BYPASS     0x00000010        
 66 #define HYDRA_FC_RESET_SCC      0x00000020        
 67 #define HYDRA_FC_MPIC_ENABLE    0x00000040        
 68 #define HYDRA_FC_SLOW_SCC_PCLK  0x00000080        
 69 #define HYDRA_FC_MPIC_IS_MASTER 0x00000100        
 70                                                   
 71                                                   
 72     /*                                            
 73      *  OpenPIC Interrupt Sources                 
 74      */                                           
 75                                                   
 76 #define HYDRA_INT_SIO           0                 
 77 #define HYDRA_INT_SCSI_DMA      1                 
 78 #define HYDRA_INT_SCCA_TX_DMA   2                 
 79 #define HYDRA_INT_SCCA_RX_DMA   3                 
 80 #define HYDRA_INT_SCCB_TX_DMA   4                 
 81 #define HYDRA_INT_SCCB_RX_DMA   5                 
 82 #define HYDRA_INT_SCSI          6                 
 83 #define HYDRA_INT_SCCA          7                 
 84 #define HYDRA_INT_SCCB          8                 
 85 #define HYDRA_INT_VIA           9                 
 86 #define HYDRA_INT_ADB           10                
 87 #define HYDRA_INT_ADB_NMI       11                
 88 #define HYDRA_INT_EXT1          12      /* PCI    
 89 #define HYDRA_INT_EXT2          13      /* PCI    
 90 #define HYDRA_INT_EXT3          14      /* PCI    
 91 #define HYDRA_INT_EXT4          15      /* PCI    
 92 #define HYDRA_INT_EXT5          16      /* IDE    
 93 #define HYDRA_INT_EXT6          17      /* IDE    
 94 #define HYDRA_INT_EXT7          18      /* Pow    
 95 #define HYDRA_INT_SPARE         19                
 96                                                   
 97 #endif /* __KERNEL__ */                           
 98                                                   
 99 #endif /* _ASMPPC_HYDRA_H */                      
100                                                   

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