1 /* 1
2 * Prototypes, etc. for the Freescale MPC52xx
3 * May need to be cleaned as the port goes on
4 *
5 * Copyright (C) 2004-2005 Sylvain Munaut <tnt
6 * Copyright (C) 2003 MontaVista, Software, In
7 *
8 * This file is licensed under the terms of th
9 * version 2. This program is licensed "as is"
10 * kind, whether express or implied.
11 */
12
13 #ifndef __ASM_POWERPC_MPC52xx_H__
14 #define __ASM_POWERPC_MPC52xx_H__
15
16 #ifndef __ASSEMBLY__
17 #include <asm/types.h>
18 #include <asm/mpc5xxx.h>
19 #endif /* __ASSEMBLY__ */
20
21 #include <linux/suspend.h>
22
23 /* Variants of the 5200(B) */
24 #define MPC5200_SVR 0x80110010
25 #define MPC5200_SVR_MASK 0xfffffff0
26 #define MPC5200B_SVR 0x80110020
27 #define MPC5200B_SVR_MASK 0xfffffff0
28
29 /* ===========================================
30 /* Structures mapping of some unit register se
31 /* ===========================================
32
33 #ifndef __ASSEMBLY__
34
35 /* Memory Mapping Control */
36 struct mpc52xx_mmap_ctl {
37 u32 mbar; /* MMAP_CTRL +
38
39 u32 cs0_start; /* MMAP_CTRL +
40 u32 cs0_stop; /* MMAP_CTRL +
41 u32 cs1_start; /* MMAP_CTRL +
42 u32 cs1_stop; /* MMAP_CTRL +
43 u32 cs2_start; /* MMAP_CTRL +
44 u32 cs2_stop; /* MMAP_CTRL +
45 u32 cs3_start; /* MMAP_CTRL +
46 u32 cs3_stop; /* MMAP_CTRL +
47 u32 cs4_start; /* MMAP_CTRL +
48 u32 cs4_stop; /* MMAP_CTRL +
49 u32 cs5_start; /* MMAP_CTRL +
50 u32 cs5_stop; /* MMAP_CTRL +
51
52 u32 sdram0; /* MMAP_CTRL +
53 u32 sdram1; /* MMAP_CTRL +
54
55 u32 reserved[4]; /* MMAP_CTRL +
56
57 u32 boot_start; /* MMAP_CTRL +
58 u32 boot_stop; /* MMAP_CTRL +
59
60 u32 ipbi_ws_ctrl; /* MMAP_CTRL +
61
62 u32 cs6_start; /* MMAP_CTRL +
63 u32 cs6_stop; /* MMAP_CTRL +
64 u32 cs7_start; /* MMAP_CTRL +
65 u32 cs7_stop; /* MMAP_CTRL +
66 };
67
68 /* SDRAM control */
69 struct mpc52xx_sdram {
70 u32 mode; /* SDRAM + 0x0
71 u32 ctrl; /* SDRAM + 0x0
72 u32 config1; /* SDRAM + 0x0
73 u32 config2; /* SDRAM + 0x0
74 };
75
76 /* SDMA */
77 struct mpc52xx_sdma {
78 u32 taskBar; /* SDMA + 0x00
79 u32 currentPointer; /* SDMA + 0x04
80 u32 endPointer; /* SDMA + 0x08
81 u32 variablePointer; /* SDMA + 0x0c
82
83 u8 IntVect1; /* SDMA + 0x10
84 u8 IntVect2; /* SDMA + 0x11
85 u16 PtdCntrl; /* SDMA + 0x12
86
87 u32 IntPend; /* SDMA + 0x14
88 u32 IntMask; /* SDMA + 0x18
89
90 u16 tcr[16]; /* SDMA + 0x1c
91
92 u8 ipr[32]; /* SDMA + 0x3c
93
94 u32 cReqSelect; /* SDMA + 0x5c
95 u32 task_size0; /* SDMA + 0x60
96 u32 task_size1; /* SDMA + 0x64
97 u32 MDEDebug; /* SDMA + 0x68
98 u32 ADSDebug; /* SDMA + 0x6c
99 u32 Value1; /* SDMA + 0x70
100 u32 Value2; /* SDMA + 0x74
101 u32 Control; /* SDMA + 0x78
102 u32 Status; /* SDMA + 0x7c
103 u32 PTDDebug; /* SDMA + 0x80
104 };
105
106 /* GPT */
107 struct mpc52xx_gpt {
108 u32 mode; /* GPTx + 0x00
109 u32 count; /* GPTx + 0x04
110 u32 pwm; /* GPTx + 0x08
111 u32 status; /* GPTx + 0X0c
112 };
113
114 /* GPIO */
115 struct mpc52xx_gpio {
116 u32 port_config; /* GPIO + 0x00
117 u32 simple_gpioe; /* GPIO + 0x04
118 u32 simple_ode; /* GPIO + 0x08
119 u32 simple_ddr; /* GPIO + 0x0c
120 u32 simple_dvo; /* GPIO + 0x10
121 u32 simple_ival; /* GPIO + 0x14
122 u8 outo_gpioe; /* GPIO + 0x18
123 u8 reserved1[3]; /* GPIO + 0x19
124 u8 outo_dvo; /* GPIO + 0x1c
125 u8 reserved2[3]; /* GPIO + 0x1d
126 u8 sint_gpioe; /* GPIO + 0x20
127 u8 reserved3[3]; /* GPIO + 0x21
128 u8 sint_ode; /* GPIO + 0x24
129 u8 reserved4[3]; /* GPIO + 0x25
130 u8 sint_ddr; /* GPIO + 0x28
131 u8 reserved5[3]; /* GPIO + 0x29
132 u8 sint_dvo; /* GPIO + 0x2c
133 u8 reserved6[3]; /* GPIO + 0x2d
134 u8 sint_inten; /* GPIO + 0x30
135 u8 reserved7[3]; /* GPIO + 0x31
136 u16 sint_itype; /* GPIO + 0x34
137 u16 reserved8; /* GPIO + 0x36
138 u8 gpio_control; /* GPIO + 0x38
139 u8 reserved9[3]; /* GPIO + 0x39
140 u8 sint_istat; /* GPIO + 0x3c
141 u8 sint_ival; /* GPIO + 0x3d
142 u8 bus_errs; /* GPIO + 0x3e
143 u8 reserved10; /* GPIO + 0x3f
144 };
145
146 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_C
147 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD
148 #define MPC52xx_GPIO_PCI_DIS
149
150 /* GPIO with WakeUp*/
151 struct mpc52xx_gpio_wkup {
152 u8 wkup_gpioe; /* GPIO_WKUP +
153 u8 reserved1[3]; /* GPIO_WKUP +
154 u8 wkup_ode; /* GPIO_WKUP +
155 u8 reserved2[3]; /* GPIO_WKUP +
156 u8 wkup_ddr; /* GPIO_WKUP +
157 u8 reserved3[3]; /* GPIO_WKUP +
158 u8 wkup_dvo; /* GPIO_WKUP +
159 u8 reserved4[3]; /* GPIO_WKUP +
160 u8 wkup_inten; /* GPIO_WKUP +
161 u8 reserved5[3]; /* GPIO_WKUP +
162 u8 wkup_iinten; /* GPIO_WKUP +
163 u8 reserved6[3]; /* GPIO_WKUP +
164 u16 wkup_itype; /* GPIO_WKUP +
165 u8 reserved7[2]; /* GPIO_WKUP +
166 u8 wkup_maste; /* GPIO_WKUP +
167 u8 reserved8[3]; /* GPIO_WKUP +
168 u8 wkup_ival; /* GPIO_WKUP +
169 u8 reserved9[3]; /* GPIO_WKUP +
170 u8 wkup_istat; /* GPIO_WKUP +
171 u8 reserved10[3]; /* GPIO_WKUP +
172 };
173
174 /* XLB Bus control */
175 struct mpc52xx_xlb {
176 u8 reserved[0x40];
177 u32 config; /* XLB + 0x40
178 u32 version; /* XLB + 0x44
179 u32 status; /* XLB + 0x48
180 u32 int_enable; /* XLB + 0x4c
181 u32 addr_capture; /* XLB + 0x50
182 u32 bus_sig_capture; /* XLB + 0x54
183 u32 addr_timeout; /* XLB + 0x58
184 u32 data_timeout; /* XLB + 0x5c
185 u32 bus_act_timeout; /* XLB + 0x60
186 u32 master_pri_enable; /* XLB + 0x64
187 u32 master_priority; /* XLB + 0x68
188 u32 base_address; /* XLB + 0x6c
189 u32 snoop_window; /* XLB + 0x70
190 };
191
192 #define MPC52xx_XLB_CFG_PLDIS (1 <<
193 #define MPC52xx_XLB_CFG_SNOOP (1 <<
194
195 /* Clock Distribution control */
196 struct mpc52xx_cdm {
197 u32 jtag_id; /* CDM + 0x00
198 u32 rstcfg; /* CDM + 0x04
199 u32 breadcrumb; /* CDM + 0x08
200
201 u8 mem_clk_sel; /* CDM + 0x0c
202 u8 xlb_clk_sel; /* CDM + 0x0d
203 u8 ipb_clk_sel; /* CDM + 0x0e
204 u8 pci_clk_sel; /* CDM + 0x0f
205
206 u8 ext_48mhz_en; /* CDM + 0x10
207 u8 fd_enable; /* CDM + 0x11
208 u16 fd_counters; /* CDM + 0x12
209
210 u32 clk_enables; /* CDM + 0x14
211
212 u8 osc_disable; /* CDM + 0x18
213 u8 reserved0[3]; /* CDM + 0x19
214
215 u8 ccs_sleep_enable; /* CDM + 0x1c
216 u8 osc_sleep_enable; /* CDM + 0x1d
217 u8 reserved1; /* CDM + 0x1e
218 u8 ccs_qreq_test; /* CDM + 0x1f
219
220 u8 soft_reset; /* CDM + 0x20
221 u8 no_ckstp; /* CDM + 0x21
222 u8 reserved2[2]; /* CDM + 0x22
223
224 u8 pll_lock; /* CDM + 0x24
225 u8 pll_looselock; /* CDM + 0x25
226 u8 pll_sm_lockwin; /* CDM + 0x26
227 u8 reserved3; /* CDM + 0x27
228
229 u16 reserved4; /* CDM + 0x28
230 u16 mclken_div_psc1; /* CDM + 0x2a
231
232 u16 reserved5; /* CDM + 0x2c
233 u16 mclken_div_psc2; /* CDM + 0x2e
234
235 u16 reserved6; /* CDM + 0x30
236 u16 mclken_div_psc3; /* CDM + 0x32
237
238 u16 reserved7; /* CDM + 0x34
239 u16 mclken_div_psc6; /* CDM + 0x36
240 };
241
242 /* Interrupt controller Register set */
243 struct mpc52xx_intr {
244 u32 per_mask; /* INTR + 0x00
245 u32 per_pri1; /* INTR + 0x04
246 u32 per_pri2; /* INTR + 0x08
247 u32 per_pri3; /* INTR + 0x0c
248 u32 ctrl; /* INTR + 0x10
249 u32 main_mask; /* INTR + 0x14
250 u32 main_pri1; /* INTR + 0x18
251 u32 main_pri2; /* INTR + 0x1c
252 u32 reserved1; /* INTR + 0x20
253 u32 enc_status; /* INTR + 0x24
254 u32 crit_status; /* INTR + 0x28
255 u32 main_status; /* INTR + 0x2c
256 u32 per_status; /* INTR + 0x30
257 u32 reserved2; /* INTR + 0x34
258 u32 per_error; /* INTR + 0x38
259 };
260
261 #endif /* __ASSEMBLY__ */
262
263
264 /* ===========================================
265 /* Prototypes for MPC52xx sysdev
266 /* ===========================================
267
268 #ifndef __ASSEMBLY__
269
270 struct device_node;
271
272 /* mpc52xx_common.c */
273 extern void mpc5200_setup_xlb_arbiter(void);
274 extern void mpc52xx_declare_of_platform_device
275 extern int mpc5200_psc_ac97_gpio_reset(int psc
276 extern void mpc52xx_map_common_devices(void);
277 extern int mpc52xx_set_psc_clkdiv(int psc_id,
278 extern void __noreturn mpc52xx_restart(char *c
279
280 /* mpc52xx_gpt.c */
281 struct mpc52xx_gpt_priv;
282 extern struct mpc52xx_gpt_priv *mpc52xx_gpt_fr
283 extern int mpc52xx_gpt_start_timer(struct mpc5
284 int continuous);
285 extern u64 mpc52xx_gpt_timer_period(struct mpc
286 extern int mpc52xx_gpt_stop_timer(struct mpc52
287
288 /* mpc52xx_pic.c */
289 extern void mpc52xx_init_irq(void);
290 extern unsigned int mpc52xx_get_irq(void);
291
292 /* mpc52xx_pci.c */
293 #ifdef CONFIG_PCI
294 extern int __init mpc52xx_add_bridge(struct de
295 extern void __init mpc52xx_setup_pci(void);
296 #else
297 static inline void mpc52xx_setup_pci(void) { }
298 #endif
299
300 #endif /* __ASSEMBLY__ */
301
302 #ifdef CONFIG_PM
303 struct mpc52xx_suspend {
304 void (*board_suspend_prepare)(void __i
305 void (*board_resume_finish)(void __iom
306 };
307
308 extern struct mpc52xx_suspend mpc52xx_suspend;
309 extern int __init mpc52xx_pm_init(void);
310 extern int mpc52xx_set_wakeup_gpio(u8 pin, u8
311
312 /* lite5200 calls mpc5200 suspend functions, s
313 extern int mpc52xx_pm_prepare(void);
314 extern int mpc52xx_pm_enter(suspend_state_t);
315 extern void mpc52xx_pm_finish(void);
316 extern char saved_sram[0x4000]; /* reuse buffe
317
318 #ifdef CONFIG_PPC_LITE5200
319 int __init lite5200_pm_init(void);
320 #endif
321 #endif /* CONFIG_PM */
322
323 #endif /* __ASM_POWERPC_MPC52xx_H__ */
324
325
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