1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 /*
3 * Contains the definition of registers common
4 * If a register definition has been changed i
5 * variant, we will case it in #ifndef XXX ...
6 * number used in the Programming Environments
7 * Implementations of the PowerPC Architecture
8 */
9
10 #ifndef _ASM_POWERPC_REG_H
11 #define _ASM_POWERPC_REG_H
12 #ifdef __KERNEL__
13
14 #include <linux/stringify.h>
15 #include <linux/const.h>
16 #include <asm/cputable.h>
17 #include <asm/asm-const.h>
18 #include <asm/feature-fixups.h>
19
20 /* Pickup Book E specific registers. */
21 #ifdef CONFIG_BOOKE
22 #include <asm/reg_booke.h>
23 #endif
24
25 #ifdef CONFIG_FSL_EMB_PERFMON
26 #include <asm/reg_fsl_emb.h>
27 #endif
28
29 #include <asm/reg_8xx.h>
30
31 #define MSR_SF_LG 63 /* Ena
32 #define MSR_HV_LG 60 /* Hyp
33 #define MSR_TS_T_LG 34 /* Tra
34 #define MSR_TS_S_LG 33 /* Tra
35 #define MSR_TS_LG 33 /* Tra
36 #define MSR_TM_LG 32 /* Tra
37 #define MSR_VEC_LG 25 /* Ena
38 #define MSR_VSX_LG 23 /* Ena
39 #define MSR_S_LG 22 /* Sec
40 #define MSR_POW_LG 18 /* Ena
41 #define MSR_WE_LG 18 /* Wai
42 #define MSR_TGPR_LG 17 /* TLB
43 #define MSR_CE_LG 17 /* Cri
44 #define MSR_ILE_LG 16 /* Int
45 #define MSR_EE_LG 15 /* Ext
46 #define MSR_PR_LG 14 /* Pro
47 #define MSR_FP_LG 13 /* Flo
48 #define MSR_ME_LG 12 /* Mac
49 #define MSR_FE0_LG 11 /* Flo
50 #define MSR_SE_LG 10 /* Sin
51 #define MSR_BE_LG 9 /* Bra
52 #define MSR_DE_LG 9 /* Deb
53 #define MSR_FE1_LG 8 /* Flo
54 #define MSR_IP_LG 6 /* Exc
55 #define MSR_IR_LG 5 /* Ins
56 #define MSR_DR_LG 4 /* Dat
57 #define MSR_PE_LG 3 /* Pro
58 #define MSR_PX_LG 2 /* Pro
59 #define MSR_PMM_LG 2 /* Per
60 #define MSR_RI_LG 1 /* Rec
61 #define MSR_LE_LG 0 /* Lit
62
63 #ifdef __ASSEMBLY__
64 #define __MASK(X) (1<<(X))
65 #else
66 #define __MASK(X) (1UL<<(X))
67 #endif
68
69 #ifdef CONFIG_PPC64
70 #define MSR_SF __MASK(MSR_SF_LG)
71 #define MSR_HV __MASK(MSR_HV_LG)
72 #define MSR_S __MASK(MSR_S_LG)
73 #else
74 /* so tests for these bits fail on 32-bit */
75 #define MSR_SF 0
76 #define MSR_HV 0
77 #define MSR_S 0
78 #endif
79
80 /*
81 * To be used in shared book E/book S, this av
82 * book S/book E in shared code
83 */
84 #ifndef MSR_SPE
85 #define MSR_SPE 0
86 #endif
87
88 #define MSR_VEC __MASK(MSR_VEC_LG)
89 #define MSR_VSX __MASK(MSR_VSX_LG)
90 #define MSR_POW __MASK(MSR_POW_LG)
91 #define MSR_WE __MASK(MSR_WE_LG)
92 #define MSR_TGPR __MASK(MSR_TGPR_LG)
93 #define MSR_CE __MASK(MSR_CE_LG)
94 #define MSR_ILE __MASK(MSR_ILE_LG)
95 #define MSR_EE __MASK(MSR_EE_LG)
96 #define MSR_PR __MASK(MSR_PR_LG)
97 #define MSR_FP __MASK(MSR_FP_LG)
98 #define MSR_ME __MASK(MSR_ME_LG)
99 #define MSR_FE0 __MASK(MSR_FE0_LG)
100 #define MSR_SE __MASK(MSR_SE_LG)
101 #define MSR_BE __MASK(MSR_BE_LG)
102 #define MSR_DE __MASK(MSR_DE_LG)
103 #define MSR_FE1 __MASK(MSR_FE1_LG)
104 #define MSR_IP __MASK(MSR_IP_LG)
105 #define MSR_IR __MASK(MSR_IR_LG)
106 #define MSR_DR __MASK(MSR_DR_LG)
107 #define MSR_PE __MASK(MSR_PE_LG)
108 #define MSR_PX __MASK(MSR_PX_LG)
109 #ifndef MSR_PMM
110 #define MSR_PMM __MASK(MSR_PMM_LG)
111 #endif
112 #define MSR_RI __MASK(MSR_RI_LG)
113 #define MSR_LE __MASK(MSR_LE_LG)
114
115 #define MSR_TM __MASK(MSR_TM_LG)
116 #define MSR_TS_N 0
117 #define MSR_TS_S __MASK(MSR_TS_S_LG)
118 #define MSR_TS_T __MASK(MSR_TS_T_LG)
119 #define MSR_TS_MASK (MSR_TS_T | MSR_TS_S)
120 #define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) ==
121 #define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS
122 #define MSR_TM_SUSPENDED(x) (((x) & MSR_TS
123
124 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
125 #define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK)
126 #else
127 #define MSR_TM_ACTIVE(x) ((void)(x), 0)
128 #endif
129
130 #if defined(CONFIG_PPC_BOOK3S_64)
131 #define MSR_64BIT MSR_SF
132
133 /* Server variant */
134 #define __MSR (MSR_ME | MSR_RI | MSR
135 #ifdef __BIG_ENDIAN__
136 #define MSR_ __MSR
137 #define MSR_IDLE (MSR_ME | MSR_SF | MSR
138 #else
139 #define MSR_ (__MSR | MSR_LE)
140 #define MSR_IDLE (MSR_ME | MSR_SF | MSR
141 #endif
142 #define MSR_KERNEL (MSR_ | MSR_64BIT)
143 #define MSR_USER32 (MSR_ | MSR_PR | MSR_E
144 #define MSR_USER64 (MSR_USER32 | MSR_64BI
145 #elif defined(CONFIG_PPC_BOOK3S_32) || defined
146 /* Default MSR for kernel mode. */
147 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|
148 #define MSR_USER (MSR_KERNEL|MSR_PR|MSR
149 #endif
150
151 #ifndef MSR_64BIT
152 #define MSR_64BIT 0
153 #endif
154
155 /* Condition Register related */
156 #define CR0_SHIFT 28
157 #define CR0_MASK 0xF
158 #define CR0_TBEGIN_FAILURE (0x2 << 28) /*
159
160
161 /* Power Management - Processor Stop Status an
162 #define PSSCR_RL_MASK 0x0000000F /*
163 #define PSSCR_MTL_MASK 0x000000F0 /*
164 #define PSSCR_TR_MASK 0x00000300 /*
165 #define PSSCR_PSLL_MASK 0x000F0000 /*
166 #define PSSCR_EC 0x00100000 /*
167 #define PSSCR_ESL 0x00200000 /*
168 #define PSSCR_SD 0x00400000 /*
169 #define PSSCR_PLS 0xf000000000000000 /*
170 #define PSSCR_PLS_SHIFT 60
171 #define PSSCR_GUEST_VIS 0xf0000000000003ffUL /
172 #define PSSCR_FAKE_SUSPEND 0x00000400 /*
173 #define PSSCR_FAKE_SUSPEND_LG 10 /*
174
175 /* Floating Point Status and Control Register
176 #define FPSCR_FX 0x80000000 /* FPU
177 #define FPSCR_FEX 0x40000000 /* FPU
178 #define FPSCR_VX 0x20000000 /* Inv
179 #define FPSCR_OX 0x10000000 /* Ove
180 #define FPSCR_UX 0x08000000 /* Und
181 #define FPSCR_ZX 0x04000000 /* Zer
182 #define FPSCR_XX 0x02000000 /* Ine
183 #define FPSCR_VXSNAN 0x01000000 /* Inv
184 #define FPSCR_VXISI 0x00800000 /* Inv
185 #define FPSCR_VXIDI 0x00400000 /* Inv
186 #define FPSCR_VXZDZ 0x00200000 /* Inv
187 #define FPSCR_VXIMZ 0x00100000 /* Inv
188 #define FPSCR_VXVC 0x00080000 /* Inv
189 #define FPSCR_FR 0x00040000 /* Fra
190 #define FPSCR_FI 0x00020000 /* Fra
191 #define FPSCR_FPRF 0x0001f000 /* FPU
192 #define FPSCR_FPCC 0x0000f000 /* FPU
193 #define FPSCR_VXSOFT 0x00000400 /* Inv
194 #define FPSCR_VXSQRT 0x00000200 /* Inv
195 #define FPSCR_VXCVI 0x00000100 /* Inv
196 #define FPSCR_VE 0x00000080 /* Inv
197 #define FPSCR_OE 0x00000040 /* IEE
198 #define FPSCR_UE 0x00000020 /* IEE
199 #define FPSCR_ZE 0x00000010 /* IEE
200 #define FPSCR_XE 0x00000008 /* FP
201 #define FPSCR_NI 0x00000004 /* FPU
202 #define FPSCR_RN 0x00000003 /* FPU
203
204 /* Bit definitions for SPEFSCR. */
205 #define SPEFSCR_SOVH 0x80000000 /* Sum
206 #define SPEFSCR_OVH 0x40000000 /* Int
207 #define SPEFSCR_FGH 0x20000000 /* Emb
208 #define SPEFSCR_FXH 0x10000000 /* Emb
209 #define SPEFSCR_FINVH 0x08000000 /* Emb
210 #define SPEFSCR_FDBZH 0x04000000 /* Emb
211 #define SPEFSCR_FUNFH 0x02000000 /* Emb
212 #define SPEFSCR_FOVFH 0x01000000 /* Emb
213 #define SPEFSCR_FINXS 0x00200000 /* Emb
214 #define SPEFSCR_FINVS 0x00100000 /* Emb
215 #define SPEFSCR_FDBZS 0x00080000 /* Emb
216 #define SPEFSCR_FUNFS 0x00040000 /* Emb
217 #define SPEFSCR_FOVFS 0x00020000 /* Emb
218 #define SPEFSCR_MODE 0x00010000 /* Emb
219 #define SPEFSCR_SOV 0x00008000 /* Int
220 #define SPEFSCR_OV 0x00004000 /* Int
221 #define SPEFSCR_FG 0x00002000 /* Emb
222 #define SPEFSCR_FX 0x00001000 /* Emb
223 #define SPEFSCR_FINV 0x00000800 /* Emb
224 #define SPEFSCR_FDBZ 0x00000400 /* Emb
225 #define SPEFSCR_FUNF 0x00000200 /* Emb
226 #define SPEFSCR_FOVF 0x00000100 /* Emb
227 #define SPEFSCR_FINXE 0x00000040 /* Emb
228 #define SPEFSCR_FINVE 0x00000020 /* Emb
229 #define SPEFSCR_FDBZE 0x00000010 /* Emb
230 #define SPEFSCR_FUNFE 0x00000008 /* Emb
231 #define SPEFSCR_FOVFE 0x00000004 /* Emb
232 #define SPEFSCR_FRMC 0x00000003 /* Emb
233
234 /* Special Purpose Registers (SPRNs)*/
235
236 #define SPRN_PID 0x030 /* Process ID
237 #ifdef CONFIG_BOOKE
238 #define SPRN_PID0 SPRN_PID/* Process ID
239 #endif
240
241 #define SPRN_CTR 0x009 /* Count Regis
242 #define SPRN_DSCR 0x11
243 #define SPRN_CFAR 0x1c /* Come From A
244 #define SPRN_AMR 0x1d /* Authority M
245 #define SPRN_UAMOR 0x9d /* User Author
246 #define SPRN_AMOR 0x15d /* Authority M
247 #define SPRN_ACOP 0x1F /* Available C
248 #define SPRN_TFIAR 0x81 /* Transaction
249 #define SPRN_TEXASR 0x82 /* Transaction
250 #define SPRN_TEXASRU 0x83 /* '' ''
251
252 #define TEXASR_FC_LG (63 - 7) /* Fai
253 #define TEXASR_AB_LG (63 - 31) /* Abo
254 #define TEXASR_SU_LG (63 - 32) /* Sus
255 #define TEXASR_HV_LG (63 - 34) /* Hyp
256 #define TEXASR_PR_LG (63 - 35) /* Pri
257 #define TEXASR_FS_LG (63 - 36) /* fai
258 #define TEXASR_EX_LG (63 - 37) /* TFI
259 #define TEXASR_ROT_LG (63 - 38) /* ROT
260
261 #define TEXASR_ABORT __MASK(TEXASR_AB_LG) /
262 #define TEXASR_SUSP __MASK(TEXASR_SU_LG) /
263 #define TEXASR_HV __MASK(TEXASR_HV_LG) /
264 #define TEXASR_PR __MASK(TEXASR_PR_LG) /
265 #define TEXASR_FS __MASK(TEXASR_FS_LG) /
266 #define TEXASR_EXACT __MASK(TEXASR_EX_LG) /
267 #define TEXASR_ROT __MASK(TEXASR_ROT_LG)
268 #define TEXASR_FC (ASM_CONST(0xFF) << TE
269
270 #define SPRN_TFHAR 0x80 /* Transaction
271
272 #define SPRN_TIDR 144 /* Thread ID r
273 #define SPRN_CTRLF 0x088
274 #define SPRN_CTRLT 0x098
275 #define CTRL_CT 0xc0000000 /* cur
276 #define CTRL_CT0 0x80000000 /* thr
277 #define CTRL_CT1 0x40000000 /* thr
278 #define CTRL_TE 0x00c00000 /* thr
279 #define CTRL_RUNLATCH 0x1
280 #define SPRN_DAWR0 0xB4
281 #define SPRN_DAWR1 0xB5
282 #define SPRN_RPR 0xBA /* Relative Pr
283 #define SPRN_CIABR 0xBB
284 #define CIABR_PRIV 0x3
285 #define CIABR_PRIV_USER 1
286 #define CIABR_PRIV_SUPER 2
287 #define CIABR_PRIV_HYPER 3
288 #define SPRN_DAWRX0 0xBC
289 #define SPRN_DAWRX1 0xBD
290 #define DAWRX_USER __MASK(0)
291 #define DAWRX_KERNEL __MASK(1)
292 #define DAWRX_HYP __MASK(2)
293 #define DAWRX_WTI __MASK(3)
294 #define DAWRX_WT __MASK(4)
295 #define DAWRX_DR __MASK(5)
296 #define DAWRX_DW __MASK(6)
297 #define SPRN_DABR 0x3F5 /* Data Addres
298 #define SPRN_DABR2 0x13D /* e300 */
299 #define SPRN_DABRX 0x3F7 /* Data Addres
300 #define DABRX_USER __MASK(0)
301 #define DABRX_KERNEL __MASK(1)
302 #define DABRX_HYP __MASK(2)
303 #define DABRX_BTI __MASK(3)
304 #define DABRX_ALL (DABRX_BTI | DABRX_HYP
305 #define SPRN_DAR 0x013 /* Data Addres
306 #define SPRN_DBCR 0x136 /* e300 Data B
307 #define SPRN_DSISR 0x012 /* Data Storag
308 #define DSISR_BAD_DIRECT_ST 0x80000000 /*
309 #define DSISR_NOHPTE 0x40000000 /*
310 #define DSISR_ATTR_CONFLICT 0x20000000 /*
311 #define DSISR_NOEXEC_OR_G 0x10000000 /*
312 #define DSISR_PROTFAULT 0x08000000 /*
313 #define DSISR_BADACCESS 0x04000000 /*
314 #define DSISR_ISSTORE 0x02000000 /*
315 #define DSISR_DABRMATCH 0x00400000 /*
316 #define DSISR_NOSEGMENT 0x00200000 /*
317 #define DSISR_KEYFAULT 0x00200000 /*
318 #define DSISR_BAD_EXT_CTRL 0x00100000 /*
319 #define DSISR_UNSUPP_MMU 0x00080000 /*
320 #define DSISR_SET_RC 0x00040000 /*
321 #define DSISR_PRTABLE_FAULT 0x00020000 /*
322 #define DSISR_ICSWX_NO_CT 0x00004000 /*
323 #define DSISR_BAD_COPYPASTE 0x00000008 /*
324 #define DSISR_BAD_AMO 0x00000004 /*
325 #define DSISR_BAD_CI_LDST 0x00000002 /*
326
327 /*
328 * DSISR_NOEXEC_OR_G doesn't actually exist. T
329 * 0 on DSIs. However, on ISIs, the correspond
330 * indicates an attempt at executing from a no
331 * or segment or from a guarded page.
332 *
333 * We add a definition here for completeness a
334 * DSISR and SRR1 in do_page_fault.
335 */
336
337 /*
338 * DSISR bits that are treated as a fault. Any
339 * here will skip hash_page, and cause do_page
340 * trigger a SIGBUS or SIGSEGV:
341 */
342 #define DSISR_BAD_FAULT_32S (DSISR_BAD_DIR
343 DSISR_BADACCE
344 DSISR_BAD_EXT
345 #define DSISR_BAD_FAULT_64S (DSISR_BAD_FAU
346 DSISR_ATTR_CO
347 DSISR_UNSUPP_
348 DSISR_PRTABLE
349 DSISR_ICSWX_N
350 DSISR_BAD_COP
351 DSISR_BAD_AMO
352 DSISR_BAD_CI_
353 /*
354 * These bits are equivalent in SRR1 and DSISR
355 * instruction access interrupts on Book3S
356 */
357 #define DSISR_SRR1_MATCH_32S (DSISR_NOHPTE
358 DSISR_NOEXEC_
359 DSISR_PROTFAU
360 #define DSISR_SRR1_MATCH_64S (DSISR_SRR1_MA
361 DSISR_KEYFAUL
362 DSISR_UNSUPP_
363 DSISR_SET_RC
364 DSISR_PRTABLE
365
366 #define SPRN_TBRL 0x10C /* Time Base R
367 #define SPRN_TBRU 0x10D /* Time Base R
368 #define SPRN_CIR 0x11B /* Chip Inform
369 #define SPRN_TBWL 0x11C /* Time Base L
370 #define SPRN_TBWU 0x11D /* Time Base U
371 #define SPRN_TBU40 0x11E /* Timebase up
372 #define SPRN_SPURR 0x134 /* Scaled PURR
373 #define SPRN_HSPRG0 0x130 /* Hypervisor
374 #define SPRN_HSPRG1 0x131 /* Hypervisor
375 #define SPRN_HDSISR 0x132
376 #define SPRN_HDAR 0x133
377 #define SPRN_HDEC 0x136 /* Hypervisor
378 #define SPRN_HIOR 0x137 /* 970 Hypervi
379 #define SPRN_RMOR 0x138 /* Real mode o
380 #define SPRN_HRMOR 0x139 /* Real mode o
381 #define SPRN_HDEXCR_RO 0x1C7 /* Hypervisor
382 #define SPRN_HASHKEYR 0x1D4 /* Non-privile
383 #define SPRN_HDEXCR 0x1D7 /* Hypervisor
384 #define SPRN_DEXCR_RO 0x32C /* DEXCR (non-
385 #define SPRN_ASDR 0x330 /* Access segm
386 #define SPRN_DEXCR 0x33C /* Dynamic exe
387 #define DEXCR_PR_SBHE 0x80000000UL /* 0: S
388 #define DEXCR_PR_IBRTPD 0x10000000UL /* 3: I
389 #define DEXCR_PR_SRAPD 0x08000000UL /* 4: S
390 #define DEXCR_PR_NPHIE 0x04000000UL /* 5: N
391 #define DEXCR_INIT DEXCR_PR_NPHIE /* Fix
392 #define SPRN_IC 0x350 /* Virtual Ins
393 #define SPRN_VTB 0x351 /* Virtual Tim
394 #define SPRN_LDBAR 0x352 /* LD Base Add
395 #define SPRN_PMICR 0x354 /* Power Manag
396 #define SPRN_PMSR 0x355 /* Power Manag
397 #define SPRN_PMMAR 0x356 /* Power Manag
398 #define SPRN_PSSCR 0x357 /* Processor S
399 #define SPRN_PSSCR_PR 0x337 /* PSSCR ISA 3
400 #define SPRN_TRIG2 0x372
401 #define SPRN_PMCR 0x374 /* Power Manag
402 #define SPRN_RWMR 0x375 /* Region-Weig
403
404 /* HFSCR and FSCR bit numbers are the same */
405 #define FSCR_PREFIX_LG 13 /* Enable Pref
406 #define FSCR_SCV_LG 12 /* Enable Syst
407 #define FSCR_MSGP_LG 10 /* Enable MSGP
408 #define FSCR_TAR_LG 8 /* Enable Targ
409 #define FSCR_EBB_LG 7 /* Enable Even
410 #define FSCR_TM_LG 5 /* Enable Tran
411 #define FSCR_BHRB_LG 4 /* Enable Bran
412 #define FSCR_PM_LG 3 /* Enable prob
413 #define FSCR_DSCR_LG 2 /* Enable Data
414 #define FSCR_VECVSX_LG 1 /* Enable VMX/
415 #define FSCR_FP_LG 0 /* Enable Floa
416 #define SPRN_FSCR 0x099 /* Facility St
417 #define FSCR_PREFIX __MASK(FSCR_PREFIX_LG)
418 #define FSCR_SCV __MASK(FSCR_SCV_LG)
419 #define FSCR_TAR __MASK(FSCR_TAR_LG)
420 #define FSCR_EBB __MASK(FSCR_EBB_LG)
421 #define FSCR_DSCR __MASK(FSCR_DSCR_LG)
422 #define FSCR_INTR_CAUSE (ASM_CONST(0xFF) <<
423 #define SPRN_HFSCR 0xbe /* HV=1 Facili
424 #define HFSCR_PREFIX __MASK(FSCR_PREFIX_LG)
425 #define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
426 #define HFSCR_TAR __MASK(FSCR_TAR_LG)
427 #define HFSCR_EBB __MASK(FSCR_EBB_LG)
428 #define HFSCR_TM __MASK(FSCR_TM_LG)
429 #define HFSCR_PM __MASK(FSCR_PM_LG)
430 #define HFSCR_BHRB __MASK(FSCR_BHRB_LG)
431 #define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
432 #define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
433 #define HFSCR_FP __MASK(FSCR_FP_LG)
434 #define HFSCR_INTR_CAUSE FSCR_INTR_CAUSE
435 #define SPRN_TAR 0x32f /* Target Addr
436 #define SPRN_LPCR 0x13E /* LPAR Contro
437 #define LPCR_VPM0 ASM_CONST(0x80
438 #define LPCR_VPM1 ASM_CONST(0x40
439 #define LPCR_ISL ASM_CONST(0x20
440 #define LPCR_VC_SH 61
441 #define LPCR_DPFD_SH 52
442 #define LPCR_DPFD (ASM_CONST(7)
443 #define LPCR_VRMASD_SH 47
444 #define LPCR_VRMASD (ASM_CONST(0x1
445 #define LPCR_VRMA_L ASM_CONST(0x00
446 #define LPCR_VRMA_LP0 ASM_CONST(0x00
447 #define LPCR_VRMA_LP1 ASM_CONST(0x00
448 #define LPCR_RMLS 0x1C000000
449 #define LPCR_RMLS_SH 26
450 #define LPCR_HAIL ASM_CONST(0x00
451 #define LPCR_ILE ASM_CONST(0x00
452 #define LPCR_AIL ASM_CONST(0x00
453 #define LPCR_AIL_0 ASM_CONST(0x00
454 #define LPCR_AIL_3 ASM_CONST(0x00
455 #define LPCR_ONL ASM_CONST(0x00
456 #define LPCR_LD ASM_CONST(0x00
457 #define LPCR_PECE ASM_CONST(0x00
458 #define LPCR_PECEDP ASM_CONST(0x0000000000
459 #define LPCR_PECEDH ASM_CONST(0x0000000000
460 #define LPCR_PECE0 ASM_CONST(0x00
461 #define LPCR_PECE1 ASM_CONST(0x00
462 #define LPCR_PECE2 ASM_CONST(0x00
463 #define LPCR_PECE_HVEE ASM_CONST(0x00
464 #define LPCR_MER ASM_CONST(0x00
465 #define LPCR_MER_SH 11
466 #define LPCR_GTSE ASM_CONST(0x00
467 #define LPCR_TC ASM_CONST(0x00
468 #define LPCR_HEIC ASM_CONST(0x00
469 #define LPCR_LPES 0x0000000c
470 #define LPCR_LPES0 ASM_CONST(0x00
471 #define LPCR_LPES1 ASM_CONST(0x00
472 #define LPCR_LPES_SH 2
473 #define LPCR_RMI ASM_CONST(0x00
474 #define LPCR_HVICE ASM_CONST(0x00
475 #define LPCR_HDICE ASM_CONST(0x00
476 #define LPCR_UPRT ASM_CONST(0x00
477 #define LPCR_HR ASM_CONST(0x00
478 #ifndef SPRN_LPID
479 #define SPRN_LPID 0x13F /* Logical Par
480 #endif
481 #define SPRN_HMER 0x150 /* Hypervisor
482 #define HMER_DEBUG_TRIG (1ul << (63 -
483 #define SPRN_HMEER 0x151 /* Hyp mainten
484 #define SPRN_PCR 0x152 /* Processor c
485 #define PCR_VEC_DIS (__MASK(63-0)) /* Vec
486 #define PCR_VSX_DIS (__MASK(63-1)) /* VSX
487 #define PCR_TM_DIS (__MASK(63-2)) /* Tra
488 #define PCR_MMA_DIS (__MASK(63-3)) /* Matr
489 #define PCR_HIGH_BITS (PCR_MMA_DIS | PCR_VEC
490 /*
491 * These bits are used in the function kvmppc_
492 * determine both the compatibility level whic
493 * compatibility level which the host is capab
494 */
495 #define PCR_ARCH_300 0x10 /* Arc
496 #define PCR_ARCH_207 0x8 /* Arc
497 #define PCR_ARCH_206 0x4 /* Arc
498 #define PCR_ARCH_205 0x2 /* Arc
499 #define PCR_LOW_BITS (PCR_ARCH_207 | PCR_AR
500 #define PCR_MASK ~(PCR_HIGH_BITS | PCR_
501 #define SPRN_HEIR 0x153 /* Hypervisor
502 #define SPRN_TLBINDEXR 0x154 /* P7 TLB cont
503 #define SPRN_TLBVPNR 0x155 /* P7 TLB cont
504 #define SPRN_TLBRPNR 0x156 /* P7 TLB cont
505 #define SPRN_TLBLPIDR 0x157 /* P7 TLB cont
506 #define SPRN_DBAT0L 0x219 /* Data BAT 0
507 #define SPRN_DBAT0U 0x218 /* Data BAT 0
508 #define SPRN_DBAT1L 0x21B /* Data BAT 1
509 #define SPRN_DBAT1U 0x21A /* Data BAT 1
510 #define SPRN_DBAT2L 0x21D /* Data BAT 2
511 #define SPRN_DBAT2U 0x21C /* Data BAT 2
512 #define SPRN_DBAT3L 0x21F /* Data BAT 3
513 #define SPRN_DBAT3U 0x21E /* Data BAT 3
514 #define SPRN_DBAT4L 0x239 /* Data BAT 4
515 #define SPRN_DBAT4U 0x238 /* Data BAT 4
516 #define SPRN_DBAT5L 0x23B /* Data BAT 5
517 #define SPRN_DBAT5U 0x23A /* Data BAT 5
518 #define SPRN_DBAT6L 0x23D /* Data BAT 6
519 #define SPRN_DBAT6U 0x23C /* Data BAT 6
520 #define SPRN_DBAT7L 0x23F /* Data BAT 7
521 #define SPRN_DBAT7U 0x23E /* Data BAT 7
522 #define SPRN_PPR 0x380 /* SMT Thread
523 #define SPRN_TSCR 0x399 /* Thread Swit
524
525 #define SPRN_DEC 0x016 /* Dec
526 #define SPRN_PIT 0x3DB /* Pro
527
528 #define SPRN_DER 0x095 /* Deb
529 #define DER_RSTE 0x40000000 /* Res
530 #define DER_CHSTPE 0x20000000 /* Che
531 #define DER_MCIE 0x10000000 /* Mac
532 #define DER_EXTIE 0x02000000 /* Ext
533 #define DER_ALIE 0x01000000 /* Ali
534 #define DER_PRIE 0x00800000 /* Pro
535 #define DER_FPUVIE 0x00400000 /* FP
536 #define DER_DECIE 0x00200000 /* Dec
537 #define DER_SYSIE 0x00040000 /* Sys
538 #define DER_TRE 0x00020000 /* Tra
539 #define DER_SEIE 0x00004000 /* FP
540 #define DER_ITLBMSE 0x00002000 /* Imp
541 #define DER_ITLBERE 0x00001000 /* Imp
542 #define DER_DTLBMSE 0x00000800 /* Imp
543 #define DER_DTLBERE 0x00000400 /* Imp
544 #define DER_LBRKE 0x00000008 /* Loa
545 #define DER_IBRKE 0x00000004 /* Ins
546 #define DER_EBRKE 0x00000002 /* Ext
547 #define DER_DPIE 0x00000001 /* Dev
548 #define SPRN_DMISS 0x3D0 /* Dat
549 #define SPRN_DHDES 0x0B1 /* Dir
550 #define SPRN_DPDES 0x0B0 /* Dir
551 #define SPRN_EAR 0x11A /* Ext
552 #define SPRN_HASH1 0x3D2 /* Pri
553 #define SPRN_HASH2 0x3D3 /* Sec
554 #define SPRN_HID0 0x3F0 /* Har
555 #define HID0_HDICE_SH (63 - 23) /* 970
556 #define HID0_EMCP (1<<31) /* Ena
557 #define HID0_EBA (1<<29) /* Ena
558 #define HID0_EBD (1<<28) /* Ena
559 #define HID0_SBCLK (1<<27)
560 #define HID0_EICE (1<<26)
561 #define HID0_TBEN (1<<26) /* Tim
562 #define HID0_ECLK (1<<25)
563 #define HID0_PAR (1<<24)
564 #define HID0_STEN (1<<24) /* Sof
565 #define HID0_HIGH_BAT (1<<23) /* Ena
566 #define HID0_DOZE (1<<23)
567 #define HID0_NAP (1<<22)
568 #define HID0_SLEEP (1<<21)
569 #define HID0_DPM (1<<20)
570 #define HID0_BHTCLR (1<<18) /* Cle
571 #define HID0_XAEN (1<<17) /* Ext
572 #define HID0_NHR (1<<16) /* Not
573 #define HID0_ICE (1<<15) /* Ins
574 #define HID0_DCE (1<<14) /* Dat
575 #define HID0_ILOCK (1<<13) /* Ins
576 #define HID0_DLOCK (1<<12) /* Dat
577 #define HID0_ICFI (1<<11) /* Ins
578 #define HID0_DCI (1<<10) /* Dat
579 #define HID0_SPD (1<<9) /* Spe
580 #define HID0_DAPUEN (1<<8) /* Deb
581 #define HID0_SGE (1<<7) /* Sto
582 #define HID0_SIED (1<<7) /* Ser
583 #define HID0_DCFA (1<<6) /* Dat
584 #define HID0_LRSTK (1<<4) /* Lin
585 #define HID0_BTIC (1<<5) /* Bra
586 #define HID0_ABE (1<<3) /* Add
587 #define HID0_FOLD (1<<3) /* Bra
588 #define HID0_BHTE (1<<2) /* Bra
589 #define HID0_BTCD (1<<1) /* Bra
590 #define HID0_NOPDST (1<<1) /* No-
591 #define HID0_NOPTI (1<<0) /* No-
592 /* POWER8 HID0 bits */
593 #define HID0_POWER8_4LPARMODE __MASK(61)
594 #define HID0_POWER8_2LPARMODE __MASK(57)
595 #define HID0_POWER8_1TO2LPAR __MASK(52)
596 #define HID0_POWER8_1TO4LPAR __MASK(51)
597 #define HID0_POWER8_DYNLPARDIS __MASK(48)
598
599 /* POWER9 HID0 bits */
600 #define HID0_POWER9_RADIX __MASK(63 - 8)
601
602 #define SPRN_HID1 0x3F1 /* Har
603 #ifdef CONFIG_PPC_BOOK3S_32
604 #define HID1_EMCP (1<<31) /* 745
605 #define HID1_DFS (1<<22) /* 744
606 #define HID1_PC0 (1<<16) /* 745
607 #define HID1_PC1 (1<<15) /* 745
608 #define HID1_PC2 (1<<14) /* 745
609 #define HID1_PC3 (1<<13) /* 745
610 #define HID1_SYNCBE (1<<11) /* 745
611 #define HID1_ABE (1<<10) /* 745
612 #define HID1_PS (1<<16) /* 750
613 #endif
614 #define SPRN_HID2_750FX 0x3F8 /* IBM
615 #define SPRN_HID2_GEKKO 0x398 /* Gek
616 #define SPRN_HID2_G2_LE 0x3F3 /* G2_
617 #define HID2_G2_LE_HBE (1<<18) /* Hig
618 #define SPRN_IABR 0x3F2 /* Instruction
619 #define SPRN_IABR2 0x3FA /* 83x
620 #define SPRN_IBCR 0x135 /* 83x
621 #define SPRN_IAMR 0x03D /* Ins
622 #define SPRN_HID4 0x3F4 /* 970
623 #define HID4_LPES0 (1ul << (63-0)) /* LP
624 #define HID4_RMLS2_SH (63 - 2) /* Rea
625 #define HID4_LPID5_SH (63 - 6) /* par
626 #define HID4_RMOR_SH (63 - 22) /* rea
627 #define HID4_RMOR (0xFFFFul << HID4_RMO
628 #define HID4_LPES1 (1 << (63-57)) /* LPA
629 #define HID4_RMLS0_SH (63 - 58) /* Rea
630 #define HID4_LPID1_SH 0 /* par
631 #define SPRN_HID4_GEKKO 0x3F3 /* Gek
632 #define SPRN_HID5 0x3F6 /* 970
633 #define SPRN_HID6 0x3F9 /* BE HID 6 */
634 #define HID6_LB (0x0F<<12) /* Concurre
635 #define HID6_DLP (1<<20) /* Disable all
636 #define SPRN_TSC_CELL 0x399 /* Thread swit
637 #define TSC_CELL_DEC_ENABLE_0 0x400000 /* De
638 #define TSC_CELL_DEC_ENABLE_1 0x200000 /* De
639 #define TSC_CELL_EE_ENABLE 0x100000 /* Ex
640 #define TSC_CELL_EE_BOOST 0x080000 /* Ex
641 #define SPRN_TSC 0x3FD /* Thread swit
642 #define SPRN_TST 0x3FC /* Thread swit
643 #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
644 #define SPRN_IAC1 0x3F4 /* Ins
645 #define SPRN_IAC2 0x3F5 /* Ins
646 #endif
647 #define SPRN_IBAT0L 0x211 /* Ins
648 #define SPRN_IBAT0U 0x210 /* Ins
649 #define SPRN_IBAT1L 0x213 /* Ins
650 #define SPRN_IBAT1U 0x212 /* Ins
651 #define SPRN_IBAT2L 0x215 /* Ins
652 #define SPRN_IBAT2U 0x214 /* Ins
653 #define SPRN_IBAT3L 0x217 /* Ins
654 #define SPRN_IBAT3U 0x216 /* Ins
655 #define SPRN_IBAT4L 0x231 /* Ins
656 #define SPRN_IBAT4U 0x230 /* Ins
657 #define SPRN_IBAT5L 0x233 /* Ins
658 #define SPRN_IBAT5U 0x232 /* Ins
659 #define SPRN_IBAT6L 0x235 /* Ins
660 #define SPRN_IBAT6U 0x234 /* Ins
661 #define SPRN_IBAT7L 0x237 /* Ins
662 #define SPRN_IBAT7U 0x236 /* Ins
663 #define SPRN_ICMP 0x3D5 /* Ins
664 #define SPRN_ICTC 0x3FB /* Instruction
665 #ifndef SPRN_ICTRL
666 #define SPRN_ICTRL 0x3F3 /* 1011 7450 i
667 #endif
668 #define ICTRL_EICE 0x08000000 /* ena
669 #define ICTRL_EDC 0x04000000 /* ena
670 #define ICTRL_EICP 0x00000100 /* ena
671 #define SPRN_IMISS 0x3D4 /* Ins
672 #define SPRN_IMMR 0x27E /* Int
673 #define SPRN_L2CR 0x3F9 /* Lev
674 #define SPRN_L2CR2 0x3f8
675 #define L2CR_L2E 0x80000000
676 #define L2CR_L2PE 0x40000000
677 #define L2CR_L2SIZ_MASK 0x30000000
678 #define L2CR_L2SIZ_256KB 0x10000000
679 #define L2CR_L2SIZ_512KB 0x20000000
680 #define L2CR_L2SIZ_1MB 0x30000000
681 #define L2CR_L2CLK_MASK 0x0e000000
682 #define L2CR_L2CLK_DISABLED 0x00000000
683 #define L2CR_L2CLK_DIV1 0x02000000
684 #define L2CR_L2CLK_DIV1_5 0x04000000
685 #define L2CR_L2CLK_DIV2 0x08000000
686 #define L2CR_L2CLK_DIV2_5 0x0a000000
687 #define L2CR_L2CLK_DIV3 0x0c000000
688 #define L2CR_L2RAM_MASK 0x01800000
689 #define L2CR_L2RAM_FLOW 0x00000000
690 #define L2CR_L2RAM_PIPE 0x01000000
691 #define L2CR_L2RAM_PIPE_LW 0x01800000
692 #define L2CR_L2DO 0x00400000
693 #define L2CR_L2I 0x00200000
694 #define L2CR_L2CTL 0x00100000
695 #define L2CR_L2WT 0x00080000
696 #define L2CR_L2TS 0x00040000
697 #define L2CR_L2OH_MASK 0x00030000
698 #define L2CR_L2OH_0_5 0x00000000
699 #define L2CR_L2OH_1_0 0x00010000
700 #define L2CR_L2SL 0x00008000
701 #define L2CR_L2DF 0x00004000
702 #define L2CR_L2BYP 0x00002000
703 #define L2CR_L2IP 0x00000001
704 #define L2CR_L2IO_745x 0x00100000
705 #define L2CR_L2DO_745x 0x00010000
706 #define L2CR_L2REP_745x 0x00001000
707 #define L2CR_L2HWF_745x 0x00000800
708 #define SPRN_L3CR 0x3FA /* Lev
709 #define L3CR_L3E 0x80000000
710 #define L3CR_L3PE 0x40000000
711 #define L3CR_L3APE 0x20000000
712 #define L3CR_L3SIZ 0x10000000
713 #define L3CR_L3CLKEN 0x08000000
714 #define L3CR_L3RES 0x04000000
715 #define L3CR_L3CLKDIV 0x03800000
716 #define L3CR_L3IO 0x00400000
717 #define L3CR_L3SPO 0x00040000
718 #define L3CR_L3CKSP 0x00030000
719 #define L3CR_L3PSP 0x0000e000
720 #define L3CR_L3REP 0x00001000
721 #define L3CR_L3HWF 0x00000800
722 #define L3CR_L3I 0x00000400
723 #define L3CR_L3RT 0x00000300
724 #define L3CR_L3NIRCA 0x00000080
725 #define L3CR_L3DO 0x00000040
726 #define L3CR_PMEN 0x00000004
727 #define L3CR_PMSIZ 0x00000001
728
729 #define SPRN_MSSCR0 0x3f6 /* Memory Subs
730 #define SPRN_MSSSR0 0x3f7 /* Memory Subs
731 #define SPRN_LDSTCR 0x3f8 /* Load/Store
732 #define SPRN_LDSTDB 0x3f4 /* */
733 #define SPRN_LR 0x008 /* Link Regist
734 #ifndef SPRN_PIR
735 #define SPRN_PIR 0x3FF /* Processor I
736 #endif
737 #define SPRN_TIR 0x1BE /* Thread Iden
738 #define SPRN_PTCR 0x1D0 /* Partition t
739 #define SPRN_PSPB 0x09F /* Problem Sta
740 #define SPRN_PTEHI 0x3D5 /* 981 7450 PT
741 #define SPRN_PTELO 0x3D6 /* 982 7450 PT
742 #define SPRN_PURR 0x135 /* Processor U
743 #define SPRN_PVR 0x11F /* Processor V
744 #define SPRN_RPA 0x3D6 /* Required Ph
745 #define SPRN_SDA 0x3BF /* Sampled Dat
746 #define SPRN_SDR1 0x019 /* MMU Hash Ba
747 #define SPRN_ASR 0x118 /* Address Spa
748 #define SPRN_SIA 0x3BB /* Sampled Ins
749 #define SPRN_SPRG0 0x110 /* Special Pur
750 #define SPRN_SPRG1 0x111 /* Special Pur
751 #define SPRN_SPRG2 0x112 /* Special Pur
752 #define SPRN_SPRG3 0x113 /* Special Pur
753 #define SPRN_USPRG3 0x103 /* SPRG3 users
754 #define SPRN_SPRG4 0x114 /* Special Pur
755 #define SPRN_USPRG4 0x104 /* SPRG4 users
756 #define SPRN_SPRG5 0x115 /* Special Pur
757 #define SPRN_USPRG5 0x105 /* SPRG5 users
758 #define SPRN_SPRG6 0x116 /* Special Pur
759 #define SPRN_USPRG6 0x106 /* SPRG6 users
760 #define SPRN_SPRG7 0x117 /* Special Pur
761 #define SPRN_USPRG7 0x107 /* SPRG7 users
762 #define SPRN_SRR0 0x01A /* Save/Restor
763 #define SPRN_SRR1 0x01B /* Save/Restor
764
765 #ifdef CONFIG_PPC_BOOK3S
766 /*
767 * Bits loaded from MSR upon interrupt.
768 * PPC (64-bit) bits 33-36,42-47 are interrupt
769 * loaded from MSR. The exception is that SRES
770 * bit 62 (RI) from MSR. Don't use PPC_BITMASK
771 * it.
772 */
773 #define SRR1_MSR_BITS (~0x783f0000UL
774 #endif
775
776 #define SRR1_ISI_NOPT 0x40000000 /*
777 #define SRR1_ISI_N_G_OR_CIP 0x10000000 /*
778 #define SRR1_ISI_PROT 0x08000000 /*
779 #define SRR1_WAKEMASK 0x00380000 /*
780 #define SRR1_WAKEMASK_P8 0x003c0000 /*
781 #define SRR1_WAKEMCE_RESVD 0x003c0000 /*
782 #define SRR1_WAKESYSERR 0x00300000 /*
783 #define SRR1_WAKEEE 0x00200000 /*
784 #define SRR1_WAKEHVI 0x00240000 /*
785 #define SRR1_WAKEMT 0x00280000 /*
786 #define SRR1_WAKEHMI 0x00280000 /*
787 #define SRR1_WAKEDEC 0x00180000 /*
788 #define SRR1_WAKEDBELL 0x00140000 /*
789 #define SRR1_WAKETHERM 0x00100000 /*
790 #define SRR1_WAKERESET 0x00100000 /*
791 #define SRR1_WAKEHDBELL 0x000c0000 /*
792 #define SRR1_WAKESTATE 0x00030000 /*
793 #define SRR1_WS_HVLOSS 0x00030000 /*
794 #define SRR1_WS_GPRLOSS 0x00020000 /*
795 #define SRR1_WS_NOLOSS 0x00010000 /*
796 #define SRR1_PROGTM 0x00200000 /*
797 #define SRR1_PROGFPE 0x00100000 /*
798 #define SRR1_PROGILL 0x00080000 /*
799 #define SRR1_PROGPRIV 0x00040000 /*
800 #define SRR1_PROGTRAP 0x00020000 /*
801 #define SRR1_PROGADDR 0x00010000 /*
802
803 #define SRR1_MCE_MCP 0x00080000 /*
804 #define SRR1_BOUNDARY 0x10000000 /*
805 #define SRR1_PREFIXED 0x20000000 /*
806
807 #define SPRN_HSRR0 0x13A /* Save/Restor
808 #define SPRN_HSRR1 0x13B /* Save/Restor
809 #define HSRR1_DENORM 0x00100000 /*
810 #define HSRR1_HISI_WRITE 0x00010000 /*
811
812 #define SPRN_TBCTL 0x35f /* PA6T Timeba
813 #define TBCTL_FREEZE 0x000000000000
814 #define TBCTL_RESTART 0x000000010000
815 #define TBCTL_UPDATE_UPPER 0x000000020000
816 #define TBCTL_UPDATE_LOWER 0x000000030000
817
818 #ifndef SPRN_SVR
819 #define SPRN_SVR 0x11E /* System Vers
820 #endif
821 #define SPRN_THRM1 0x3FC /* The
822 /* these bits were defined in inverted endian
823 #define THRM1_TIN (1 << 31)
824 #define THRM1_TIV (1 << 30)
825 #define THRM1_THRES(x) ((x&0x7f)<<23)
826 #define THRM3_SITV(x) ((x & 0x1fff) << 1)
827 #define THRM1_TID (1<<2)
828 #define THRM1_TIE (1<<1)
829 #define THRM1_V (1<<0)
830 #define SPRN_THRM2 0x3FD /* The
831 #define SPRN_THRM3 0x3FE /* The
832 #define THRM3_E (1<<0)
833 #define SPRN_TLBMISS 0x3D4 /* 980
834 #define SPRN_UMMCR0 0x3A8 /* User Monito
835 #define SPRN_UMMCR1 0x3AC /* User Monito
836 #define SPRN_UPMC1 0x3A9 /* User Perfor
837 #define SPRN_UPMC2 0x3AA /* User Perfor
838 #define SPRN_UPMC3 0x3AD /* User Perfor
839 #define SPRN_UPMC4 0x3AE /* User Perfor
840 #define SPRN_USIA 0x3AB /* User Sample
841 #define SPRN_VRSAVE 0x100 /* Vector Regi
842 #define SPRN_XER 0x001 /* Fixed Point
843
844 #define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monito
845 #define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monito
846 #define SPRN_PMC1_GEKKO 0x3B9 /* Gekko Perfor
847 #define SPRN_PMC2_GEKKO 0x3BA /* Gekko Perfor
848 #define SPRN_PMC3_GEKKO 0x3BD /* Gekko Perfor
849 #define SPRN_PMC4_GEKKO 0x3BE /* Gekko Perfor
850 #define SPRN_WPAR_GEKKO 0x399 /* Gekko Write
851
852 #define SPRN_SCOMC 0x114 /* SCOM Access
853 #define SPRN_SCOMD 0x115 /* SCOM Access
854
855 /* Performance monitor SPRs */
856 #ifdef CONFIG_PPC64
857 #define SPRN_MMCR0 795
858 #define MMCR0_FC 0x80000000UL /* freeze
859 #define MMCR0_FCS 0x40000000UL /* freeze
860 #define MMCR0_KERNEL_DISABLE MMCR0_FCS
861 #define MMCR0_FCP 0x20000000UL /* freeze
862 #define MMCR0_PROBLEM_DISABLE MMCR0_FCP
863 #define MMCR0_FCM1 0x10000000UL /* freeze
864 #define MMCR0_FCM0 0x08000000UL /* freeze
865 #define MMCR0_PMXE ASM_CONST(0x04000000)
866 #define MMCR0_FCECE ASM_CONST(0x02000000)
867 #define MMCR0_TBEE 0x00400000UL /* time b
868 #define MMCR0_BHRBA 0x00200000UL /* BHRB A
869 #define MMCR0_EBE 0x00100000UL /* Event
870 #define MMCR0_PMCC 0x000c0000UL /* PMC co
871 #define MMCR0_PMCCEXT ASM_CONST(0x00000200)
872 #define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6
873 #define MMCR0_PMC1CE 0x00008000UL /* PMC1 c
874 #define MMCR0_PMCjCE ASM_CONST(0x00004000)
875 #define MMCR0_TRIGGER 0x00002000UL /* TRIGGE
876 #define MMCR0_PMAO_SYNC ASM_CONST(0x00000800
877 #define MMCR0_C56RUN ASM_CONST(0x00000100)
878 /* performance monitor alert has occurred, set
879 #define MMCR0_PMAO ASM_CONST(0x00000080)
880 #define MMCR0_SHRFC 0x00000040UL /* SHRre
881 #define MMCR0_FC56 0x00000010UL /* freeze
882 #define MMCR0_FCTI 0x00000008UL /* freeze
883 #define MMCR0_FCTA 0x00000004UL /* freeze
884 #define MMCR0_FCWAIT 0x00000002UL /* freeze
885 #define MMCR0_FCHV 0x00000001UL /* freeze
886 #define SPRN_MMCR1 798
887 #define SPRN_MMCR2 785
888 #define SPRN_MMCR3 754
889 #define SPRN_UMMCR2 769
890 #define SPRN_UMMCR3 738
891 #define SPRN_MMCRA 0x312
892 #define MMCRA_SDSYNC 0x80000000UL /* SDAR s
893 #define MMCRA_SDAR_DCACHE_MISS 0x40000000UL
894 #define MMCRA_SDAR_ERAT_MISS 0x20000000UL
895 #define MMCRA_SIHV 0x10000000UL /* state
896 #define MMCRA_SIPR 0x08000000UL /* state
897 #define MMCRA_SLOT 0x07000000UL /* SLOT b
898 #define MMCRA_SLOT_SHIFT 24
899 #define MMCRA_SAMPLE_ENABLE 0x00000001UL /*
900 #define MMCRA_BHRB_DISABLE _UL(0x2000000000
901 #define POWER6_MMCRA_SDSYNC 0x00000800000000
902 #define POWER6_MMCRA_SIHV 0x00000400000000
903 #define POWER6_MMCRA_SIPR 0x00000200000000
904 #define POWER6_MMCRA_THRM 0x00000020UL
905 #define POWER6_MMCRA_OTHER 0x0000000EUL
906
907 #define POWER7P_MMCRA_SIAR_VALID 0x10000000
908 #define POWER7P_MMCRA_SDAR_VALID 0x08000000
909
910 #define SPRN_MMCRH 316 /* Hypervisor
911 #define SPRN_MMCRS 894 /* Supervisor
912 #define SPRN_MMCRC 851 /* Core monito
913 #define SPRN_EBBHR 804 /* Event based
914 #define SPRN_EBBRR 805 /* Event based
915 #define SPRN_BESCR 806 /* Branch even
916 #define BESCR_GE 0x8000000000000000ULL
917 #define SPRN_WORT 895 /* Workload op
918 #define SPRN_WORC 863 /* Workload op
919
920 #define SPRN_PMC1 787
921 #define SPRN_PMC2 788
922 #define SPRN_PMC3 789
923 #define SPRN_PMC4 790
924 #define SPRN_PMC5 791
925 #define SPRN_PMC6 792
926 #define SPRN_PMC7 793
927 #define SPRN_PMC8 794
928 #define SPRN_SIER 784
929 #define SIER_SIPR 0x2000000
930 #define SIER_SIHV 0x1000000
931 #define SIER_SIAR_VALID 0x0400000
932 #define SIER_SDAR_VALID 0x0200000
933 #define SPRN_SIER2 752
934 #define SPRN_SIER3 753
935 #define SPRN_USIER2 736
936 #define SPRN_USIER3 737
937 #define SPRN_SIAR 796
938 #define SPRN_SDAR 797
939 #define SPRN_TACR 888
940 #define SPRN_TCSCR 889
941 #define SPRN_CSIGR 890
942 #define SPRN_SPMC1 892
943 #define SPRN_SPMC2 893
944
945 /* When EBB is enabled, some of MMCR0/MMCR2/SI
946 #define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE
947 #define MMCR2_USER_MASK 0x4020100804020000UL /
948 #define SIER_USER_MASK 0x7fffffUL
949
950 #define SPRN_PA6T_MMCR0 795
951 #define PA6T_MMCR0_EN0 0x000000000000
952 #define PA6T_MMCR0_EN1 0x000000000000
953 #define PA6T_MMCR0_EN2 0x000000000000
954 #define PA6T_MMCR0_EN3 0x000000000000
955 #define PA6T_MMCR0_EN4 0x000000000000
956 #define PA6T_MMCR0_EN5 0x000000000000
957 #define PA6T_MMCR0_SUPEN 0x000000000000
958 #define PA6T_MMCR0_PREN 0x000000000000
959 #define PA6T_MMCR0_HYPEN 0x000000000000
960 #define PA6T_MMCR0_FCM0 0x000000000000
961 #define PA6T_MMCR0_FCM1 0x000000000000
962 #define PA6T_MMCR0_INTGEN 0x000000000000
963 #define PA6T_MMCR0_INTEN0 0x000000000000
964 #define PA6T_MMCR0_INTEN1 0x000000000000
965 #define PA6T_MMCR0_INTEN2 0x000000000000
966 #define PA6T_MMCR0_INTEN3 0x000000000000
967 #define PA6T_MMCR0_INTEN4 0x000000000001
968 #define PA6T_MMCR0_INTEN5 0x000000000002
969 #define PA6T_MMCR0_DISCNT 0x000000000004
970 #define PA6T_MMCR0_UOP 0x000000000008
971 #define PA6T_MMCR0_TRG 0x000000000010
972 #define PA6T_MMCR0_TRGEN 0x000000000020
973 #define PA6T_MMCR0_TRGREG 0x000000000160
974 #define PA6T_MMCR0_SIARLOG 0x000000000200
975 #define PA6T_MMCR0_SDARLOG 0x000000000400
976 #define PA6T_MMCR0_PROEN 0x000000000800
977 #define PA6T_MMCR0_PROLOG 0x000000001000
978 #define PA6T_MMCR0_DAMEN2 0x000000002000
979 #define PA6T_MMCR0_DAMEN3 0x000000004000
980 #define PA6T_MMCR0_DAMEN4 0x000000008000
981 #define PA6T_MMCR0_DAMEN5 0x000000010000
982 #define PA6T_MMCR0_DAMSEL2 0x000000020000
983 #define PA6T_MMCR0_DAMSEL3 0x000000040000
984 #define PA6T_MMCR0_DAMSEL4 0x000000080000
985 #define PA6T_MMCR0_DAMSEL5 0x000000100000
986 #define PA6T_MMCR0_HANDDIS 0x000000200000
987 #define PA6T_MMCR0_PCTEN 0x000000400000
988 #define PA6T_MMCR0_SOCEN 0x000000800000
989 #define PA6T_MMCR0_SOCMOD 0x000001000000
990
991 #define SPRN_PA6T_MMCR1 798
992 #define PA6T_MMCR1_ES2 0x000000000000
993 #define PA6T_MMCR1_ES3 0x000000000000
994 #define PA6T_MMCR1_ES4 0x0000000000ff
995 #define PA6T_MMCR1_ES5 0x00000000ff00
996
997 #define SPRN_PA6T_UPMC0 771 /* User PerfMo
998 #define SPRN_PA6T_UPMC1 772 /* ... */
999 #define SPRN_PA6T_UPMC2 773
1000 #define SPRN_PA6T_UPMC3 774
1001 #define SPRN_PA6T_UPMC4 775
1002 #define SPRN_PA6T_UPMC5 776
1003 #define SPRN_PA6T_UMMCR0 779 /* User Monit
1004 #define SPRN_PA6T_SIAR 780 /* Sampled In
1005 #define SPRN_PA6T_UMMCR1 782 /* User Monit
1006 #define SPRN_PA6T_SIER 785 /* Sampled In
1007 #define SPRN_PA6T_PMC0 787
1008 #define SPRN_PA6T_PMC1 788
1009 #define SPRN_PA6T_PMC2 789
1010 #define SPRN_PA6T_PMC3 790
1011 #define SPRN_PA6T_PMC4 791
1012 #define SPRN_PA6T_PMC5 792
1013 #define SPRN_PA6T_TSR0 793 /* Timestamp
1014 #define SPRN_PA6T_TSR1 794 /* Timestamp
1015 #define SPRN_PA6T_TSR2 799 /* Timestamp
1016 #define SPRN_PA6T_TSR3 784 /* Timestamp
1017
1018 #define SPRN_PA6T_IER 981 /* Icache Err
1019 #define SPRN_PA6T_DER 982 /* Dcache Err
1020 #define SPRN_PA6T_BER 862 /* BIU Error
1021 #define SPRN_PA6T_MER 849 /* MMU Error
1022
1023 #define SPRN_PA6T_IMA0 880 /* Instructio
1024 #define SPRN_PA6T_IMA1 881 /* ... */
1025 #define SPRN_PA6T_IMA2 882
1026 #define SPRN_PA6T_IMA3 883
1027 #define SPRN_PA6T_IMA4 884
1028 #define SPRN_PA6T_IMA5 885
1029 #define SPRN_PA6T_IMA6 886
1030 #define SPRN_PA6T_IMA7 887
1031 #define SPRN_PA6T_IMA8 888
1032 #define SPRN_PA6T_IMA9 889
1033 #define SPRN_PA6T_BTCR 978 /* Breakpoint
1034 #define SPRN_PA6T_IMAAT 979 /* Instructio
1035 #define SPRN_PA6T_PCCR 1019 /* Power Coun
1036 #define SPRN_BKMK 1020 /* Cell Bookm
1037 #define SPRN_PA6T_RPCCR 1021 /* Retire PC
1038
1039
1040 #else /* 32-bit */
1041 #define SPRN_MMCR0 952 /* Monitor Mo
1042 #define MMCR0_FC 0x80000000UL /* freez
1043 #define MMCR0_FCS 0x40000000UL /* freez
1044 #define MMCR0_FCP 0x20000000UL /* freez
1045 #define MMCR0_FCM1 0x10000000UL /* freez
1046 #define MMCR0_FCM0 0x08000000UL /* freez
1047 #define MMCR0_PMXE 0x04000000UL /* perfo
1048 #define MMCR0_FCECE 0x02000000UL /* freez
1049 #define MMCR0_TBEE 0x00400000UL /* time
1050 #define MMCR0_PMC1CE 0x00008000UL /* PMC1
1051 #define MMCR0_PMCnCE 0x00004000UL /* count
1052 #define MMCR0_TRIGGER 0x00002000UL /* TRIGG
1053 #define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1
1054 #define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2
1055
1056 #define SPRN_MMCR1 956
1057 #define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3
1058 #define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4
1059 #define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5
1060 #define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6
1061 #define SPRN_MMCR2 944
1062 #define SPRN_PMC1 953 /* Performanc
1063 #define SPRN_PMC2 954 /* Performanc
1064 #define SPRN_PMC3 957 /* Performanc
1065 #define SPRN_PMC4 958 /* Performanc
1066 #define SPRN_PMC5 945 /* Performanc
1067 #define SPRN_PMC6 946 /* Performanc
1068
1069 #define SPRN_SIAR 955 /* Sampled In
1070
1071 /* Bit definitions for MMCR0 and PMC1 / PMC2.
1072 #define MMCR0_PMC1_CYCLES (1 << 7)
1073 #define MMCR0_PMC1_ICACHEMISS (5 << 7)
1074 #define MMCR0_PMC1_DTLB (6 << 7)
1075 #define MMCR0_PMC2_DCACHEMISS 0x6
1076 #define MMCR0_PMC2_CYCLES 0x1
1077 #define MMCR0_PMC2_ITLB 0x7
1078 #define MMCR0_PMC2_LOADMISSTIME 0x5
1079 #endif
1080
1081 /*
1082 * SPRG usage:
1083 *
1084 * All 64-bit:
1085 * - SPRG1 stores PACA pointer except 64
1086 * HV mode in which case it is HSPRG0
1087 *
1088 * 64-bit server:
1089 * - SPRG0 scratch for TM recheckpoint/r
1090 * - SPRG2 scratch for exception vectors
1091 * - SPRG3 CPU and NUMA node for VDSO ge
1092 * - HSPRG0 stores PACA in HV mode
1093 * - HSPRG1 scratch for "HV" exceptions
1094 *
1095 * 64-bit embedded
1096 * - SPRG0 generic exception scratch
1097 * - SPRG2 TLB exception stack
1098 * - SPRG3 critical exception scratch (u
1099 * - SPRG4 unused (user visible)
1100 * - SPRG6 TLB miss scratch (user visibl
1101 * - SPRG7 CPU and NUMA node for VDSO ge
1102 * - SPRG8 machine check exception scrat
1103 * - SPRG9 debug exception scratch
1104 *
1105 * All 32-bit:
1106 * - SPRG3 current thread_struct physica
1107 * (virtual on BookE, physical on othe
1108 *
1109 * 32-bit classic:
1110 * - SPRG0 scratch for exception vectors
1111 * - SPRG1 scratch for exception vectors
1112 * - SPRG2 indicator that we are in RTAS
1113 * - SPRG4 (603 only) pseudo TLB LRU dat
1114 *
1115 * 32-bit 440 and FSL BookE:
1116 * - SPRG0 scratch for exception vectors
1117 * - SPRG1 scratch for exception vectors
1118 * - SPRG2 scratch for crit interrupts h
1119 * - SPRG4 scratch for exception vectors
1120 * - SPRG5 scratch for exception vectors
1121 * - SPRG6 scratch for machine check han
1122 * - SPRG7 scratch for exception vectors
1123 * - SPRG9 scratch for debug vectors (e5
1124 *
1125 * Additionally, BookE separates "read"
1126 * of those registers. That allows to us
1127 * readable variant for reads, which can
1128 * with KVM type virtualization.
1129 *
1130 * 32-bit 8xx:
1131 * - SPRG0 scratch for exception vectors
1132 * - SPRG1 scratch for exception vectors
1133 * - SPRG2 scratch for exception vectors
1134 *
1135 */
1136 #ifdef CONFIG_PPC64
1137 #define SPRN_SPRG_PACA SPRN_SPRG1
1138 #else
1139 #define SPRN_SPRG_THREAD SPRN_SPRG3
1140 #endif
1141
1142 #ifdef CONFIG_PPC_BOOK3S_64
1143 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG2
1144 #define SPRN_SPRG_HPACA SPRN_HSPRG0
1145 #define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1
1146 #define SPRN_SPRG_VDSO_READ SPRN_USPRG3
1147 #define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3
1148
1149 #define GET_PACA(rX)
1150 BEGIN_FTR_SECTION_NESTED(66);
1151 mfspr rX,SPRN_SPRG_PACA;
1152 FTR_SECTION_ELSE_NESTED(66);
1153 mfspr rX,SPRN_SPRG_HPACA;
1154 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_
1155
1156 #define SET_PACA(rX)
1157 BEGIN_FTR_SECTION_NESTED(66);
1158 mtspr SPRN_SPRG_PACA,rX;
1159 FTR_SECTION_ELSE_NESTED(66);
1160 mtspr SPRN_SPRG_HPACA,rX;
1161 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_
1162
1163 #define GET_SCRATCH0(rX)
1164 BEGIN_FTR_SECTION_NESTED(66);
1165 mfspr rX,SPRN_SPRG_SCRATCH0;
1166 FTR_SECTION_ELSE_NESTED(66);
1167 mfspr rX,SPRN_SPRG_HSCRATCH0;
1168 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_
1169
1170 #define SET_SCRATCH0(rX)
1171 BEGIN_FTR_SECTION_NESTED(66);
1172 mtspr SPRN_SPRG_SCRATCH0,rX;
1173 FTR_SECTION_ELSE_NESTED(66);
1174 mtspr SPRN_SPRG_HSCRATCH0,rX;
1175 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_
1176
1177 #else /* CONFIG_PPC_BOOK3S_64 */
1178 #define GET_SCRATCH0(rX) mfspr rX,SP
1179 #define SET_SCRATCH0(rX) mtspr SPRN_
1180
1181 #endif
1182
1183 #ifdef CONFIG_PPC_BOOK3E_64
1184 #define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8
1185 #define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG3
1186 #define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9
1187 #define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2
1188 #define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6
1189 #define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0
1190 #define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GE
1191 #define SPRN_SPRG_VDSO_READ SPRN_USPRG7
1192 #define SPRN_SPRG_VDSO_WRITE SPRN_SPRG7
1193
1194 #define SET_PACA(rX) mtspr SPRN_SPRG_PAC
1195 #define GET_PACA(rX) mfspr rX,SPRN_SPRG_
1196
1197 #endif
1198
1199 #ifdef CONFIG_PPC_BOOK3S_32
1200 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1201 #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1202 #define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1203 #define SPRN_SPRG_603_LRU SPRN_SPRG4
1204 #endif
1205
1206 #ifdef CONFIG_BOOKE
1207 #define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0
1208 #define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0
1209 #define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1
1210 #define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1
1211 #define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
1212 #define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
1213 #define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R
1214 #define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W
1215 #define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R
1216 #define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W
1217 #define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1
1218 #define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1
1219 #define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R
1220 #define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W
1221 #define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9
1222 #define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9
1223 #endif
1224
1225 #ifdef CONFIG_PPC_8xx
1226 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1227 #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1228 #define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1229 #endif
1230
1231
1232
1233 /*
1234 * An mtfsf instruction with the L bit set. O
1235 * full 64bits of FPSCR is restored and on ot
1236 *
1237 * Until binutils gets the new form of mtfsf,
1238 */
1239 #ifdef CONFIG_PPC64
1240 #define MTFSF_L(REG) \
1241 .long (0xfc00058e | ((0xff) << 17) |
1242 #else
1243 #define MTFSF_L(REG) mtfsf 0xff, (REG)
1244 #endif
1245
1246 /* Processor Version Register (PVR) field ext
1247
1248 #define PVR_VER(pvr) (((pvr) >> 16) & 0xF
1249 #define PVR_REV(pvr) (((pvr) >> 0) & 0xF
1250
1251 #define pvr_version_is(pvr) (PVR_VER(mfsp
1252
1253 /*
1254 * IBM has further subdivided the standard Po
1255 * revision subfields of the PVR for the Powe
1256 */
1257
1258 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFF
1259 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF)
1260 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF)
1261 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF)
1262 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF)
1263 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF)
1264
1265 /* Processor Version Numbers */
1266
1267 #define PVR_403GA 0x00200000
1268 #define PVR_403GB 0x00200100
1269 #define PVR_403GC 0x00200200
1270 #define PVR_403GCX 0x00201400
1271 #define PVR_405GP 0x40110000
1272 #define PVR_476 0x11a52000
1273 #define PVR_476FPE 0x7ff50000
1274 #define PVR_STB03XXX 0x40310000
1275 #define PVR_NP405H 0x41410000
1276 #define PVR_NP405L 0x41610000
1277 #define PVR_601 0x00010000
1278 #define PVR_602 0x00050000
1279 #define PVR_603 0x00030000
1280 #define PVR_603e 0x00060000
1281 #define PVR_603ev 0x00070000
1282 #define PVR_603r 0x00071000
1283 #define PVR_604 0x00040000
1284 #define PVR_604e 0x00090000
1285 #define PVR_604r 0x000A0000
1286 #define PVR_620 0x00140000
1287 #define PVR_740 0x00080000
1288 #define PVR_750 PVR_740
1289 #define PVR_740P 0x10080000
1290 #define PVR_750P PVR_740P
1291 #define PVR_7400 0x000C0000
1292 #define PVR_7410 0x800C0000
1293 #define PVR_7450 0x80000000
1294 #define PVR_8540 0x80200000
1295 #define PVR_8560 0x80200000
1296 #define PVR_VER_E500V1 0x8020
1297 #define PVR_VER_E500V2 0x8021
1298 #define PVR_VER_E500MC 0x8023
1299 #define PVR_VER_E5500 0x8024
1300 #define PVR_VER_E6500 0x8040
1301 #define PVR_VER_7450 0x8000
1302 #define PVR_VER_7455 0x8001
1303 #define PVR_VER_7447 0x8002
1304 #define PVR_VER_7447A 0x8003
1305 #define PVR_VER_7448 0x8004
1306
1307 /*
1308 * For the 8xx processors, all of them report
1309 * the PowerPC core. The various versions of
1310 * differentiated by the version number in th
1311 * Module (CPM).
1312 */
1313 #define PVR_8xx 0x00500000
1314
1315 #define PVR_8240 0x00810100
1316 #define PVR_8245 0x80811014
1317 #define PVR_8260 PVR_8240
1318
1319 /* 476 Simulator seems to currently have the
1320 #define PVR_476_ISS 0x00052000
1321
1322 /* 64-bit processors */
1323 #define PVR_NORTHSTAR 0x0033
1324 #define PVR_PULSAR 0x0034
1325 #define PVR_POWER4 0x0035
1326 #define PVR_ICESTAR 0x0036
1327 #define PVR_SSTAR 0x0037
1328 #define PVR_POWER4p 0x0038
1329 #define PVR_970 0x0039
1330 #define PVR_POWER5 0x003A
1331 #define PVR_POWER5p 0x003B
1332 #define PVR_970FX 0x003C
1333 #define PVR_POWER6 0x003E
1334 #define PVR_POWER7 0x003F
1335 #define PVR_630 0x0040
1336 #define PVR_630p 0x0041
1337 #define PVR_970MP 0x0044
1338 #define PVR_970GX 0x0045
1339 #define PVR_POWER7p 0x004A
1340 #define PVR_POWER8E 0x004B
1341 #define PVR_POWER8NVL 0x004C
1342 #define PVR_POWER8 0x004D
1343 #define PVR_HX_C2000 0x0066
1344 #define PVR_POWER9 0x004E
1345 #define PVR_POWER10 0x0080
1346 #define PVR_POWER11 0x0082
1347 #define PVR_BE 0x0070
1348 #define PVR_PA6T 0x0090
1349
1350 /* "Logical" PVR values defined in PAPR, repr
1351 #define PVR_ARCH_204 0x0f000001
1352 #define PVR_ARCH_205 0x0f000002
1353 #define PVR_ARCH_206 0x0f000003
1354 #define PVR_ARCH_206p 0x0f100003
1355 #define PVR_ARCH_207 0x0f000004
1356 #define PVR_ARCH_300 0x0f000005
1357 #define PVR_ARCH_31 0x0f000006
1358 #define PVR_ARCH_31_P11 0x0f000007
1359
1360 /* Macros for setting and retrieving special
1361 #ifndef __ASSEMBLY__
1362
1363 #if defined(CONFIG_PPC64) || defined(__CHECKE
1364 typedef struct {
1365 u32 val;
1366 #ifdef CONFIG_PPC64
1367 u32 suffix;
1368 #endif
1369 } __packed ppc_inst_t;
1370 #else
1371 typedef u32 ppc_inst_t;
1372 #endif
1373
1374 #define mfmsr() ({unsigned long rval;
1375 asm volatile("mfmsr %
1376
1377 #ifdef CONFIG_PPC_BOOK3S_64
1378 #define __mtmsrd(v, l) asm volatile("mtmsrd
1379 : : "r"
1380 #define mtmsr(v) __mtmsrd((v), 0)
1381 #define __MTMSR "mtmsrd"
1382 #else
1383 #define mtmsr(v) asm volatile("mtmsr %
1384 : "r" ((
1385 : "memor
1386 #define __mtmsrd(v, l) BUILD_BUG()
1387 #define __MTMSR "mtmsr"
1388 #endif
1389
1390 static inline void mtmsr_isync(unsigned long
1391 {
1392 asm volatile(__MTMSR " %0; " ASM_FTR_
1393 "r" (val), "i" (CPU_F
1394 }
1395
1396 #define mfspr(rn) ({unsigned long rval;
1397 asm volatile("mfspr %
1398 : "=r" (rval)
1399 #define mtspr(rn, v) asm volatile("mtspr "
1400 : "r" ((
1401 : "memor
1402 #define wrtspr(rn) asm volatile("mtspr "
1403
1404 static inline void wrtee(unsigned long val)
1405 {
1406 if (__builtin_constant_p(val))
1407 asm volatile("wrteei %0" : :
1408 else
1409 asm volatile("wrtee %0" : : "
1410 }
1411
1412 extern unsigned long msr_check_and_set(unsign
1413 extern bool strict_msr_control;
1414 extern void __msr_check_and_clear(unsigned lo
1415 static inline void msr_check_and_clear(unsign
1416 {
1417 if (strict_msr_control)
1418 __msr_check_and_clear(bits);
1419 }
1420
1421 #ifdef CONFIG_PPC32
1422 static inline u32 mfsr(u32 idx)
1423 {
1424 u32 val;
1425
1426 if (__builtin_constant_p(idx))
1427 asm volatile("mfsr %0, %1" :
1428 else
1429 asm volatile("mfsrin %0, %1"
1430
1431 return val;
1432 }
1433
1434 static inline void mtsr(u32 val, u32 idx)
1435 {
1436 if (__builtin_constant_p(idx))
1437 asm volatile("mtsr %1, %0" :
1438 else
1439 asm volatile("mtsrin %0, %1"
1440 }
1441 #endif
1442
1443 extern unsigned long current_stack_frame(void
1444
1445 register unsigned long current_stack_pointer
1446
1447 extern unsigned long scom970_read(unsigned in
1448 extern void scom970_write(unsigned int addres
1449
1450 struct pt_regs;
1451
1452 extern void ppc_save_regs(struct pt_regs *reg
1453 #endif /* __ASSEMBLY__ */
1454 #endif /* __KERNEL__ */
1455 #endif /* _ASM_POWERPC_REG_H */
1456
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