1 // SPDX-License-Identifier: GPL-2.0-or-later 1
2 /*
3 * This program is used to generate definition
4 * assembly language modules.
5 *
6 * We use the technique used in the OSF Mach k
7 * generate asm statements containing #defines
8 * compile this file to assembler, and then ex
9 * #defines from the assembly-language output.
10 */
11
12 #include <linux/compat.h>
13 #include <linux/signal.h>
14 #include <linux/sched.h>
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
18 #include <linux/types.h>
19 #include <linux/mman.h>
20 #include <linux/mm.h>
21 #include <linux/suspend.h>
22 #include <linux/hrtimer.h>
23 #ifdef CONFIG_PPC64
24 #include <linux/time.h>
25 #include <linux/hardirq.h>
26 #endif
27 #include <linux/kbuild.h>
28
29 #include <asm/io.h>
30 #include <asm/page.h>
31 #include <asm/processor.h>
32 #include <asm/cputable.h>
33 #include <asm/thread_info.h>
34 #include <asm/rtas.h>
35 #include <asm/vdso_datapage.h>
36 #include <asm/dbell.h>
37 #ifdef CONFIG_PPC64
38 #include <asm/paca.h>
39 #include <asm/lppaca.h>
40 #include <asm/cache.h>
41 #include <asm/mmu.h>
42 #include <asm/hvcall.h>
43 #include <asm/xics.h>
44 #endif
45 #ifdef CONFIG_PPC_POWERNV
46 #include <asm/opal.h>
47 #endif
48 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_
49 #include <linux/kvm_host.h>
50 #endif
51 #if defined(CONFIG_KVM) && defined(CONFIG_PPC_
52 #include <asm/kvm_book3s.h>
53 #include <asm/kvm_ppc.h>
54 #endif
55
56 #ifdef CONFIG_PPC32
57 #ifdef CONFIG_BOOKE
58 #include "head_booke.h"
59 #endif
60 #endif
61
62 #if defined(CONFIG_PPC_E500)
63 #include "../mm/mmu_decl.h"
64 #endif
65
66 #ifdef CONFIG_PPC_8xx
67 #include <asm/fixmap.h>
68 #endif
69
70 #ifdef CONFIG_XMON
71 #include "../xmon/xmon_bpts.h"
72 #endif
73
74 #define STACK_PT_REGS_OFFSET(sym, val) \
75 DEFINE(sym, STACK_INT_FRAME_REGS + off
76
77 int main(void)
78 {
79 OFFSET(THREAD, task_struct, thread);
80 OFFSET(MM, task_struct, mm);
81 #ifdef CONFIG_STACKPROTECTOR
82 OFFSET(TASK_CANARY, task_struct, stack
83 #ifdef CONFIG_PPC64
84 OFFSET(PACA_CANARY, paca_struct, canar
85 #endif
86 #endif
87 #ifdef CONFIG_PPC32
88 #ifdef CONFIG_PPC_RTAS
89 OFFSET(RTAS_SP, thread_struct, rtas_sp
90 #endif
91 #endif /* CONFIG_PPC64 */
92 OFFSET(TASK_STACK, task_struct, stack)
93 #ifdef CONFIG_SMP
94 OFFSET(TASK_CPU, task_struct, thread_i
95 #endif
96
97 #ifdef CONFIG_LIVEPATCH_64
98 OFFSET(TI_livepatch_sp, thread_info, l
99 #endif
100
101 OFFSET(KSP, thread_struct, ksp);
102 OFFSET(PT_REGS, thread_struct, regs);
103 #ifdef CONFIG_BOOKE
104 OFFSET(THREAD_NORMSAVES, thread_struct
105 #endif
106 #ifdef CONFIG_PPC_FPU
107 OFFSET(THREAD_FPEXC_MODE, thread_struc
108 OFFSET(THREAD_FPSTATE, thread_struct,
109 OFFSET(THREAD_FPSAVEAREA, thread_struc
110 #endif
111 OFFSET(FPSTATE_FPSCR, thread_fp_state,
112 OFFSET(THREAD_LOAD_FP, thread_struct,
113 #ifdef CONFIG_ALTIVEC
114 OFFSET(THREAD_VRSTATE, thread_struct,
115 OFFSET(THREAD_VRSAVEAREA, thread_struc
116 OFFSET(THREAD_USED_VR, thread_struct,
117 OFFSET(VRSTATE_VSCR, thread_vr_state,
118 OFFSET(THREAD_LOAD_VEC, thread_struct,
119 #endif /* CONFIG_ALTIVEC */
120 #ifdef CONFIG_VSX
121 OFFSET(THREAD_USED_VSR, thread_struct,
122 #endif /* CONFIG_VSX */
123 #ifdef CONFIG_PPC64
124 OFFSET(KSP_VSID, thread_struct, ksp_vs
125 #else /* CONFIG_PPC64 */
126 OFFSET(PGDIR, thread_struct, pgdir);
127 OFFSET(SRR0, thread_struct, srr0);
128 OFFSET(SRR1, thread_struct, srr1);
129 OFFSET(DAR, thread_struct, dar);
130 OFFSET(DSISR, thread_struct, dsisr);
131 #ifdef CONFIG_PPC_BOOK3S_32
132 OFFSET(THR0, thread_struct, r0);
133 OFFSET(THR3, thread_struct, r3);
134 OFFSET(THR4, thread_struct, r4);
135 OFFSET(THR5, thread_struct, r5);
136 OFFSET(THR6, thread_struct, r6);
137 OFFSET(THR8, thread_struct, r8);
138 OFFSET(THR9, thread_struct, r9);
139 OFFSET(THR11, thread_struct, r11);
140 OFFSET(THLR, thread_struct, lr);
141 OFFSET(THCTR, thread_struct, ctr);
142 OFFSET(THSR0, thread_struct, sr0);
143 #endif
144 #ifdef CONFIG_SPE
145 OFFSET(THREAD_EVR0, thread_struct, evr
146 OFFSET(THREAD_ACC, thread_struct, acc)
147 OFFSET(THREAD_USED_SPE, thread_struct,
148 #endif /* CONFIG_SPE */
149 #endif /* CONFIG_PPC64 */
150 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
151 OFFSET(THREAD_KVM_SVCPU, thread_struct
152 #endif
153 #if defined(CONFIG_KVM) && defined(CONFIG_BOOK
154 OFFSET(THREAD_KVM_VCPU, thread_struct,
155 #endif
156
157 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
158 OFFSET(PACATMSCRATCH, paca_struct, tm_
159 OFFSET(THREAD_TM_TFHAR, thread_struct,
160 OFFSET(THREAD_TM_TEXASR, thread_struct
161 OFFSET(THREAD_TM_TFIAR, thread_struct,
162 OFFSET(THREAD_TM_TAR, thread_struct, t
163 OFFSET(THREAD_TM_PPR, thread_struct, t
164 OFFSET(THREAD_TM_DSCR, thread_struct,
165 OFFSET(THREAD_TM_AMR, thread_struct, t
166 OFFSET(PT_CKPT_REGS, thread_struct, ck
167 OFFSET(THREAD_CKVRSTATE, thread_struct
168 OFFSET(THREAD_CKVRSAVE, thread_struct,
169 OFFSET(THREAD_CKFPSTATE, thread_struct
170 /* Local pt_regs on stack in int frame
171 DEFINE(TM_FRAME_SIZE, STACK_INT_FRAME_
172 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
173
174 OFFSET(TI_LOCAL_FLAGS, thread_info, lo
175
176 #ifdef CONFIG_PPC64
177 OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches
178 OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_cac
179 /* paca */
180 OFFSET(PACAPACAINDEX, paca_struct, pac
181 OFFSET(PACAPROCSTART, paca_struct, cpu
182 OFFSET(PACAKSAVE, paca_struct, kstack)
183 OFFSET(PACACURRENT, paca_struct, __cur
184 DEFINE(PACA_THREAD_INFO, offsetof(stru
185 offsetof(stru
186 OFFSET(PACASAVEDMSR, paca_struct, save
187 OFFSET(PACAR1, paca_struct, saved_r1);
188 #ifndef CONFIG_PPC_KERNEL_PCREL
189 OFFSET(PACATOC, paca_struct, kernel_to
190 #endif
191 OFFSET(PACAKBASE, paca_struct, kernelb
192 OFFSET(PACAKMSR, paca_struct, kernel_m
193 #ifdef CONFIG_PPC_BOOK3S_64
194 OFFSET(PACAHSRR_VALID, paca_struct, hs
195 OFFSET(PACASRR_VALID, paca_struct, srr
196 #endif
197 OFFSET(PACAIRQSOFTMASK, paca_struct, i
198 OFFSET(PACAIRQHAPPENED, paca_struct, i
199 OFFSET(PACA_FTRACE_ENABLED, paca_struc
200
201 #ifdef CONFIG_PPC_BOOK3E_64
202 OFFSET(PACAPGD, paca_struct, pgd);
203 OFFSET(PACA_KERNELPGD, paca_struct, ke
204 OFFSET(PACA_EXGEN, paca_struct, exgen)
205 OFFSET(PACA_EXTLB, paca_struct, extlb)
206 OFFSET(PACA_EXMC, paca_struct, exmc);
207 OFFSET(PACA_EXCRIT, paca_struct, excri
208 OFFSET(PACA_EXDBG, paca_struct, exdbg)
209 OFFSET(PACA_MC_STACK, paca_struct, mc_
210 OFFSET(PACA_CRIT_STACK, paca_struct, c
211 OFFSET(PACA_DBG_STACK, paca_struct, db
212 OFFSET(PACA_TCD_PTR, paca_struct, tcd_
213
214 OFFSET(TCD_ESEL_NEXT, tlb_core_data, e
215 OFFSET(TCD_ESEL_MAX, tlb_core_data, es
216 OFFSET(TCD_ESEL_FIRST, tlb_core_data,
217 #endif /* CONFIG_PPC_BOOK3E_64 */
218
219 #ifdef CONFIG_PPC_BOOK3S_64
220 OFFSET(PACA_EXGEN, paca_struct, exgen)
221 OFFSET(PACA_EXMC, paca_struct, exmc);
222 OFFSET(PACA_EXNMI, paca_struct, exnmi)
223 #ifdef CONFIG_PPC_64S_HASH_MMU
224 OFFSET(PACA_SLBSHADOWPTR, paca_struct,
225 OFFSET(SLBSHADOW_STACKVSID, slb_shadow
226 OFFSET(SLBSHADOW_STACKESID, slb_shadow
227 OFFSET(SLBSHADOW_SAVEAREA, slb_shadow,
228 #endif
229 OFFSET(LPPACA_PMCINUSE, lppaca, pmcreg
230 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
231 OFFSET(PACA_PMCINUSE, paca_struct, pmc
232 #endif
233 OFFSET(LPPACA_YIELDCOUNT, lppaca, yiel
234 #endif /* CONFIG_PPC_BOOK3S_64 */
235 OFFSET(PACAEMERGSP, paca_struct, emerg
236 #ifdef CONFIG_PPC_BOOK3S_64
237 OFFSET(PACAMCEMERGSP, paca_struct, mc_
238 OFFSET(PACA_NMI_EMERG_SP, paca_struct,
239 OFFSET(PACA_IN_MCE, paca_struct, in_mc
240 OFFSET(PACA_IN_NMI, paca_struct, in_nm
241 OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, p
242 OFFSET(PACA_EXRFI, paca_struct, exrfi)
243 OFFSET(PACA_L1D_FLUSH_SIZE, paca_struc
244
245 #endif
246 OFFSET(PACAHWCPUID, paca_struct, hw_cp
247 OFFSET(PACAKEXECSTATE, paca_struct, ke
248 OFFSET(PACA_DSCR_DEFAULT, paca_struct,
249 OFFSET(PACA_EXIT_SAVE_R1, paca_struct,
250 #ifdef CONFIG_PPC_BOOK3E_64
251 OFFSET(PACA_TRAP_SAVE, paca_struct, tr
252 #endif
253 OFFSET(PACA_SPRG_VDSO, paca_struct, sp
254 #else /* CONFIG_PPC64 */
255 #endif /* CONFIG_PPC64 */
256
257 /* RTAS */
258 OFFSET(RTASBASE, rtas_t, base);
259 OFFSET(RTASENTRY, rtas_t, entry);
260
261 /* Interrupt register frame */
262 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME
263 DEFINE(SWITCH_FRAME_SIZE, STACK_SWITCH
264 STACK_PT_REGS_OFFSET(GPR0, gpr[0]);
265 STACK_PT_REGS_OFFSET(GPR1, gpr[1]);
266 STACK_PT_REGS_OFFSET(GPR2, gpr[2]);
267 STACK_PT_REGS_OFFSET(GPR3, gpr[3]);
268 STACK_PT_REGS_OFFSET(GPR4, gpr[4]);
269 STACK_PT_REGS_OFFSET(GPR5, gpr[5]);
270 STACK_PT_REGS_OFFSET(GPR6, gpr[6]);
271 STACK_PT_REGS_OFFSET(GPR7, gpr[7]);
272 STACK_PT_REGS_OFFSET(GPR8, gpr[8]);
273 STACK_PT_REGS_OFFSET(GPR9, gpr[9]);
274 STACK_PT_REGS_OFFSET(GPR10, gpr[10]);
275 STACK_PT_REGS_OFFSET(GPR11, gpr[11]);
276 STACK_PT_REGS_OFFSET(GPR12, gpr[12]);
277 STACK_PT_REGS_OFFSET(GPR13, gpr[13]);
278 /*
279 * Note: these symbols include _ becau
280 * register names
281 */
282 STACK_PT_REGS_OFFSET(_NIP, nip);
283 STACK_PT_REGS_OFFSET(_MSR, msr);
284 STACK_PT_REGS_OFFSET(_CTR, ctr);
285 STACK_PT_REGS_OFFSET(_LINK, link);
286 STACK_PT_REGS_OFFSET(_CCR, ccr);
287 STACK_PT_REGS_OFFSET(_XER, xer);
288 STACK_PT_REGS_OFFSET(_DAR, dar);
289 STACK_PT_REGS_OFFSET(_DEAR, dear);
290 STACK_PT_REGS_OFFSET(_DSISR, dsisr);
291 STACK_PT_REGS_OFFSET(_ESR, esr);
292 STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_g
293 STACK_PT_REGS_OFFSET(RESULT, result);
294 STACK_PT_REGS_OFFSET(_TRAP, trap);
295 #ifdef CONFIG_PPC64
296 STACK_PT_REGS_OFFSET(SOFTE, softe);
297 STACK_PT_REGS_OFFSET(_PPR, ppr);
298 #endif
299
300 #ifdef CONFIG_PPC_PKEY
301 STACK_PT_REGS_OFFSET(STACK_REGS_AMR, a
302 STACK_PT_REGS_OFFSET(STACK_REGS_IAMR,
303 #endif
304
305 #if defined(CONFIG_PPC32) && defined(CONFIG_BO
306 STACK_PT_REGS_OFFSET(MAS0, mas0);
307 /* we overload MMUCR for 44x on MAS0 s
308 STACK_PT_REGS_OFFSET(MMUCR, mas0);
309 STACK_PT_REGS_OFFSET(MAS1, mas1);
310 STACK_PT_REGS_OFFSET(MAS2, mas2);
311 STACK_PT_REGS_OFFSET(MAS3, mas3);
312 STACK_PT_REGS_OFFSET(MAS6, mas6);
313 STACK_PT_REGS_OFFSET(MAS7, mas7);
314 STACK_PT_REGS_OFFSET(_SRR0, srr0);
315 STACK_PT_REGS_OFFSET(_SRR1, srr1);
316 STACK_PT_REGS_OFFSET(_CSRR0, csrr0);
317 STACK_PT_REGS_OFFSET(_CSRR1, csrr1);
318 STACK_PT_REGS_OFFSET(_DSRR0, dsrr0);
319 STACK_PT_REGS_OFFSET(_DSRR1, dsrr1);
320 #endif
321
322 /* About the CPU features table */
323 OFFSET(CPU_SPEC_FEATURES, cpu_spec, cp
324 OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_s
325 OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu
326
327 OFFSET(pbe_address, pbe, address);
328 OFFSET(pbe_orig_address, pbe, orig_add
329 OFFSET(pbe_next, pbe, next);
330
331 #ifndef CONFIG_PPC64
332 DEFINE(TASK_SIZE, TASK_SIZE);
333 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>2
334 #endif /* ! CONFIG_PPC64 */
335
336 /* datapage offsets for use by vdso */
337 OFFSET(VDSO_DATA_OFFSET, vdso_arch_dat
338 OFFSET(VDSO_RNG_DATA_OFFSET, vdso_arch
339 OFFSET(CFG_TB_TICKS_PER_SEC, vdso_arch
340 #ifdef CONFIG_PPC64
341 OFFSET(CFG_ICACHE_BLOCKSZ, vdso_arch_d
342 OFFSET(CFG_DCACHE_BLOCKSZ, vdso_arch_d
343 OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_arc
344 OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_arc
345 OFFSET(CFG_SYSCALL_MAP64, vdso_arch_da
346 OFFSET(CFG_SYSCALL_MAP32, vdso_arch_da
347 #else
348 OFFSET(CFG_SYSCALL_MAP32, vdso_arch_da
349 #endif
350 OFFSET(VDSO_CLOCKMODE_OFFSET, vdso_arc
351 DEFINE(VDSO_CLOCKMODE_TIMENS, VDSO_CLO
352
353 #ifdef CONFIG_BUG
354 DEFINE(BUG_ENTRY_SIZE, sizeof(struct b
355 #endif
356
357 #ifdef CONFIG_KVM
358 OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch
359 OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.h
360 OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.
361 OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.
362 OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrs
363 OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fp
364 #ifdef CONFIG_ALTIVEC
365 OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr)
366 #endif
367 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.x
368 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.c
369 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.li
370 #ifdef CONFIG_PPC_BOOK3S
371 OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
372 #endif
373 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.cc
374 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.ni
375 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
376 OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs
377 OFFSET(VCPU_SRR0, kvm_vcpu, arch.shreg
378 OFFSET(VCPU_SRR1, kvm_vcpu, arch.shreg
379 OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shre
380 OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shre
381 OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shre
382 OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shre
383 #endif
384 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
385 OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch
386 OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.
387 OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.
388 OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.g
389 OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.ce
390 OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, ar
391 OFFSET(VCPU_ACTIVITY_START, kvm_vcpu,
392 OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumula
393 OFFSET(TAS_TOTAL, kvmhv_tb_accumulator
394 OFFSET(TAS_MIN, kvmhv_tb_accumulator,
395 OFFSET(TAS_MAX, kvmhv_tb_accumulator,
396 #endif
397 OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arc
398 OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arc
399 OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arc
400 OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arc
401 OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arc
402 OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch
403 OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arc
404 OFFSET(VCPU_SHARED, kvm_vcpu, arch.sha
405 OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_
406 OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch
407 #if defined(CONFIG_PPC_BOOK3S_64) && defined(C
408 OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.s
409 #endif
410
411 OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch
412 OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch
413 OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch
414 OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_ar
415 OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch
416 OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch
417
418 OFFSET(VCPU_KVM, kvm_vcpu, kvm);
419 OFFSET(KVM_LPID, kvm, arch.lpid);
420
421 /* book3s */
422 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
423 OFFSET(KVM_SDR1, kvm, arch.sdr1);
424 OFFSET(KVM_HOST_LPID, kvm, arch.host_l
425 OFFSET(KVM_HOST_LPCR, kvm, arch.host_l
426 OFFSET(KVM_HOST_SDR1, kvm, arch.host_s
427 OFFSET(KVM_ENABLED_HCALLS, kvm, arch.e
428 OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_
429 OFFSET(KVM_SECURE_GUEST, kvm, arch.sec
430 OFFSET(VCPU_DSISR, kvm_vcpu, arch.shre
431 OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs
432 OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pi
433 OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.
434 OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_
435 OFFSET(VCPU_CPU, kvm_vcpu, cpu);
436 OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch
437 #endif
438 #ifdef CONFIG_PPC_BOOK3S
439 OFFSET(VCPU_PURR, kvm_vcpu, arch.purr)
440 OFFSET(VCPU_SPURR, kvm_vcpu, arch.spur
441 OFFSET(VCPU_IC, kvm_vcpu, arch.ic);
442 OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr)
443 OFFSET(VCPU_AMR, kvm_vcpu, arch.amr);
444 OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamo
445 OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr)
446 OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl)
447 OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr)
448 OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabr
449 OFFSET(VCPU_DAWR0, kvm_vcpu, arch.dawr
450 OFFSET(VCPU_DAWRX0, kvm_vcpu, arch.daw
451 OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciab
452 OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hfl
453 OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arc
454 OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arc
455 OFFSET(VCPU_CEDED, kvm_vcpu, arch.cede
456 OFFSET(VCPU_PRODDED, kvm_vcpu, arch.pr
457 OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr)
458 OFFSET(VCPU_MMCRA, kvm_vcpu, arch.mmcr
459 OFFSET(VCPU_MMCRS, kvm_vcpu, arch.mmcr
460 OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc);
461 OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar)
462 OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar)
463 OFFSET(VCPU_SIER, kvm_vcpu, arch.sier)
464 OFFSET(VCPU_SLB, kvm_vcpu, arch.slb);
465 OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.sl
466 OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb
467 OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arc
468 OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.
469 OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.i
470 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.
471 OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap)
472 OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar)
473 OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr);
474 OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr)
475 OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb)
476 OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbh
477 OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbr
478 OFFSET(VCPU_BESCR, kvm_vcpu, arch.besc
479 OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csig
480 OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr)
481 OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcsc
482 OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop)
483 OFFSET(VCPU_WORT, kvm_vcpu, arch.wort)
484 OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfsc
485 OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore,
486 OFFSET(VCORE_IN_GUEST, kvmppc_vcore, i
487 OFFSET(VCORE_NAPPING_THREADS, kvmppc_v
488 OFFSET(VCORE_KVM, kvmppc_vcore, kvm);
489 OFFSET(VCORE_TB_OFFSET, kvmppc_vcore,
490 OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vc
491 OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr)
492 OFFSET(VCORE_PCR, kvmppc_vcore, pcr);
493 OFFSET(VCORE_DPDES, kvmppc_vcore, dpde
494 OFFSET(VCORE_VTB, kvmppc_vcore, vtb);
495 OFFSET(VCPU_SLB_E, kvmppc_slb, orige);
496 OFFSET(VCPU_SLB_V, kvmppc_slb, origv);
497 DEFINE(VCPU_SLB_SIZE, sizeof(struct kv
498 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
499 OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfha
500 OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfia
501 OFFSET(VCPU_TEXASR, kvm_vcpu, arch.tex
502 OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arc
503 OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr
504 OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp
505 OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_
506 OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.
507 OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_t
508 OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer
509 OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_t
510 OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr
511 OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr
512 OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr
513 OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.ds
514 OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar
515 #endif
516
517 #ifdef CONFIG_PPC_BOOK3S_64
518 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
519 OFFSET(PACA_SVCPU, paca_struct, shadow
520 # define SVCPU_FIELD(x, f) DEFINE(x, offs
521 #else
522 # define SVCPU_FIELD(x, f)
523 #endif
524 # define HSTATE_FIELD(x, f) DEFINE(x, offs
525 #else /* 32-bit */
526 # define SVCPU_FIELD(x, f) DEFINE(x, offs
527 # define HSTATE_FIELD(x, f) DEFINE(x, offs
528 #endif
529
530 SVCPU_FIELD(SVCPU_CR, cr);
531 SVCPU_FIELD(SVCPU_XER, xer);
532 SVCPU_FIELD(SVCPU_CTR, ctr);
533 SVCPU_FIELD(SVCPU_LR, lr);
534 SVCPU_FIELD(SVCPU_PC, pc);
535 SVCPU_FIELD(SVCPU_R0, gpr[0]);
536 SVCPU_FIELD(SVCPU_R1, gpr[1]);
537 SVCPU_FIELD(SVCPU_R2, gpr[2]);
538 SVCPU_FIELD(SVCPU_R3, gpr[3]);
539 SVCPU_FIELD(SVCPU_R4, gpr[4]);
540 SVCPU_FIELD(SVCPU_R5, gpr[5]);
541 SVCPU_FIELD(SVCPU_R6, gpr[6]);
542 SVCPU_FIELD(SVCPU_R7, gpr[7]);
543 SVCPU_FIELD(SVCPU_R8, gpr[8]);
544 SVCPU_FIELD(SVCPU_R9, gpr[9]);
545 SVCPU_FIELD(SVCPU_R10, gpr[10]);
546 SVCPU_FIELD(SVCPU_R11, gpr[11]);
547 SVCPU_FIELD(SVCPU_R12, gpr[12]);
548 SVCPU_FIELD(SVCPU_R13, gpr[13]);
549 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_d
550 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar
551 SVCPU_FIELD(SVCPU_LAST_INST, last_inst
552 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_
553 #ifdef CONFIG_PPC_BOOK3S_32
554 SVCPU_FIELD(SVCPU_SR, sr);
555 #endif
556 #ifdef CONFIG_PPC64
557 SVCPU_FIELD(SVCPU_SLB, slb);
558 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
559 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_
560 #endif
561
562 HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
563 HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
564 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr
565 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandl
566 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0
567 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1
568 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2
569 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest
570 HSTATE_FIELD(HSTATE_RESTORE_HID5, rest
571 HSTATE_FIELD(HSTATE_NAPPING, napping);
572
573 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
574 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwth
575 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hw
576 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu
577 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vco
578 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi
579 HSTATE_FIELD(HSTATE_PTID, ptid);
580 HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake
581 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0
582 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1
583 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2
584 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]
585 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]
586 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5
587 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]
588 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0])
589 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1])
590 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2])
591 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3])
592 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4])
593 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5])
594 HSTATE_FIELD(HSTATE_PURR, host_purr);
595 HSTATE_FIELD(HSTATE_SPURR, host_spurr)
596 HSTATE_FIELD(HSTATE_DSCR, host_dscr);
597 HSTATE_FIELD(HSTATE_DABR, dabr);
598 HSTATE_FIELD(HSTATE_DECEXP, dec_expire
599 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_sp
600 DEFINE(IPI_PRIORITY, IPI_PRIORITY);
601 OFFSET(KVM_SPLIT_RPR, kvm_split_mode,
602 OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode
603 OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode
604 OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mod
605 OFFSET(KVM_SPLIT_NAPPED, kvm_split_mod
606 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
607
608 #ifdef CONFIG_PPC_BOOK3S_64
609 HSTATE_FIELD(HSTATE_CFAR, cfar);
610 HSTATE_FIELD(HSTATE_PPR, ppr);
611 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fs
612 #endif /* CONFIG_PPC_BOOK3S_64 */
613
614 #else /* CONFIG_PPC_BOOK3S */
615 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.cc
616 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.x
617 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.li
618 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.c
619 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.ni
620 OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg
621 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.
622 OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch
623 OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.
624 OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.
625 #endif /* CONFIG_PPC_BOOK3S */
626 #endif /* CONFIG_KVM */
627
628 #ifdef CONFIG_KVM_GUEST
629 OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_ar
630 OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_ar
631 OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_ar
632 OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_sh
633 OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_sh
634 OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_ar
635 OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_sha
636 #endif
637
638 #ifdef CONFIG_44x
639 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
640 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
641 #endif
642 #ifdef CONFIG_PPC_E500
643 DEFINE(TLBCAM_SIZE, sizeof(struct tlbc
644 OFFSET(TLBCAM_MAS0, tlbcam, MAS0);
645 OFFSET(TLBCAM_MAS1, tlbcam, MAS1);
646 OFFSET(TLBCAM_MAS2, tlbcam, MAS2);
647 OFFSET(TLBCAM_MAS3, tlbcam, MAS3);
648 OFFSET(TLBCAM_MAS7, tlbcam, MAS7);
649 #endif
650
651 #if defined(CONFIG_KVM) && defined(CONFIG_SPE)
652 OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]
653 OFFSET(VCPU_ACC, kvm_vcpu, arch.acc);
654 OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.sp
655 OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, ar
656 #endif
657
658 #ifdef CONFIG_KVM_BOOKE_HV
659 OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.
660 OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.
661 #endif
662
663 #ifdef CONFIG_KVM_EXIT_TIMING
664 OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu,
665 OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu,
666 OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm
667 OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm
668 #endif
669
670 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SER
671
672 #ifdef CONFIG_PPC_8xx
673 DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_v
674 #endif
675
676 #ifdef CONFIG_XMON
677 DEFINE(BPT_SIZE, BPT_SIZE);
678 #endif
679
680 return 0;
681 }
682
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