1 /* SPDX-License-Identifier: GPL-2.0-or-later *
2 /*
3 * Kernel execution entry point code.
4 *
5 * Copyright (c) 1995-1996 Gary Thomas <gdt@
6 * Initial PowerPC version.
7 * Copyright (c) 1996 Cort Dougan <cort@cs.n
8 * Rewritten for PReP
9 * Copyright (c) 1996 Paul Mackerras <paulus
10 * Low-level exception handers, MMU suppo
11 * Copyright (c) 1997 Dan Malek <dmalek@jlc.
12 * PowerPC 8xx modifications.
13 * Copyright (c) 1998-1999 TiVo, Inc.
14 * PowerPC 403GCX modifications.
15 * Copyright (c) 1999 Grant Erickson <grant@
16 * PowerPC 403GCX/405GP modifications.
17 * Copyright 2000 MontaVista Software Inc.
18 * PPC405 modifications
19 * PowerPC 403GCX/405GP modifications.
20 * Author: MontaVista Software, Inc.
21 * frank_rowand@mvista.com or sou
22 * debbie_chu@mvista.com
23 * Copyright 2002-2005 MontaVista Software,
24 * PowerPC 44x support, Matt Porter <mport
25 */
26
27 #include <linux/init.h>
28 #include <linux/pgtable.h>
29 #include <asm/processor.h>
30 #include <asm/page.h>
31 #include <asm/mmu.h>
32 #include <asm/cputable.h>
33 #include <asm/thread_info.h>
34 #include <asm/ppc_asm.h>
35 #include <asm/asm-offsets.h>
36 #include <asm/ptrace.h>
37 #include <asm/synch.h>
38 #include <asm/code-patching-asm.h>
39 #include "head_booke.h"
40
41
42 /* As with the other PowerPC ports, it is expe
43 * execution begins here, the following regist
44 * optional, information:
45 *
46 * r3 - Board info structure pointer (DRAM,
47 * r4 - Starting address of the init RAM dis
48 * r5 - Ending address of the init RAM disk
49 * r6 - Start of kernel command line string
50 * r7 - End of kernel command line string
51 *
52 */
53 __HEAD
54 _GLOBAL(_stext);
55 _GLOBAL(_start);
56 /*
57 * Reserve a word at a fixed location
58 * of abatron_pteptrs
59 */
60 nop
61 mr r31,r3 /* save device
62 li r24,0 /* CPU number
63
64 #ifdef CONFIG_RELOCATABLE
65 /*
66 * Relocate ourselves to the current runtime a
67 * This is called only by the Boot CPU.
68 * "relocate" is called with our current runti
69 * address.
70 * r21 will be loaded with the physical runtim
71 */
72 bcl 20,31,$+4
73 0: mflr r21
74 addis r21,r21,(_stext - 0b)@ha
75 addi r21,r21,(_stext - 0b)@l
76
77 /*
78 * We have the runtime (virutal) addre
79 * We calculate our shift of offset fr
80 * We could map the 256M page we belon
81 * get going from there.
82 */
83 lis r4,KERNELBASE@h
84 ori r4,r4,KERNELBASE@l
85 rlwinm r6,r21,0,4,31
86 rlwinm r5,r4,0,4,31
87 subf r3,r5,r6
88 add r3,r4,r3
89
90 bl relocate
91 #endif
92
93 bl init_cpu_state
94
95 /*
96 * This is where the main kernel code
97 */
98
99 /* ptr to current */
100 lis r2,init_task@h
101 ori r2,r2,init_task@l
102
103 /* ptr to current thread */
104 addi r4,r2,THREAD /* init task's
105 mtspr SPRN_SPRG_THREAD,r4
106
107 /* stack */
108 lis r1,init_thread_union@h
109 ori r1,r1,init_thread_union@l
110 li r0,0
111 stwu r0,THREAD_SIZE-STACK_FRAME_MIN
112
113 bl early_init
114
115 #ifdef CONFIG_RELOCATABLE
116 /*
117 * Relocatable kernel support based on
118 * relocation entries.
119 *
120 * r25 will contain RPN/ERPN for the s
121 * r21 will contain the current offset
122 */
123 lis r3,kernstart_addr@ha
124 la r3,kernstart_addr@l(r3)
125
126 /*
127 * Compute the kernstart_addr.
128 * kernstart_addr => (r6,r8)
129 * kernstart_addr & ~0xfffffff => (r6,
130 */
131 rlwinm r6,r25,0,28,31 /* ERPN. Bits
132 rlwinm r7,r25,0,0,3 /* RPN - assum
133 rlwinm r8,r21,0,4,31 /* r8 = (_stex
134 or r8,r7,r8 /* Compute the
135
136 /* Store kernstart_addr */
137 stw r6,0(r3) /* higher 32bi
138 stw r8,4(r3) /* lower 32bit
139
140 /*
141 * Compute the virt_phys_offset :
142 * virt_phys_offset = stext.run - kern
143 *
144 * stext.run = (KERNELBASE & ~0xffffff
145 * When we relocate, we have :
146 *
147 * (kernstart_addr & 0xfffffff) =
148 *
149 * hence:
150 * virt_phys_offset = (KERNELBASE & ~
151 *
152 */
153
154 /* KERNELBASE&~0xfffffff => (r4,r5) */
155 li r4, 0 /* higer 32bit
156 lis r5,KERNELBASE@h
157 rlwinm r5,r5,0,0,3 /* Align to 25
158
159 /*
160 * 64bit subtraction.
161 */
162 subfc r5,r7,r5
163 subfe r4,r6,r4
164
165 /* Store virt_phys_offset */
166 lis r3,virt_phys_offset@ha
167 la r3,virt_phys_offset@l(r3)
168
169 stw r4,0(r3)
170 stw r5,4(r3)
171
172 #elif defined(CONFIG_DYNAMIC_MEMSTART)
173 /*
174 * Mapping based, page aligned dynamic
175 *
176 * r25 will contain RPN/ERPN for the s
177 *
178 * Add the difference between KERNELBA
179 * start of physical memory to get ker
180 */
181 lis r3,kernstart_addr@ha
182 la r3,kernstart_addr@l(r3)
183
184 lis r4,KERNELBASE@h
185 ori r4,r4,KERNELBASE@l
186 lis r5,PAGE_OFFSET@h
187 ori r5,r5,PAGE_OFFSET@l
188 subf r4,r5,r4
189
190 rlwinm r6,r25,0,28,31 /* ERPN */
191 rlwinm r7,r25,0,0,3 /* RPN - assum
192 add r7,r7,r4
193
194 stw r6,0(r3)
195 stw r7,4(r3)
196 #endif
197
198 /*
199 * Decide what sort of machine this is and ini
200 */
201 #ifdef CONFIG_KASAN
202 bl kasan_early_init
203 #endif
204 li r3,0
205 mr r4,r31
206 bl machine_init
207 bl MMU_init
208
209 /* Setup PTE pointers for the Abatron
210 lis r6, swapper_pg_dir@h
211 ori r6, r6, swapper_pg_dir@l
212 lis r5, abatron_pteptrs@h
213 ori r5, r5, abatron_pteptrs@l
214 lis r4, KERNELBASE@h
215 ori r4, r4, KERNELBASE@l
216 stw r5, 0(r4) /* Save abatro
217 stw r6, 0(r5)
218
219 /* Clear the Machine Check Syndrome Re
220 li r0,0
221 mtspr SPRN_MCSR,r0
222
223 /* Let's move on */
224 lis r4,start_kernel@h
225 ori r4,r4,start_kernel@l
226 lis r3,MSR_KERNEL@h
227 ori r3,r3,MSR_KERNEL@l
228 mtspr SPRN_SRR0,r4
229 mtspr SPRN_SRR1,r3
230 rfi /* change cont
231
232 /*
233 * Interrupt vector entry code
234 *
235 * The Book E MMUs are always on so we don't n
236 * interrupts in real mode as with previous PP
237 * this case we handle interrupts in the kerne
238 * space.
239 *
240 * Interrupt vectors are dynamically placed re
241 * interrupt prefix as determined by the addre
242 * The interrupt vectors offsets are programme
243 * for each interrupt vector entry.
244 *
245 * Interrupt vectors must be aligned on a 16 b
246 * We align on a 32 byte cache line boundary f
247 */
248
249 interrupt_base:
250 /* Critical Input Interrupt */
251 CRITICAL_EXCEPTION(0x0100, CRITICAL, C
252
253 /* Machine Check Interrupt */
254 CRITICAL_EXCEPTION(0x0200, MACHINE_CHE
255 machine_check_excep
256 MCHECK_EXCEPTION(0x0210, MachineCheckA
257
258 /* Data Storage Interrupt */
259 DATA_STORAGE_EXCEPTION
260
261 /* Instruction Storage Interru
262 INSTRUCTION_STORAGE_EXCEPTION
263
264 /* External Input Interrupt */
265 EXCEPTION(0x0500, BOOKE_INTERRUPT_EXTE
266
267 /* Alignment Interrupt */
268 ALIGNMENT_EXCEPTION
269
270 /* Program Interrupt */
271 PROGRAM_EXCEPTION
272
273 /* Floating Point Unavailable Interrup
274 #ifdef CONFIG_PPC_FPU
275 FP_UNAVAILABLE_EXCEPTION
276 #else
277 EXCEPTION(0x2010, BOOKE_INTERRUPT_FP_U
278 FloatingPointUnavailable, un
279 #endif
280 /* System Call Interrupt */
281 START_EXCEPTION(SystemCall)
282 SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_
283
284 /* Auxiliary Processor Unavailable Int
285 EXCEPTION(0x2020, BOOKE_INTERRUPT_AP_U
286 AuxillaryProcessorUnavailabl
287
288 /* Decrementer Interrupt */
289 DECREMENTER_EXCEPTION
290
291 /* Fixed Internal Timer Interrupt */
292 /* TODO: Add FIT support */
293 EXCEPTION(0x1010, BOOKE_INTERRUPT_FIT,
294
295 /* Watchdog Timer Interrupt */
296 /* TODO: Add watchdog support */
297 #ifdef CONFIG_BOOKE_WDT
298 CRITICAL_EXCEPTION(0x1020, WATCHDOG, W
299 #else
300 CRITICAL_EXCEPTION(0x1020, WATCHDOG, W
301 #endif
302
303 /* Data TLB Error Interrupt */
304 START_EXCEPTION(DataTLBError44x)
305 mtspr SPRN_SPRG_WSCRATCH0, r10
306 mtspr SPRN_SPRG_WSCRATCH1, r11
307 mtspr SPRN_SPRG_WSCRATCH2, r12
308 mtspr SPRN_SPRG_WSCRATCH3, r13
309 mfcr r11
310 mtspr SPRN_SPRG_WSCRATCH4, r11
311 mfspr r10, SPRN_DEAR /* Get
312
313 /* If we are faulting a kernel address
314 * kernel page tables.
315 */
316 lis r11, PAGE_OFFSET@h
317 cmplw cr7, r10, r11
318 blt+ cr7, 3f
319 lis r11, swapper_pg_dir@h
320 ori r11, r11, swapper_pg_dir@l
321
322 mfspr r12,SPRN_MMUCR
323 rlwinm r12,r12,0,0,23 /* Cle
324
325 b 4f
326
327 /* Get the PGD for the current thread
328 3:
329 mfspr r11,SPRN_SPRG_THREAD
330 lwz r11,PGDIR(r11)
331
332 /* Load PID into MMUCR TID */
333 mfspr r12,SPRN_MMUCR
334 mfspr r13,SPRN_PID /* Get
335 rlwimi r12,r13,0,24,31 /* Set
336 #ifdef CONFIG_PPC_KUAP
337 cmpwi r13,0
338 beq 2f /* KUA
339 #endif
340
341 4:
342 mtspr SPRN_MMUCR,r12
343
344 /* Mask of required permission bits. N
345 * do copy ESR:ST to _PAGE_WRITE posit
346 * to an RO page is pretty common, we
347 * _PAGE_DIRTY. We could do it, but it
348 * event so I'd rather take the overhe
349 * rather than adding an instruction h
350 * whether the whole thing is worth it
351 * as we could avoid loading SPRN_ESR
352 * place...
353 *
354 * TODO: Is it worth doing that mfspr
355 * place or can we save a couple
356 */
357 mfspr r12,SPRN_ESR
358 li r13,_PAGE_PRESENT|_PAGE_ACCESS
359 rlwimi r13,r12,10,30,30
360
361 /* Load the PTE */
362 /* Compute pgdir/pmd offset */
363 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT
364 lwzx r11, r12, r11 /* Get
365 rlwinm. r12, r11, 0, 0, 20 /* Ext
366 beq 2f /* Bai
367
368 /* Compute pte address */
369 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT
370 lwz r11, 0(r12) /* Get
371 lwz r12, 4(r12) /* Get
372
373 lis r10,tlb_44x_index@ha
374
375 andc. r13,r13,r12 /* Che
376
377 /* Load the next available TLB index *
378 lwz r13,tlb_44x_index@l(r10)
379
380 bne 2f /* Bai
381
382 /* Increment, rollover, and store TLB
383 addi r13,r13,1
384
385 patch_site 0f, patch__tlb_44x_hwater_D
386 /* Compare with watermark (instruction
387 0: cmpwi 0,r13,1 /* res
388 ble 5f
389 li r13,0
390 5:
391 /* Store the next available TLB index
392 stw r13,tlb_44x_index@l(r10)
393
394 /* Re-load the faulting address */
395 mfspr r10,SPRN_DEAR
396
397 /* Jump to common tlb load */
398 b finish_tlb_load_44x
399
400 2:
401 /* The bailout. Restore registers to
402 * and call the heavyweights to help u
403 */
404 mfspr r11, SPRN_SPRG_RSCRATCH4
405 mtcr r11
406 mfspr r13, SPRN_SPRG_RSCRATCH3
407 mfspr r12, SPRN_SPRG_RSCRATCH2
408 mfspr r11, SPRN_SPRG_RSCRATCH1
409 mfspr r10, SPRN_SPRG_RSCRATCH0
410 b DataStorage
411
412 /* Instruction TLB Error Interrupt */
413 /*
414 * Nearly the same as above, except we
415 * information from different register
416 * to a different point.
417 */
418 START_EXCEPTION(InstructionTLBError44x
419 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Sa
420 mtspr SPRN_SPRG_WSCRATCH1, r11
421 mtspr SPRN_SPRG_WSCRATCH2, r12
422 mtspr SPRN_SPRG_WSCRATCH3, r13
423 mfcr r11
424 mtspr SPRN_SPRG_WSCRATCH4, r11
425 mfspr r10, SPRN_SRR0 /* Get
426
427 /* If we are faulting a kernel address
428 * kernel page tables.
429 */
430 lis r11, PAGE_OFFSET@h
431 cmplw cr7, r10, r11
432 blt+ cr7, 3f
433 lis r11, swapper_pg_dir@h
434 ori r11, r11, swapper_pg_dir@l
435
436 mfspr r12,SPRN_MMUCR
437 rlwinm r12,r12,0,0,23 /* Cle
438
439 b 4f
440
441 /* Get the PGD for the current thread
442 3:
443 mfspr r11,SPRN_SPRG_THREAD
444 lwz r11,PGDIR(r11)
445
446 /* Load PID into MMUCR TID */
447 mfspr r12,SPRN_MMUCR
448 mfspr r13,SPRN_PID /* Get
449 rlwimi r12,r13,0,24,31 /* Set
450 #ifdef CONFIG_PPC_KUAP
451 cmpwi r13,0
452 beq 2f /* KUA
453 #endif
454
455 4:
456 mtspr SPRN_MMUCR,r12
457
458 /* Make up the required permissions */
459 li r13,_PAGE_PRESENT | _PAGE_ACCE
460
461 /* Compute pgdir/pmd offset */
462 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT
463 lwzx r11, r12, r11 /* Get
464 rlwinm. r12, r11, 0, 0, 20 /* Ext
465 beq 2f /* Bai
466
467 /* Compute pte address */
468 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT
469 lwz r11, 0(r12) /* Get
470 lwz r12, 4(r12) /* Get
471
472 lis r10,tlb_44x_index@ha
473
474 andc. r13,r13,r12 /* Che
475
476 /* Load the next available TLB index *
477 lwz r13,tlb_44x_index@l(r10)
478
479 bne 2f /* Bai
480
481 /* Increment, rollover, and store TLB
482 addi r13,r13,1
483
484 patch_site 0f, patch__tlb_44x_hwater_I
485 /* Compare with watermark (instruction
486 0: cmpwi 0,r13,1 /* res
487 ble 5f
488 li r13,0
489 5:
490 /* Store the next available TLB index
491 stw r13,tlb_44x_index@l(r10)
492
493 /* Re-load the faulting address */
494 mfspr r10,SPRN_SRR0
495
496 /* Jump to common TLB load point */
497 b finish_tlb_load_44x
498
499 2:
500 /* The bailout. Restore registers to
501 * and call the heavyweights to help u
502 */
503 mfspr r11, SPRN_SPRG_RSCRATCH4
504 mtcr r11
505 mfspr r13, SPRN_SPRG_RSCRATCH3
506 mfspr r12, SPRN_SPRG_RSCRATCH2
507 mfspr r11, SPRN_SPRG_RSCRATCH1
508 mfspr r10, SPRN_SPRG_RSCRATCH0
509 b InstructionStorage
510
511 /*
512 * Both the instruction and data TLB miss get
513 * point to load the TLB.
514 * r10 - EA of fault
515 * r11 - PTE high word value
516 * r12 - PTE low word value
517 * r13 - TLB index
518 * cr7 - Result of comparison with PAGE_O
519 * MMUCR - loaded with proper value when
520 * Upon exit, we reload everything and RF
521 */
522 finish_tlb_load_44x:
523 /* Combine RPN & ERPN an write WS 0 */
524 rlwimi r11,r12,0,0,31-PAGE_SHIFT
525 tlbwe r11,r13,PPC44x_TLB_XLAT
526
527 /*
528 * Create WS1. This is the faulting ad
529 * page size, and valid flag.
530 */
531 li r11,PPC44x_TLB_VALID | PPC44x_
532 /* Insert valid and page size */
533 rlwimi r10,r11,0,PPC44x_PTE_ADD_MASK_
534 tlbwe r10,r13,PPC44x_TLB_PAGEID
535
536 /* And WS 2 */
537 li r10,0xf84
538 rlwimi r10,r12,29,30,31
539 and r11,r12,r10
540 bge cr7,1f /* Use
541 rlwimi r11,r11,3,26,28
542 rlwinm r11,r11,0,~PPC44x_TLB_SX
543 1: tlbwe r11,r13,PPC44x_TLB_ATTRIB
544
545 /* Done...restore registers and get ou
546 */
547 mfspr r11, SPRN_SPRG_RSCRATCH4
548 mtcr r11
549 mfspr r13, SPRN_SPRG_RSCRATCH3
550 mfspr r12, SPRN_SPRG_RSCRATCH2
551 mfspr r11, SPRN_SPRG_RSCRATCH1
552 mfspr r10, SPRN_SPRG_RSCRATCH0
553 rfi
554
555 /* TLB error interrupts for 476
556 */
557 #ifdef CONFIG_PPC_47x
558 START_EXCEPTION(DataTLBError47x)
559 mtspr SPRN_SPRG_WSCRATCH0,r10 /* Sav
560 mtspr SPRN_SPRG_WSCRATCH1,r11
561 mtspr SPRN_SPRG_WSCRATCH2,r12
562 mtspr SPRN_SPRG_WSCRATCH3,r13
563 mfcr r11
564 mtspr SPRN_SPRG_WSCRATCH4,r11
565 mfspr r10,SPRN_DEAR /* Get
566
567 /* If we are faulting a kernel address
568 * kernel page tables.
569 */
570 lis r11,PAGE_OFFSET@h
571 cmplw cr7,r10,r11
572 blt+ cr7,3f
573 lis r11,swapper_pg_dir@h
574 ori r11,r11, swapper_pg_dir@l
575 li r12,0 /* MMU
576 b 4f
577
578 /* Get the PGD for the current thread
579 3: mfspr r11,SPRN_SPRG3
580 lwz r11,PGDIR(r11)
581 mfspr r12,SPRN_PID /* Get
582 #ifdef CONFIG_PPC_KUAP
583 cmpwi r12,0
584 beq 2f /* KUA
585 #endif
586 4: mtspr SPRN_MMUCR,r12 /* Set
587
588 /* Mask of required permission bits. N
589 * do copy ESR:ST to _PAGE_WRITE posit
590 * to an RO page is pretty common, we
591 * _PAGE_DIRTY. We could do it, but it
592 * event so I'd rather take the overhe
593 * rather than adding an instruction h
594 * whether the whole thing is worth it
595 * as we could avoid loading SPRN_ESR
596 * place...
597 *
598 * TODO: Is it worth doing that mfspr
599 * place or can we save a couple
600 */
601 mfspr r12,SPRN_ESR
602 li r13,_PAGE_PRESENT|_PAGE_ACCESS
603 rlwimi r13,r12,10,30,30
604
605 /* Load the PTE */
606 /* Compute pgdir/pmd offset */
607 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,P
608 lwzx r11,r12,r11 /* Get
609
610 /* Word 0 is EPN,V,TS,DSIZ */
611 li r12,PPC47x_TLB0_VALID | PPC47x
612 rlwimi r10,r12,0,32-PAGE_SHIFT,31
613 li r12,0
614 tlbwe r10,r12,0
615
616 /* XXX can we do better ? Need to make
617 * latch V bit in MMUCR0 before the PT
618 #ifdef CONFIG_SMP
619 isync
620 #endif
621
622 rlwinm. r12,r11,0,0,20 /* Ext
623 /* Compute pte address */
624 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,P
625 beq 2f /* Bai
626 lwz r11,0(r12) /* Get
627
628 /* XXX can we do better ? maybe insert
629 * bottom of r12 to create a data depe
630 * as destination nowadays
631 */
632 #ifdef CONFIG_SMP
633 lwsync
634 #endif
635 lwz r12,4(r12) /* Get
636
637 andc. r13,r13,r12 /* Che
638
639 /* Jump to common tlb load */
640 beq finish_tlb_load_47x
641
642 2: /* The bailout. Restore registers to
643 * and call the heavyweights to help u
644 */
645 mfspr r11,SPRN_SPRG_RSCRATCH4
646 mtcr r11
647 mfspr r13,SPRN_SPRG_RSCRATCH3
648 mfspr r12,SPRN_SPRG_RSCRATCH2
649 mfspr r11,SPRN_SPRG_RSCRATCH1
650 mfspr r10,SPRN_SPRG_RSCRATCH0
651 b DataStorage
652
653 /* Instruction TLB Error Interrupt */
654 /*
655 * Nearly the same as above, except we
656 * information from different register
657 * to a different point.
658 */
659 START_EXCEPTION(InstructionTLBError47x
660 mtspr SPRN_SPRG_WSCRATCH0,r10 /* Sav
661 mtspr SPRN_SPRG_WSCRATCH1,r11
662 mtspr SPRN_SPRG_WSCRATCH2,r12
663 mtspr SPRN_SPRG_WSCRATCH3,r13
664 mfcr r11
665 mtspr SPRN_SPRG_WSCRATCH4,r11
666 mfspr r10,SPRN_SRR0 /* Get
667
668 /* If we are faulting a kernel address
669 * kernel page tables.
670 */
671 lis r11,PAGE_OFFSET@h
672 cmplw cr7,r10,r11
673 blt+ cr7,3f
674 lis r11,swapper_pg_dir@h
675 ori r11,r11, swapper_pg_dir@l
676 li r12,0 /* MMU
677 b 4f
678
679 /* Get the PGD for the current thread
680 3: mfspr r11,SPRN_SPRG_THREAD
681 lwz r11,PGDIR(r11)
682 mfspr r12,SPRN_PID /* Get
683 #ifdef CONFIG_PPC_KUAP
684 cmpwi r12,0
685 beq 2f /* KUA
686 #endif
687 4: mtspr SPRN_MMUCR,r12 /* Set
688
689 /* Make up the required permissions */
690 li r13,_PAGE_PRESENT | _PAGE_ACCE
691
692 /* Load PTE */
693 /* Compute pgdir/pmd offset */
694 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,P
695 lwzx r11,r12,r11 /* Get
696
697 /* Word 0 is EPN,V,TS,DSIZ */
698 li r12,PPC47x_TLB0_VALID | PPC47x
699 rlwimi r10,r12,0,32-PAGE_SHIFT,31
700 li r12,0
701 tlbwe r10,r12,0
702
703 /* XXX can we do better ? Need to make
704 * latch V bit in MMUCR0 before the PT
705 #ifdef CONFIG_SMP
706 isync
707 #endif
708
709 rlwinm. r12,r11,0,0,20 /* Ext
710 /* Compute pte address */
711 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,P
712 beq 2f /* Bai
713
714 lwz r11,0(r12) /* Get
715 /* XXX can we do better ? maybe insert
716 * bottom of r12 to create a data depe
717 * as destination nowadays
718 */
719 #ifdef CONFIG_SMP
720 lwsync
721 #endif
722 lwz r12,4(r12) /* Get
723
724 andc. r13,r13,r12 /* Che
725
726 /* Jump to common TLB load point */
727 beq finish_tlb_load_47x
728
729 2: /* The bailout. Restore registers to
730 * and call the heavyweights to help u
731 */
732 mfspr r11, SPRN_SPRG_RSCRATCH4
733 mtcr r11
734 mfspr r13, SPRN_SPRG_RSCRATCH3
735 mfspr r12, SPRN_SPRG_RSCRATCH2
736 mfspr r11, SPRN_SPRG_RSCRATCH1
737 mfspr r10, SPRN_SPRG_RSCRATCH0
738 b InstructionStorage
739
740 /*
741 * Both the instruction and data TLB miss get
742 * point to load the TLB.
743 * r10 - free to use
744 * r11 - PTE high word value
745 * r12 - PTE low word value
746 * r13 - free to use
747 * cr7 - Result of comparison with PAGE_O
748 * MMUCR - loaded with proper value when
749 * Upon exit, we reload everything and RF
750 */
751 finish_tlb_load_47x:
752 /* Combine RPN & ERPN an write WS 1 */
753 rlwimi r11,r12,0,0,31-PAGE_SHIFT
754 tlbwe r11,r13,1
755
756 /* And make up word 2 */
757 li r10,0xf84
758 rlwimi r10,r12,29,30,31
759 and r11,r12,r10
760 bge cr7,1f /* Use
761 rlwimi r11,r11,3,26,28
762 rlwinm r11,r11,0,~PPC47x_TLB2_SX
763 1: tlbwe r11,r13,2
764
765 /* Done...restore registers and get ou
766 */
767 mfspr r11, SPRN_SPRG_RSCRATCH4
768 mtcr r11
769 mfspr r13, SPRN_SPRG_RSCRATCH3
770 mfspr r12, SPRN_SPRG_RSCRATCH2
771 mfspr r11, SPRN_SPRG_RSCRATCH1
772 mfspr r10, SPRN_SPRG_RSCRATCH0
773 rfi
774
775 #endif /* CONFIG_PPC_47x */
776
777 /* Debug Interrupt */
778 /*
779 * This statement needs to exist at th
780 * definition just in case you end up
781 * exception within another exception.
782 */
783 DEBUG_CRIT_EXCEPTION
784
785 interrupt_end:
786
787 /*
788 * Global functions
789 */
790
791 /*
792 * Adjust the machine check IVOR on 440A cores
793 */
794 _GLOBAL(__fixup_440A_mcheck)
795 li r3,MachineCheckA@l
796 mtspr SPRN_IVOR1,r3
797 sync
798 blr
799
800 /*
801 * Init CPU state. This is called at boot time
802 * to setup initial TLB entries, setup IVORs,
803 *
804 */
805 _GLOBAL(init_cpu_state)
806 mflr r22
807 #ifdef CONFIG_PPC_47x
808 /* We use the PVR to differentiate 44x
809 mfspr r3,SPRN_PVR
810 srwi r3,r3,16
811 cmplwi cr0,r3,PVR_476FPE@h
812 beq head_start_47x
813 cmplwi cr0,r3,PVR_476@h
814 beq head_start_47x
815 cmplwi cr0,r3,PVR_476_ISS@h
816 beq head_start_47x
817 #endif /* CONFIG_PPC_47x */
818
819 /*
820 * In case the firmware didn't do it, we apply
821 * that are good for all 440 core variants her
822 */
823 mfspr r3,SPRN_CCR0
824 rlwinm r3,r3,0,0,27 /* disable ica
825 isync
826 mtspr SPRN_CCR0,r3
827 isync
828 sync
829
830 /*
831 * Set up the initial MMU state for 44x
832 *
833 * We are still executing code at the virtual
834 * mappings set by the firmware for the base o
835 *
836 * We first invalidate all TLB entries but the
837 * we are running from. We then load the KERN
838 * mappings so we can begin to use kernel addr
839 * natively and so the interrupt vector locati
840 * permanently pinned (necessary since Book E
841 * implementations always have translation ena
842 *
843 * TODO: Use the known TLB entry we are runnin
844 * determine which physical region we ar
845 * in. This can be used to determine wh
846 * (on a shared CPU system) or PCI memor
847 * (on a DRAMless system) we are located
848 * For now, we assume a perfect world wh
849 * we are located at the base of DRAM (p
850 */
851
852 /*
853 * Search TLB for entry that we are currently
854 * Invalidate all entries but the one we are u
855 */
856 /* Load our current PID->MMUCR TID and
857 mfspr r3,SPRN_PID
858 mfmsr r4
859 andi. r4,r4,MSR_IS@l
860 beq wmmucr
861 oris r3,r3,PPC44x_MMUCR_STS@h
862 wmmucr: mtspr SPRN_MMUCR,r3
863 sync
864
865 bcl 20,31,$+4
866 invstr: mflr r5
867 tlbsx r23,0,r5
868 li r4,0
869 li r3,0
870 1: cmpw r23,r4
871 beq skpinv
872 tlbwe r3,r4,PPC44x_TLB_PAGEID
873 skpinv: addi r4,r4,1
874 cmpwi r4,64
875 bne 1b
876 isync
877
878 /*
879 * Configure and load pinned entry into TLB sl
880 */
881 #ifdef CONFIG_NONSTATIC_KERNEL
882 /*
883 * In case of a NONSTATIC_KERNEL we re
884 * entries of the initial mapping set
885 * The XLAT entry is stored in r25
886 */
887
888 /* Read the XLAT entry for our current
889 tlbre r25,r23,PPC44x_TLB_XLAT
890
891 lis r3,KERNELBASE@h
892 ori r3,r3,KERNELBASE@l
893
894 /* Use our current RPN entry */
895 mr r4,r25
896 #else
897
898 lis r3,PAGE_OFFSET@h
899 ori r3,r3,PAGE_OFFSET@l
900
901 /* Kernel is at the base of RAM */
902 li r4, 0 /* Loa
903 #endif
904
905 /* Load the kernel PID = 0 */
906 li r0,0
907 mtspr SPRN_PID,r0
908 sync
909
910 /* Initialize MMUCR */
911 li r5,0
912 mtspr SPRN_MMUCR,r5
913 sync
914
915 /* pageid fields */
916 clrrwi r3,r3,10 /* Mas
917 ori r3,r3,PPC44x_TLB_VALID | PPC44
918
919 /* xlat fields */
920 clrrwi r4,r4,10 /* Mas
921 /* ERP
922
923 /* attrib fields */
924 /* Added guarded bit to protect agains
925 li r5,0
926 ori r5,r5,(PPC44x_TLB_SW | PPC44x_
927
928 li r0,63 /* TL
929
930 tlbwe r3,r0,PPC44x_TLB_PAGEID /* Loa
931 tlbwe r4,r0,PPC44x_TLB_XLAT /* Loa
932 tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Loa
933
934 /* Force context change */
935 mfmsr r0
936 mtspr SPRN_SRR1, r0
937 lis r0,3f@h
938 ori r0,r0,3f@l
939 mtspr SPRN_SRR0,r0
940 sync
941 rfi
942
943 /* If necessary, invalidate original e
944 3: cmpwi r23,63
945 beq 4f
946 li r6,0
947 tlbwe r6,r23,PPC44x_TLB_PAGEID
948 isync
949
950 4:
951 #ifdef CONFIG_PPC_EARLY_DEBUG_44x
952 /* Add UART mapping for early debug. *
953
954 /* pageid fields */
955 lis r3,PPC44x_EARLY_DEBUG_VIRTADDR
956 ori r3,r3,PPC44x_TLB_VALID|PPC44x_
957
958 /* xlat fields */
959 lis r4,CONFIG_PPC_EARLY_DEBUG_44x_
960 ori r4,r4,CONFIG_PPC_EARLY_DEBUG_4
961
962 /* attrib fields */
963 li r5,(PPC44x_TLB_SW|PPC44x_TLB_S
964 li r0,62 /* TL
965
966 tlbwe r3,r0,PPC44x_TLB_PAGEID
967 tlbwe r4,r0,PPC44x_TLB_XLAT
968 tlbwe r5,r0,PPC44x_TLB_ATTRIB
969
970 /* Force context change */
971 isync
972 #endif /* CONFIG_PPC_EARLY_DEBUG_44x */
973
974 /* Establish the interrupt vector offs
975 SET_IVOR(0, CriticalInput);
976 SET_IVOR(1, MachineCheck);
977 SET_IVOR(2, DataStorage);
978 SET_IVOR(3, InstructionStorage);
979 SET_IVOR(4, ExternalInput);
980 SET_IVOR(5, Alignment);
981 SET_IVOR(6, Program);
982 SET_IVOR(7, FloatingPointUnavailable)
983 SET_IVOR(8, SystemCall);
984 SET_IVOR(9, AuxillaryProcessorUnavail
985 SET_IVOR(10, Decrementer);
986 SET_IVOR(11, FixedIntervalTimer);
987 SET_IVOR(12, WatchdogTimer);
988 SET_IVOR(13, DataTLBError44x);
989 SET_IVOR(14, InstructionTLBError44x);
990 SET_IVOR(15, DebugCrit);
991
992 b head_start_common
993
994
995 #ifdef CONFIG_PPC_47x
996
997 #ifdef CONFIG_SMP
998
999 /* Entry point for secondary 47x processors */
1000 _GLOBAL(start_secondary_47x)
1001 mr r24,r3 /* CPU number
1002
1003 bl init_cpu_state
1004
1005 /* Now we need to bolt the rest of ke
1006 * is done in C code. We must be care
1007 * struct or our stack can (and will
1008 * of reach of the initial 256M TLB e
1009 * small temporary stack in .bss for
1010 * because only one CPU at a time can
1011 */
1012 lis r1,temp_boot_stack@h
1013 ori r1,r1,temp_boot_stack@l
1014 addi r1,r1,1024-STACK_FRAME_MIN_SI
1015 li r0,0
1016 stw r0,0(r1)
1017 bl mmu_init_secondary
1018
1019 /* Now we can get our task struct and
1020
1021 /* Get current's stack and current */
1022 lis r2,secondary_current@ha
1023 lwz r2,secondary_current@l(r2)
1024 lwz r1,TASK_STACK(r2)
1025
1026 /* Current stack pointer */
1027 addi r1,r1,THREAD_SIZE-STACK_FRAME
1028 li r0,0
1029 stw r0,0(r1)
1030
1031 /* Kernel stack for exception entry i
1032 addi r4,r2,THREAD /* init task'
1033 mtspr SPRN_SPRG3,r4
1034
1035 b start_secondary
1036
1037 #endif /* CONFIG_SMP */
1038
1039 /*
1040 * Set up the initial MMU state for 44x
1041 *
1042 * We are still executing code at the virtual
1043 * mappings set by the firmware for the base
1044 */
1045
1046 head_start_47x:
1047 /* Load our current PID->MMUCR TID an
1048 mfspr r3,SPRN_PID
1049 mfmsr r4
1050 andi. r4,r4,MSR_IS@l
1051 beq 1f
1052 oris r3,r3,PPC47x_MMUCR_STS@h
1053 1: mtspr SPRN_MMUCR,r3
1054 sync
1055
1056 /* Find the entry we are running from
1057 bcl 20,31,$+4
1058 1: mflr r23
1059 tlbsx r23,0,r23
1060 tlbre r24,r23,0
1061 tlbre r25,r23,1
1062 tlbre r26,r23,2
1063
1064 /*
1065 * Cleanup time
1066 */
1067
1068 /* Initialize MMUCR */
1069 li r5,0
1070 mtspr SPRN_MMUCR,r5
1071 sync
1072
1073 clear_all_utlb_entries:
1074
1075 #; Set initial values.
1076
1077 addis r3,0,0x8000
1078 addi r4,0,0
1079 addi r5,0,0
1080 b clear_utlb_entry
1081
1082 #; Align the loop to speed things up.
1083
1084 .align 6
1085
1086 clear_utlb_entry:
1087
1088 tlbwe r4,r3,0
1089 tlbwe r5,r3,1
1090 tlbwe r5,r3,2
1091 addis r3,r3,0x2000
1092 cmpwi r3,0
1093 bne clear_utlb_entry
1094 addis r3,0,0x8000
1095 addis r4,r4,0x100
1096 cmpwi r4,0
1097 bne clear_utlb_entry
1098
1099 #; Restore original entry.
1100
1101 oris r23,r23,0x8000 /* specify th
1102 tlbwe r24,r23,0
1103 tlbwe r25,r23,1
1104 tlbwe r26,r23,2
1105
1106 /*
1107 * Configure and load pinned entry into TLB f
1108 */
1109
1110 lis r3,PAGE_OFFSET@h
1111 ori r3,r3,PAGE_OFFSET@l
1112
1113 /* Load the kernel PID = 0 */
1114 li r0,0
1115 mtspr SPRN_PID,r0
1116 sync
1117
1118 /* Word 0 */
1119 clrrwi r3,r3,12 /* Ma
1120 ori r3,r3,PPC47x_TLB0_VALID | PPC
1121
1122 /* Word 1 - use r25. RPN is the same
1123
1124 /* Word 2 */
1125 li r5,0
1126 ori r5,r5,PPC47x_TLB2_S_RWX
1127 #ifdef CONFIG_SMP
1128 ori r5,r5,PPC47x_TLB2_M
1129 #endif
1130
1131 /* We write to way 0 and bolted 0 */
1132 lis r0,0x8800
1133 tlbwe r3,r0,0
1134 tlbwe r25,r0,1
1135 tlbwe r5,r0,2
1136
1137 /*
1138 * Configure SSPCR, ISPCR and USPCR for now t
1139 * them up later
1140 */
1141 LOAD_REG_IMMEDIATE(r3, 0x9abcdef0)
1142 mtspr SPRN_SSPCR,r3
1143 mtspr SPRN_USPCR,r3
1144 LOAD_REG_IMMEDIATE(r3, 0x12345670)
1145 mtspr SPRN_ISPCR,r3
1146
1147 /* Force context change */
1148 mfmsr r0
1149 mtspr SPRN_SRR1, r0
1150 lis r0,3f@h
1151 ori r0,r0,3f@l
1152 mtspr SPRN_SRR0,r0
1153 sync
1154 rfi
1155
1156 /* Invalidate original entry we used
1157 3:
1158 rlwinm r24,r24,0,21,19 /* clear the
1159 tlbwe r24,r23,0
1160 addi r24,0,0
1161 tlbwe r24,r23,1
1162 tlbwe r24,r23,2
1163 isync /* Clear out
1164
1165 #ifdef CONFIG_PPC_EARLY_DEBUG_44x
1166 /* Add UART mapping for early debug.
1167
1168 /* Word 0 */
1169 lis r3,PPC44x_EARLY_DEBUG_VIRTADD
1170 ori r3,r3,PPC47x_TLB0_VALID | PPC
1171
1172 /* Word 1 */
1173 lis r4,CONFIG_PPC_EARLY_DEBUG_44x
1174 ori r4,r4,CONFIG_PPC_EARLY_DEBUG_
1175
1176 /* Word 2 */
1177 li r5,(PPC47x_TLB2_S_RW | PPC47x
1178
1179 /* Bolted in way 0, bolt slot 5, we -
1180 * congruence class as the kernel, we
1181 * some point
1182 */
1183 lis r0,0x8d00
1184 tlbwe r3,r0,0
1185 tlbwe r4,r0,1
1186 tlbwe r5,r0,2
1187
1188 /* Force context change */
1189 isync
1190 #endif /* CONFIG_PPC_EARLY_DEBUG_44x */
1191
1192 /* Establish the interrupt vector off
1193 SET_IVOR(0, CriticalInput);
1194 SET_IVOR(1, MachineCheckA);
1195 SET_IVOR(2, DataStorage);
1196 SET_IVOR(3, InstructionStorage);
1197 SET_IVOR(4, ExternalInput);
1198 SET_IVOR(5, Alignment);
1199 SET_IVOR(6, Program);
1200 SET_IVOR(7, FloatingPointUnavailable
1201 SET_IVOR(8, SystemCall);
1202 SET_IVOR(9, AuxillaryProcessorUnavai
1203 SET_IVOR(10, Decrementer);
1204 SET_IVOR(11, FixedIntervalTimer);
1205 SET_IVOR(12, WatchdogTimer);
1206 SET_IVOR(13, DataTLBError47x);
1207 SET_IVOR(14, InstructionTLBError47x);
1208 SET_IVOR(15, DebugCrit);
1209
1210 /* We configure icbi to invalidate 12
1211 * current 32-bit kernel code isn't t
1212 * block size. We also disable the BT
1213 * in some circumstances (see IBM Err
1214 */
1215 mfspr r3,SPRN_CCR0
1216 oris r3,r3,0x0020
1217 ori r3,r3,0x0040
1218 mtspr SPRN_CCR0,r3
1219 isync
1220
1221 #endif /* CONFIG_PPC_47x */
1222
1223 /*
1224 * Here we are back to code that is common be
1225 *
1226 * We proceed to further kernel initializatio
1227 * main kernel entry
1228 */
1229 head_start_common:
1230 /* Establish the interrupt vector bas
1231 lis r4,interrupt_base@h /* IV
1232 mtspr SPRN_IVPR,r4
1233
1234 /*
1235 * If the kernel was loaded at a non-
1236 * mask off the most significant 4 bi
1237 * from the start of physical memory
1238 */
1239 rlwinm r22,r22,0,4,31
1240 addis r22,r22,PAGE_OFFSET@h
1241 mtlr r22
1242 isync
1243 blr
1244
1245 #ifdef CONFIG_SMP
1246 .data
1247 .align 12
1248 temp_boot_stack:
1249 .space 1024
1250 #endif /* CONFIG_SMP */
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