1 /* SPDX-License-Identifier: GPL-2.0-or-later *
2 /*
3 * PowerPC version
4 * Copyright (C) 1995-1996 Gary Thomas (gdt
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu)
6 * Copyright (C) 1996 Cort Dougan <cort@cs.n
7 * Low-level exception handlers and MMU suppo
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications by Dan Malek
11 * Copyright (C) 1997 Dan Malek (dmalek@jlc
12 *
13 * This file contains low-level support and s
14 * embedded processors, including trap and in
15 */
16
17 #include <linux/init.h>
18 #include <linux/magic.h>
19 #include <linux/pgtable.h>
20 #include <linux/sizes.h>
21 #include <linux/linkage.h>
22
23 #include <asm/processor.h>
24 #include <asm/page.h>
25 #include <asm/mmu.h>
26 #include <asm/cache.h>
27 #include <asm/cputable.h>
28 #include <asm/thread_info.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/asm-offsets.h>
31 #include <asm/ptrace.h>
32 #include <asm/code-patching-asm.h>
33 #include <asm/interrupt.h>
34
35 /*
36 * Value for the bits that have fixed value in
37 * Also used for tagging DAR for DTLBerror.
38 */
39 #define RPN_PATTERN 0x00f0
40
41 #include "head_32.h"
42
43 #define PAGE_SHIFT_512K 19
44 #define PAGE_SHIFT_8M 23
45
46 __HEAD
47 _GLOBAL(_stext);
48 _GLOBAL(_start);
49
50 /* MPC8xx
51 * This port was done on an MBX board with an
52 * support an ELF compressed (zImage) boot fro
53 * code there loads up some registers before c
54 * r3: ptr to board info data
55 * r4: initrd_start or if no initrd then 0
56 * r5: initrd_end - unused if r4 is 0
57 * r6: Start of command line string
58 * r7: End of command line string
59 *
60 * I decided to use conditional compilation in
61 * adding more processor specific branches aro
62 * Since this is an embedded processor, I also
63 * savings I can get.
64 *
65 * The MPC8xx does not have any BATs, but it s
66 * We first initialize the MMU to support 8M b
67 * entry into each of the instruction and data
68 * 8M 1:1. I also mapped an additional I/O sp
69 * the "internal" processor registers before M
70 *
71 * -- Dan
72 */
73 .globl __start
74 __start:
75 mr r31,r3 /* sav
76
77 /* We have to turn on the MMU right aw
78 * set correctly.
79 */
80 bl initial_mmu
81
82 /* We now have the lower 8 Meg mapped into TLB
83 * ready to work.
84 */
85
86 turn_on_mmu:
87 mfmsr r0
88 ori r0,r0,MSR_DR|MSR_IR
89 mtspr SPRN_SRR1,r0
90 lis r0,start_here@h
91 ori r0,r0,start_here@l
92 mtspr SPRN_SRR0,r0
93 rfi /* ena
94
95
96 #ifdef CONFIG_PERF_EVENTS
97 .align 4
98
99 .globl itlb_miss_counter
100 itlb_miss_counter:
101 .space 4
102
103 .globl dtlb_miss_counter
104 dtlb_miss_counter:
105 .space 4
106
107 .globl instruction_counter
108 instruction_counter:
109 .space 4
110 #endif
111
112 /* System reset */
113 EXCEPTION(INTERRUPT_SYSTEM_RESET, Rese
114
115 /* Machine check */
116 START_EXCEPTION(INTERRUPT_MACHINE_CHEC
117 EXCEPTION_PROLOG INTERRUPT_MACHINE_CHE
118 prepare_transfer_to_handler
119 bl machine_check_exception
120 b interrupt_return
121
122 /* External interrupt */
123 EXCEPTION(INTERRUPT_EXTERNAL, Hardware
124
125 /* Alignment exception */
126 START_EXCEPTION(INTERRUPT_ALIGNMENT, A
127 EXCEPTION_PROLOG INTERRUPT_ALIGNMENT A
128 prepare_transfer_to_handler
129 bl alignment_exception
130 REST_NVGPRS(r1)
131 b interrupt_return
132
133 /* Program check exception */
134 START_EXCEPTION(INTERRUPT_PROGRAM, Pro
135 EXCEPTION_PROLOG INTERRUPT_PROGRAM Pro
136 prepare_transfer_to_handler
137 bl program_check_exception
138 REST_NVGPRS(r1)
139 b interrupt_return
140
141 /* Decrementer */
142 EXCEPTION(INTERRUPT_DECREMENTER, Decre
143
144 /* System call */
145 START_EXCEPTION(INTERRUPT_SYSCALL, Sys
146 SYSCALL_ENTRY INTERRUPT_SYSCALL
147
148 /* Single step - not used on 601 */
149 EXCEPTION(INTERRUPT_TRACE, SingleStep,
150
151 /* On the MPC8xx, this is a software emulation
152 * for all unimplemented and illegal instructi
153 */
154 START_EXCEPTION(INTERRUPT_SOFT_EMU_8xx
155 EXCEPTION_PROLOG INTERRUPT_SOFT_EMU_8x
156 prepare_transfer_to_handler
157 bl emulation_assist_interrupt
158 REST_NVGPRS(r1)
159 b interrupt_return
160
161 /*
162 * For the MPC8xx, this is a software tablewal
163 * TLB. The task switch loads the M_TWB regis
164 * level table.
165 * If we discover there is no second level tab
166 * is an invalid pte, we load that into the TL
167 * into the TLB Error interrupt where we can h
168 * We have to use the MD_xxx registers for the
169 * equivalent MI_xxx registers only perform th
170 */
171
172 #ifdef CONFIG_8xx_CPU15
173 #define INVALIDATE_ADJACENT_PAGES_CPU15(addr,
174 addi tmp, addr, PAGE_SIZE; \
175 tlbie tmp; \
176 addi tmp, addr, -PAGE_SIZE; \
177 tlbie tmp
178 #else
179 #define INVALIDATE_ADJACENT_PAGES_CPU15(addr,
180 #endif
181
182 START_EXCEPTION(INTERRUPT_INST_TLB_MIS
183 mtspr SPRN_SPRG_SCRATCH2, r10
184 mtspr SPRN_M_TW, r11
185
186 /* If we are faulting a kernel address
187 * kernel page tables.
188 */
189 mfspr r10, SPRN_SRR0 /* Get effecti
190 INVALIDATE_ADJACENT_PAGES_CPU15(r10, r
191 mtspr SPRN_MD_EPN, r10
192 mfspr r10, SPRN_M_TWB /* Get level 1
193 lwz r11, (swapper_pg_dir-PAGE_OFFS
194 mtspr SPRN_MD_TWC, r11
195 mfspr r10, SPRN_MD_TWC
196 lwz r10, 0(r10) /* Get the pte
197 rlwimi r11, r10, 0, _PAGE_GUARDED | _
198 rlwimi r11, r10, 32 - 9, _PMD_PAGE_51
199 mtspr SPRN_MI_TWC, r11
200 /* The Linux PTE won't go exactly into
201 * Software indicator bits 20 and 23 m
202 * Software indicator bits 22, 24, 25,
203 * set. All other Linux PTE bits cont
204 * of the MMU.
205 */
206 rlwinm r10, r10, 0, ~0x0f00 /* Cle
207 rlwimi r10, r10, 4, 0x0400 /* Cop
208 ori r10, r10, RPN_PATTERN | 0x200
209 mtspr SPRN_MI_RPN, r10 /* Upd
210
211 /* Restore registers */
212 0: mfspr r10, SPRN_SPRG_SCRATCH2
213 mfspr r11, SPRN_M_TW
214 rfi
215 patch_site 0b, patch__itlbmiss_ex
216
217 #ifdef CONFIG_PERF_EVENTS
218 patch_site 0f, patch__itlbmiss_pe
219 0: lwz r10, (itlb_miss_counter - PAGE
220 addi r10, r10, 1
221 stw r10, (itlb_miss_counter - PAGE
222 mfspr r10, SPRN_SPRG_SCRATCH2
223 mfspr r11, SPRN_M_TW
224 rfi
225 #endif
226
227 START_EXCEPTION(INTERRUPT_DATA_TLB_MIS
228 mtspr SPRN_SPRG_SCRATCH2, r10
229 mtspr SPRN_M_TW, r11
230
231 /* If we are faulting a kernel address
232 * kernel page tables.
233 */
234 mfspr r10, SPRN_MD_EPN
235 mfspr r10, SPRN_M_TWB /* Get level 1
236 lwz r11, (swapper_pg_dir-PAGE_OFFS
237
238 mtspr SPRN_MD_TWC, r11
239 mfspr r10, SPRN_MD_TWC
240 lwz r10, 0(r10) /* Get the pte
241
242 /* Insert Guarded and Accessed flags i
243 * It is bit 27 of both the Linux PTE
244 * I got that right :-). It will be b
245 * this into the Linux pgd/pmd and loa
246 * above.
247 */
248 rlwimi r11, r10, 0, _PAGE_GUARDED | _
249 rlwimi r11, r10, 32 - 9, _PMD_PAGE_51
250 mtspr SPRN_MD_TWC, r11
251
252 /* The Linux PTE won't go exactly into
253 * Software indicator bits 24, 25, 26,
254 * set. All other Linux PTE bits cont
255 * of the MMU.
256 */
257 li r11, RPN_PATTERN
258 rlwimi r10, r11, 0, 24, 27 /* Set
259 mtspr SPRN_MD_RPN, r10 /* Upd
260 mtspr SPRN_DAR, r11 /* Tag
261
262 /* Restore registers */
263
264 0: mfspr r10, SPRN_SPRG_SCRATCH2
265 mfspr r11, SPRN_M_TW
266 rfi
267 patch_site 0b, patch__dtlbmiss_ex
268
269 #ifdef CONFIG_PERF_EVENTS
270 patch_site 0f, patch__dtlbmiss_pe
271 0: lwz r10, (dtlb_miss_counter - PAGE
272 addi r10, r10, 1
273 stw r10, (dtlb_miss_counter - PAGE
274 mfspr r10, SPRN_SPRG_SCRATCH2
275 mfspr r11, SPRN_M_TW
276 rfi
277 #endif
278
279 /* This is an instruction TLB error on the MPC
280 * to many reasons, such as executing guarded
281 * addresses. There is nothing to do but hand
282 */
283 START_EXCEPTION(INTERRUPT_INST_TLB_ERR
284 /* 0x400 is InstructionAccess exceptio
285 EXCEPTION_PROLOG INTERRUPT_INST_STORAG
286 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /
287 andis. r10,r9,SRR1_ISI_NOPT@h
288 beq+ .Litlbie
289 tlbie r12
290 .Litlbie:
291 stw r12, _DAR(r11)
292 stw r5, _DSISR(r11)
293 prepare_transfer_to_handler
294 bl do_page_fault
295 b interrupt_return
296
297 /* This is the data TLB error on the MPC8xx.
298 * many reasons, including a dirty update to a
299 * a higher level function that can handle it.
300 */
301 START_EXCEPTION(INTERRUPT_DATA_TLB_ERR
302 EXCEPTION_PROLOG_0 handle_dar_dsisr=1
303 mfspr r11, SPRN_DAR
304 cmpwi cr1, r11, RPN_PATTERN
305 beq- cr1, FixupDAR /* must be a b
306 DARFixed:/* Return from dcbx instruction bug w
307 mfspr r11, SPRN_DSISR
308 rlwinm r11, r11, 0, DSISR_NOHPTE
309 cmpwi cr1, r11, 0
310 beq+ cr1, .Ldtlbie
311 mfspr r11, SPRN_DAR
312 tlbie r11
313 rlwinm r11, r11, 16, 0xffff
314 cmplwi cr1, r11, TASK_SIZE@h
315 bge- cr1, FixupPGD
316 .Ldtlbie:
317 EXCEPTION_PROLOG_1
318 /* 0x300 is DataAccess exception, need
319 EXCEPTION_PROLOG_2 INTERRUPT_DATA_STOR
320 prepare_transfer_to_handler
321 bl do_page_fault
322 b interrupt_return
323
324 #ifdef CONFIG_VMAP_STACK
325 vmap_stack_overflow_exception
326 #endif
327
328 /* On the MPC8xx, these next four traps are us
329 * support of breakpoints and such. Someday I
330 * using them.
331 */
332 START_EXCEPTION(INTERRUPT_DATA_BREAKPO
333 EXCEPTION_PROLOG_0 handle_dar_dsisr=1
334 mfspr r11, SPRN_SRR0
335 cmplwi cr1, r11, (.Ldtlbie - PAGE_OFF
336 cmplwi cr7, r11, (.Litlbie - PAGE_OFF
337 cror 4*cr1+eq, 4*cr1+eq, 4*cr7+eq
338 bne cr1, 1f
339 mtcr r10
340 mfspr r10, SPRN_SPRG_SCRATCH0
341 mfspr r11, SPRN_SPRG_SCRATCH1
342 rfi
343
344 1: EXCEPTION_PROLOG_1
345 EXCEPTION_PROLOG_2 INTERRUPT_DATA_BREA
346 mfspr r4,SPRN_BAR
347 stw r4,_DAR(r11)
348 prepare_transfer_to_handler
349 bl do_break
350 REST_NVGPRS(r1)
351 b interrupt_return
352
353 #ifdef CONFIG_PERF_EVENTS
354 START_EXCEPTION(INTERRUPT_INST_BREAKPO
355 mtspr SPRN_SPRG_SCRATCH0, r10
356 lwz r10, (instruction_counter - PA
357 addi r10, r10, -1
358 stw r10, (instruction_counter - PA
359 lis r10, 0xffff
360 ori r10, r10, 0x01
361 mtspr SPRN_COUNTA, r10
362 mfspr r10, SPRN_SPRG_SCRATCH0
363 rfi
364 #else
365 EXCEPTION(INTERRUPT_INST_BREAKPOINT_8x
366 #endif
367 EXCEPTION(0x1e00, Trap_1e, unknown_exc
368 EXCEPTION(0x1f00, Trap_1f, unknown_exc
369
370 __HEAD
371 . = 0x2000
372
373 FixupPGD:
374 mtspr SPRN_M_TW, r10
375 mfspr r10, SPRN_DAR
376 mtspr SPRN_MD_EPN, r10
377 mfspr r11, SPRN_M_TWB /* Get level 1
378 lwz r10, (swapper_pg_dir - PAGE_OF
379 cmpwi cr1, r10, 0
380 bne cr1, 1f
381
382 rlwinm r10, r11, 0, 20, 31
383 oris r10, r10, (swapper_pg_dir - PA
384 lwz r10, (swapper_pg_dir - PAGE_OF
385 cmpwi cr1, r10, 0
386 beq cr1, 1f
387 stw r10, (swapper_pg_dir - PAGE_OF
388 mfspr r10, SPRN_M_TW
389 mtcr r10
390 mfspr r10, SPRN_SPRG_SCRATCH0
391 mfspr r11, SPRN_SPRG_SCRATCH1
392 rfi
393 1:
394 mfspr r10, SPRN_M_TW
395 b .Ldtlbie
396
397 /* This is the procedure to calculate the data
398 * by decoding the registers used by the dcbx
399 * DAR is set to the calculated address.
400 */
401 FixupDAR:/* Entry point for dcbx workaround. *
402 mtspr SPRN_M_TW, r10
403 /* fetch instruction from memory. */
404 mfspr r10, SPRN_SRR0
405 mtspr SPRN_MD_EPN, r10
406 rlwinm r11, r10, 16, 0xfff8
407 cmpli cr1, r11, TASK_SIZE@h
408 mfspr r11, SPRN_M_TWB /* Get level 1
409 blt+ cr1, 3f
410
411 /* create physical page address from e
412 tophys(r11, r10)
413 mfspr r11, SPRN_M_TWB /* Get level 1
414 rlwinm r11, r11, 0, 20, 31
415 oris r11, r11, (swapper_pg_dir - PA
416 3:
417 lwz r11, (swapper_pg_dir-PAGE_OFFS
418 rlwinm r11, r11, 0, ~_PMD_PAGE_8M
419 mtspr SPRN_MD_TWC, r11
420 mfspr r11, SPRN_MD_TWC
421 lwz r11, 0(r11) /* Get the pte
422 /* concat physical page address(r11) a
423 rlwimi r11, r10, 0, 32 - PAGE_SHIFT,
424 lwz r11,0(r11)
425 /* Check if it really is a dcbx instruction. *
426 /* dcbt and dcbtst does not generate DTLB Miss
427 * no need to include them here */
428 xoris r10, r11, 0x7c00 /* che
429 rlwinm r10, r10, 0, 21, 5
430 cmpwi cr1, r10, 2028 /* Is dcbz? */
431 beq+ cr1, 142f
432 cmpwi cr1, r10, 940 /* Is dcbi? */
433 beq+ cr1, 142f
434 cmpwi cr1, r10, 108 /* Is dcbst? *
435 beq+ cr1, 144f /* Fix
436 cmpwi cr1, r10, 172 /* Is dcbf? */
437 beq+ cr1, 142f
438 cmpwi cr1, r10, 1964 /* Is icbi? */
439 beq+ cr1, 142f
440 141: mfspr r10,SPRN_M_TW
441 b DARFixed /* Nope, go ba
442
443 144: mfspr r10, SPRN_DSISR
444 rlwinm r10, r10,0,7,5 /* Clear store
445 mtspr SPRN_DSISR, r10
446 142: /* continue, it was a dcbx, dcbi instr
447 mfctr r10
448 mtdar r10 /* sav
449 rlwinm r10, r11, 24, 24, 28 /* off
450 addi r10, r10, 150f@l /* add
451 mtctr r10 /* loa
452 xor r10, r10, r10 /* sum
453 bctr /* jum
454 150:
455 add r10, r10, r0 ;b 151f
456 add r10, r10, r1 ;b 151f
457 add r10, r10, r2 ;b 151f
458 add r10, r10, r3 ;b 151f
459 add r10, r10, r4 ;b 151f
460 add r10, r10, r5 ;b 151f
461 add r10, r10, r6 ;b 151f
462 add r10, r10, r7 ;b 151f
463 add r10, r10, r8 ;b 151f
464 add r10, r10, r9 ;b 151f
465 mtctr r11 ;b 154f /* r10
466 mtctr r11 ;b 153f /* r11
467 add r10, r10, r12 ;b 151f
468 add r10, r10, r13 ;b 151f
469 add r10, r10, r14 ;b 151f
470 add r10, r10, r15 ;b 151f
471 add r10, r10, r16 ;b 151f
472 add r10, r10, r17 ;b 151f
473 add r10, r10, r18 ;b 151f
474 add r10, r10, r19 ;b 151f
475 add r10, r10, r20 ;b 151f
476 add r10, r10, r21 ;b 151f
477 add r10, r10, r22 ;b 151f
478 add r10, r10, r23 ;b 151f
479 add r10, r10, r24 ;b 151f
480 add r10, r10, r25 ;b 151f
481 add r10, r10, r26 ;b 151f
482 add r10, r10, r27 ;b 151f
483 add r10, r10, r28 ;b 151f
484 add r10, r10, r29 ;b 151f
485 add r10, r10, r30 ;b 151f
486 add r10, r10, r31
487 151:
488 rlwinm r11,r11,19,24,28 /* off
489 cmpwi cr1, r11, 0
490 beq cr1, 152f /* if
491 addi r11, r11, 150b@l /* add
492 mtctr r11 /* loa
493 rlwinm r11,r11,0,16,10 /* mak
494 bctr /* jum
495 152:
496 mfdar r11
497 mtdar r10
498 mtctr r11 /* res
499 mfspr r11, SPRN_SPRG_THREAD
500 stw r10, DAR(r11)
501 mfspr r10, SPRN_DSISR
502 stw r10, DSISR(r11)
503 mfspr r10,SPRN_M_TW
504 b DARFixed /* Go
505
506 /* special handling for r10,r11 since
507 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* loa
508 add r10, r10, r11 /* add it */
509 mfctr r11 /* restore r11
510 b 151b
511 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* loa
512 add r10, r10, r11 /* add it */
513 mfctr r11 /* restore r11
514 b 151b
515
516 /*
517 * This is where the main kernel code starts.
518 */
519 start_here:
520 /* ptr to current */
521 lis r2,init_task@h
522 ori r2,r2,init_task@l
523
524 /* ptr to phys current thread */
525 tophys(r4,r2)
526 addi r4,r4,THREAD /* init task's
527 mtspr SPRN_SPRG_THREAD,r4
528
529 /* stack */
530 lis r1,init_thread_union@ha
531 addi r1,r1,init_thread_union@l
532 lis r0, STACK_END_MAGIC@h
533 ori r0, r0, STACK_END_MAGIC@l
534 stw r0, 0(r1)
535 li r0,0
536 stwu r0,THREAD_SIZE-STACK_FRAME_MIN
537
538 lis r6, swapper_pg_dir@ha
539 tophys(r6,r6)
540 mtspr SPRN_M_TWB, r6
541
542 bl early_init /* We have to
543
544 /*
545 * Decide what sort of machine this is and ini
546 */
547 #ifdef CONFIG_KASAN
548 bl kasan_early_init
549 #endif
550 li r3,0
551 mr r4,r31
552 bl machine_init
553 bl MMU_init
554
555 /*
556 * Go back to running unmapped so we can load
557 * and change to using our exception vectors.
558 * On the 8xx, all we have to do is invalidate
559 * the old 8M byte TLB mappings and load the p
560 */
561 /* The right way to do this would be t
562 * init's THREAD like the context swit
563 * easier......until someone changes i
564 */
565 lis r4,2f@h
566 ori r4,r4,2f@l
567 tophys(r4,r4)
568 li r3,MSR_KERNEL & ~(MSR_IR|MSR_D
569 mtspr SPRN_SRR0,r4
570 mtspr SPRN_SRR1,r3
571 rfi
572 /* Load up the kernel context */
573 2:
574 #ifdef CONFIG_PIN_TLB_IMMR
575 lis r0, MD_TWAM@h
576 oris r0, r0, 0x1f00
577 mtspr SPRN_MD_CTR, r0
578 LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE
579 tlbie r0
580 mtspr SPRN_MD_EPN, r0
581 LOAD_REG_IMMEDIATE(r0, MD_SVALID | MD_
582 mtspr SPRN_MD_TWC, r0
583 mfspr r0, SPRN_IMMR
584 rlwinm r0, r0, 0, 0xfff80000
585 ori r0, r0, 0xf0 | _PAGE_DIRTY | _
586 _PAGE_NO_CACHE | _PAGE
587 mtspr SPRN_MD_RPN, r0
588 lis r0, (MD_TWAM | MD_RSV4I)@h
589 mtspr SPRN_MD_CTR, r0
590 #endif
591 #ifndef CONFIG_PIN_TLB_TEXT
592 li r0, 0
593 mtspr SPRN_MI_CTR, r0
594 #endif
595 #if !defined(CONFIG_PIN_TLB_DATA) && !defined(
596 lis r0, MD_TWAM@h
597 mtspr SPRN_MD_CTR, r0
598 #endif
599 tlbia /* Clear all T
600 sync /* wait for tl
601
602 /* set up the PTE pointers for the Aba
603 */
604 lis r5, abatron_pteptrs@h
605 ori r5, r5, abatron_pteptrs@l
606 stw r5, 0xf0(0) /* Must match
607 tophys(r5,r5)
608 lis r6, swapper_pg_dir@h
609 ori r6, r6, swapper_pg_dir@l
610 stw r6, 0(r5)
611
612 /* Now turn on the MMU for real! */
613 li r4,MSR_KERNEL
614 lis r3,start_kernel@h
615 ori r3,r3,start_kernel@l
616 mtspr SPRN_SRR0,r3
617 mtspr SPRN_SRR1,r4
618 rfi /* enable MMU
619
620 /* Set up the initial MMU state so we can do t
621 * kernel initialization. This maps the first
622 * virtual to physical. Also, set the cache m
623 * by TLB entries and perform any additional m
624 * If configured to pin some TLBs, we pin the
625 * 24 Mbytes of data, and the 512k IMMR space.
626 * these mappings is mapped by page tables.
627 */
628 SYM_FUNC_START_LOCAL(initial_mmu)
629 li r8, 0
630 mtspr SPRN_MI_CTR, r8 /* rem
631 lis r10, MD_TWAM@h
632 mtspr SPRN_MD_CTR, r10 /* rem
633
634 tlbia /* Invalidate
635
636 lis r8, MI_APG_INIT@h /* Set
637 ori r8, r8, MI_APG_INIT@l
638 mtspr SPRN_MI_AP, r8
639 lis r8, MD_APG_INIT@h
640 ori r8, r8, MD_APG_INIT@l
641 mtspr SPRN_MD_AP, r8
642
643 /* Map the lower RAM (up to 32 Mbytes)
644 lis r8, MI_RSV4I@h
645 ori r8, r8, 0x1c00
646 oris r12, r10, MD_RSV4I@h
647 ori r12, r12, 0x1c00
648 li r9, 4
649 mtctr r9
650 lis r9, KERNELBASE@h
651 li r10, MI_PS8MEG | _PMD_ACCESSED
652 li r11, MI_BOOTINIT
653 1:
654 mtspr SPRN_MI_CTR, r8 /* Set instruc
655 addi r8, r8, 0x100
656 ori r0, r9, MI_EVALID
657 mtspr SPRN_MI_EPN, r0
658 mtspr SPRN_MI_TWC, r10
659 mtspr SPRN_MI_RPN, r11
660 mtspr SPRN_MD_CTR, r12
661 addi r12, r12, 0x100
662 mtspr SPRN_MD_EPN, r0
663 mtspr SPRN_MD_TWC, r10
664 mtspr SPRN_MD_RPN, r11
665 addis r9, r9, 0x80
666 addis r11, r11, 0x80
667
668 bdnz 1b
669
670 /* Since the cache is enabled accordin
671 * just loaded into the TLB, invalidat
672 * We should probably check/set other
673 */
674 lis r8, IDC_INVALL@h
675 mtspr SPRN_IC_CST, r8
676 mtspr SPRN_DC_CST, r8
677 lis r8, IDC_ENABLE@h
678 mtspr SPRN_IC_CST, r8
679 mtspr SPRN_DC_CST, r8
680 /* Disable debug mode entry on breakpo
681 mfspr r8, SPRN_DER
682 #ifdef CONFIG_PERF_EVENTS
683 rlwinm r8, r8, 0, ~0xc
684 #else
685 rlwinm r8, r8, 0, ~0x8
686 #endif
687 mtspr SPRN_DER, r8
688 blr
689 SYM_FUNC_END(initial_mmu)
690
691 #ifdef CONFIG_PIN_TLB
692 _GLOBAL(mmu_pin_tlb)
693 lis r9, (1f - PAGE_OFFSET)@h
694 ori r9, r9, (1f - PAGE_OFFSET)@l
695 mfmsr r10
696 mflr r11
697 li r12, MSR_KERNEL & ~(MSR_IR | M
698 rlwinm r0, r10, 0, ~MSR_RI
699 rlwinm r0, r0, 0, ~MSR_EE
700 mtmsr r0
701 isync
702 .align 4
703 mtspr SPRN_SRR0, r9
704 mtspr SPRN_SRR1, r12
705 rfi
706 1:
707 li r5, 0
708 lis r6, MD_TWAM@h
709 mtspr SPRN_MI_CTR, r5
710 mtspr SPRN_MD_CTR, r6
711 tlbia
712
713 #ifdef CONFIG_PIN_TLB_TEXT
714 LOAD_REG_IMMEDIATE(r5, 28 << 8)
715 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET)
716 LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_
717 LOAD_REG_IMMEDIATE(r8, 0xf0 | _PAGE_RO
718 LOAD_REG_ADDR(r9, _sinittext)
719 li r0, 4
720 mtctr r0
721
722 2: ori r0, r6, MI_EVALID
723 mtspr SPRN_MI_CTR, r5
724 mtspr SPRN_MI_EPN, r0
725 mtspr SPRN_MI_TWC, r7
726 mtspr SPRN_MI_RPN, r8
727 addi r5, r5, 0x100
728 addis r6, r6, SZ_8M@h
729 addis r8, r8, SZ_8M@h
730 cmplw r6, r9
731 bdnzt lt, 2b
732 lis r0, MI_RSV4I@h
733 mtspr SPRN_MI_CTR, r0
734 #endif
735
736 LOAD_REG_IMMEDIATE(r5, 28 << 8 | MD_TW
737 #ifdef CONFIG_PIN_TLB_DATA
738 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET)
739 LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_
740 li r8, 0
741 #ifdef CONFIG_PIN_TLB_IMMR
742 li r0, 3
743 #else
744 li r0, 4
745 #endif
746 mtctr r0
747 cmpwi r4, 0
748 beq 4f
749 LOAD_REG_ADDR(r9, _sinittext)
750
751 2: ori r0, r6, MD_EVALID
752 ori r12, r8, 0xf0 | _PAGE_RO | _PA
753 mtspr SPRN_MD_CTR, r5
754 mtspr SPRN_MD_EPN, r0
755 mtspr SPRN_MD_TWC, r7
756 mtspr SPRN_MD_RPN, r12
757 addi r5, r5, 0x100
758 addis r6, r6, SZ_8M@h
759 addis r8, r8, SZ_8M@h
760 cmplw r6, r9
761 bdnzt lt, 2b
762 4:
763 2: ori r0, r6, MD_EVALID
764 ori r12, r8, 0xf0 | _PAGE_DIRTY |
765 mtspr SPRN_MD_CTR, r5
766 mtspr SPRN_MD_EPN, r0
767 mtspr SPRN_MD_TWC, r7
768 mtspr SPRN_MD_RPN, r12
769 addi r5, r5, 0x100
770 addis r6, r6, SZ_8M@h
771 addis r8, r8, SZ_8M@h
772 cmplw r6, r3
773 bdnzt lt, 2b
774 #endif
775 #ifdef CONFIG_PIN_TLB_IMMR
776 LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE
777 LOAD_REG_IMMEDIATE(r7, MD_SVALID | MD_
778 mfspr r8, SPRN_IMMR
779 rlwinm r8, r8, 0, 0xfff80000
780 ori r8, r8, 0xf0 | _PAGE_DIRTY | _
781 _PAGE_NO_CACHE | _PAGE
782 mtspr SPRN_MD_CTR, r5
783 mtspr SPRN_MD_EPN, r0
784 mtspr SPRN_MD_TWC, r7
785 mtspr SPRN_MD_RPN, r8
786 #endif
787 #if defined(CONFIG_PIN_TLB_IMMR) || defined(CO
788 lis r0, (MD_RSV4I | MD_TWAM)@h
789 mtspr SPRN_MD_CTR, r0
790 #endif
791 mtspr SPRN_SRR1, r10
792 mtspr SPRN_SRR0, r11
793 rfi
794 #endif
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