1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * User-space Probes (UProbes) for powerpc !! 2 * User-space Probes (UProbes) for sparc
4 * 3 *
5 * Copyright IBM Corporation, 2007-2012 !! 4 * Copyright (C) 2013 Oracle Inc.
6 * 5 *
7 * Adapted from the x86 port by Ananth N Mavin !! 6 * This program is free software: you can redistribute it and/or modify
>> 7 * it under the terms of the GNU General Public License as published by
>> 8 * the Free Software Foundation, either version 2 of the License, or
>> 9 * (at your option) any later version.
>> 10 *
>> 11 * This program is distributed in the hope that it will be useful,
>> 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 14 * GNU General Public License for more details.
>> 15 *
>> 16 * You should have received a copy of the GNU General Public License
>> 17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
>> 18 *
>> 19 * Authors:
>> 20 * Jose E. Marchesi <jose.marchesi@oracle.com>
>> 21 * Eric Saint Etienne <eric.saint.etienne@oracle.com>
8 */ 22 */
>> 23
9 #include <linux/kernel.h> 24 #include <linux/kernel.h>
10 #include <linux/sched.h> !! 25 #include <linux/highmem.h>
11 #include <linux/ptrace.h> <<
12 #include <linux/uprobes.h> 26 #include <linux/uprobes.h>
13 #include <linux/uaccess.h> 27 #include <linux/uaccess.h>
>> 28 #include <linux/sched.h> /* For struct task_struct */
14 #include <linux/kdebug.h> 29 #include <linux/kdebug.h>
15 30
16 #include <asm/sstep.h> !! 31 #include <asm/cacheflush.h>
17 #include <asm/inst.h> !! 32 #include <linux/uaccess.h>
18 <<
19 #define UPROBE_TRAP_NR UINT_MAX <<
20 33
21 /** !! 34 /* Compute the address of the breakpoint instruction and return it.
22 * is_trap_insn - check if the instruction is !! 35 *
23 * @insn: instruction to be checked. !! 36 * Note that uprobe_get_swbp_addr is defined as a weak symbol in
24 * Returns true if @insn is a trap variant. !! 37 * kernel/events/uprobe.c.
25 */ 38 */
26 bool is_trap_insn(uprobe_opcode_t *insn) !! 39 unsigned long uprobe_get_swbp_addr(struct pt_regs *regs)
>> 40 {
>> 41 return instruction_pointer(regs);
>> 42 }
>> 43
>> 44 static void copy_to_page(struct page *page, unsigned long vaddr,
>> 45 const void *src, int len)
27 { 46 {
28 return (is_trap(*insn)); !! 47 void *kaddr = kmap_atomic(page);
>> 48
>> 49 memcpy(kaddr + (vaddr & ~PAGE_MASK), src, len);
>> 50 kunmap_atomic(kaddr);
29 } 51 }
30 52
31 /** !! 53 /* Fill in the xol area with the probed instruction followed by the
32 * arch_uprobe_analyze_insn !! 54 * single-step trap. Some fixups in the copied instruction are
33 * @mm: the probed address space. !! 55 * performed at this point.
34 * @arch_uprobe: the probepoint information. !! 56 *
35 * @addr: vaddr to probe. !! 57 * Note that uprobe_xol_copy is defined as a weak symbol in
36 * Return 0 on success or a -ve number on erro !! 58 * kernel/events/uprobe.c.
37 */ 59 */
38 int arch_uprobe_analyze_insn(struct arch_uprob !! 60 void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
39 struct mm_struct *mm, unsigned !! 61 void *src, unsigned long len)
40 { 62 {
41 if (addr & 0x03) !! 63 const u32 stp_insn = UPROBE_STP_INSN;
42 return -EINVAL; !! 64 u32 insn = *(u32 *) src;
43 65
44 if (cpu_has_feature(CPU_FTR_ARCH_31) & !! 66 /* Branches annulling their delay slot must be fixed to not do
45 ppc_inst_prefixed(ppc_inst_read(au !! 67 * so. Clearing the annul bit on these instructions we can be
46 (addr & 0x3f) == 60) { !! 68 * sure the single-step breakpoint in the XOL slot will be
47 pr_info_ratelimited("Cannot re !! 69 * executed.
48 return -EINVAL; !! 70 */
49 } !! 71
>> 72 u32 op = (insn >> 30) & 0x3;
>> 73 u32 op2 = (insn >> 22) & 0x7;
>> 74
>> 75 if (op == 0 &&
>> 76 (op2 == 1 || op2 == 2 || op2 == 3 || op2 == 5 || op2 == 6) &&
>> 77 (insn & ANNUL_BIT) == ANNUL_BIT)
>> 78 insn &= ~ANNUL_BIT;
>> 79
>> 80 copy_to_page(page, vaddr, &insn, len);
>> 81 copy_to_page(page, vaddr+len, &stp_insn, 4);
>> 82 }
50 83
51 if (!can_single_step(ppc_inst_val(ppc_ <<
52 pr_info_ratelimited("Cannot re <<
53 return -ENOTSUPP; <<
54 } <<
55 84
>> 85 /* Instruction analysis/validity.
>> 86 *
>> 87 * This function returns 0 on success or a -ve number on error.
>> 88 */
>> 89 int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe,
>> 90 struct mm_struct *mm, unsigned long addr)
>> 91 {
>> 92 /* Any unsupported instruction? Then return -EINVAL */
56 return 0; 93 return 0;
57 } 94 }
58 95
59 /* !! 96 /* If INSN is a relative control transfer instruction, return the
60 * arch_uprobe_pre_xol - prepare to execute ou !! 97 * corrected branch destination value.
61 * @auprobe: the probepoint information. !! 98 *
62 * @regs: reflects the saved user state of cur !! 99 * Note that regs->tpc and regs->tnpc still hold the values of the
>> 100 * program counters at the time of the single-step trap due to the
>> 101 * execution of the UPROBE_STP_INSN at utask->xol_vaddr + 4.
>> 102 *
63 */ 103 */
64 int arch_uprobe_pre_xol(struct arch_uprobe *au !! 104 static unsigned long relbranch_fixup(u32 insn, struct uprobe_task *utask,
>> 105 struct pt_regs *regs)
65 { 106 {
66 struct arch_uprobe_task *autask = &cur !! 107 /* Branch not taken, no mods necessary. */
>> 108 if (regs->tnpc == regs->tpc + 0x4UL)
>> 109 return utask->autask.saved_tnpc + 0x4UL;
67 110
68 autask->saved_trap_nr = current->threa !! 111 /* The three cases are call, branch w/prediction,
69 current->thread.trap_nr = UPROBE_TRAP_ !! 112 * and traditional branch.
70 regs_set_return_ip(regs, current->utas !! 113 */
>> 114 if ((insn & 0xc0000000) == 0x40000000 ||
>> 115 (insn & 0xc1c00000) == 0x00400000 ||
>> 116 (insn & 0xc1c00000) == 0x00800000) {
>> 117 unsigned long real_pc = (unsigned long) utask->vaddr;
>> 118 unsigned long ixol_addr = utask->xol_vaddr;
>> 119
>> 120 /* The instruction did all the work for us
>> 121 * already, just apply the offset to the correct
>> 122 * instruction location.
>> 123 */
>> 124 return (real_pc + (regs->tnpc - ixol_addr));
>> 125 }
71 126
72 user_enable_single_step(current); !! 127 /* It is jmpl or some other absolute PC modification instruction,
73 return 0; !! 128 * leave NPC as-is.
>> 129 */
>> 130 return regs->tnpc;
74 } 131 }
75 132
76 /** !! 133 /* If INSN is an instruction which writes its PC location
77 * uprobe_get_swbp_addr - compute address of s !! 134 * into a destination register, fix that up.
78 * @regs: Reflects the saved state of the task <<
79 * instruction. <<
80 * Return the address of the breakpoint instru <<
81 */ 135 */
82 unsigned long uprobe_get_swbp_addr(struct pt_r !! 136 static int retpc_fixup(struct pt_regs *regs, u32 insn,
>> 137 unsigned long real_pc)
83 { 138 {
84 return instruction_pointer(regs); !! 139 unsigned long *slot = NULL;
>> 140 int rc = 0;
>> 141
>> 142 /* Simplest case is 'call', which always uses %o7 */
>> 143 if ((insn & 0xc0000000) == 0x40000000)
>> 144 slot = ®s->u_regs[UREG_I7];
>> 145
>> 146 /* 'jmpl' encodes the register inside of the opcode */
>> 147 if ((insn & 0xc1f80000) == 0x81c00000) {
>> 148 unsigned long rd = ((insn >> 25) & 0x1f);
>> 149
>> 150 if (rd <= 15) {
>> 151 slot = ®s->u_regs[rd];
>> 152 } else {
>> 153 unsigned long fp = regs->u_regs[UREG_FP];
>> 154 /* Hard case, it goes onto the stack. */
>> 155 flushw_all();
>> 156
>> 157 rd -= 16;
>> 158 if (test_thread_64bit_stack(fp)) {
>> 159 unsigned long __user *uslot =
>> 160 (unsigned long __user *) (fp + STACK_BIAS) + rd;
>> 161 rc = __put_user(real_pc, uslot);
>> 162 } else {
>> 163 unsigned int __user *uslot = (unsigned int
>> 164 __user *) fp + rd;
>> 165 rc = __put_user((u32) real_pc, uslot);
>> 166 }
>> 167 }
>> 168 }
>> 169 if (slot != NULL)
>> 170 *slot = real_pc;
>> 171 return rc;
85 } 172 }
86 173
87 /* !! 174 /* Single-stepping can be avoided for certain instructions: NOPs and
88 * If xol insn itself traps and generates a si !! 175 * instructions that can be emulated. This function determines
89 * then detect the case where a singlestepped !! 176 * whether the instruction where the uprobe is installed falls in one
90 * own address. It is assumed that anything li !! 177 * of these cases and emulates it.
91 * sets thread.trap_nr != UINT_MAX. !! 178 *
92 * !! 179 * This function returns true if the single-stepping can be skipped,
93 * arch_uprobe_pre_xol/arch_uprobe_post_xol sa !! 180 * false otherwise.
94 * arch_uprobe_xol_was_trapped() simply checks <<
95 * UPROBE_TRAP_NR == UINT_MAX set by arch_upro <<
96 */ 181 */
97 bool arch_uprobe_xol_was_trapped(struct task_s !! 182 bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
98 { 183 {
99 if (t->thread.trap_nr != UPROBE_TRAP_N !! 184 /* We currently only emulate NOP instructions.
>> 185 */
>> 186
>> 187 if (auprobe->ixol == (1 << 24)) {
>> 188 regs->tnpc += 4;
>> 189 regs->tpc += 4;
100 return true; 190 return true;
>> 191 }
101 192
102 return false; 193 return false;
103 } 194 }
104 195
105 /* !! 196 /* Prepare to execute out of line. At this point
106 * Called after single-stepping. To avoid the !! 197 * current->utask->xol_vaddr points to an allocated XOL slot properly
107 * occur when we temporarily put back the orig !! 198 * initialized with the original instruction and the single-stepping
108 * single-step, we single-stepped a copy of th !! 199 * trap instruction.
109 * 200 *
110 * This function prepares to resume execution !! 201 * This function returns 0 on success, any other number on error.
111 */ 202 */
112 int arch_uprobe_post_xol(struct arch_uprobe *a !! 203 int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
113 { 204 {
114 struct uprobe_task *utask = current->u 205 struct uprobe_task *utask = current->utask;
>> 206 struct arch_uprobe_task *autask = ¤t->utask->autask;
115 207
116 WARN_ON_ONCE(current->thread.trap_nr ! !! 208 /* Save the current program counters so they can be restored
117 !! 209 * later.
118 current->thread.trap_nr = utask->autas !! 210 */
>> 211 autask->saved_tpc = regs->tpc;
>> 212 autask->saved_tnpc = regs->tnpc;
119 213
120 /* !! 214 /* Adjust PC and NPC so the first instruction in the XOL slot
121 * On powerpc, except for loads and st !! 215 * will be executed by the user task.
122 * including ones that alter code flow <<
123 * are emulated in the kernel. We get <<
124 * support doesn't exist and have to f <<
125 * to be executed. <<
126 */ 216 */
127 regs_set_return_ip(regs, (unsigned lon !! 217 instruction_pointer_set(regs, utask->xol_vaddr);
128 218
129 user_disable_single_step(current); <<
130 return 0; 219 return 0;
131 } 220 }
132 221
133 /* callback routine for handling exceptions. * !! 222 /* Prepare to resume execution after the single-step. Called after
134 int arch_uprobe_exception_notify(struct notifi !! 223 * single-stepping. To avoid the SMP problems that can occur when we
135 unsigned long !! 224 * temporarily put back the original opcode to single-step, we
>> 225 * single-stepped a copy of the instruction.
>> 226 *
>> 227 * This function returns 0 on success, any other number on error.
>> 228 */
>> 229 int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
136 { 230 {
137 struct die_args *args = data; !! 231 struct uprobe_task *utask = current->utask;
138 struct pt_regs *regs = args->regs; !! 232 struct arch_uprobe_task *autask = &utask->autask;
>> 233 u32 insn = auprobe->ixol;
>> 234 int rc = 0;
>> 235
>> 236 if (utask->state == UTASK_SSTEP_ACK) {
>> 237 regs->tnpc = relbranch_fixup(insn, utask, regs);
>> 238 regs->tpc = autask->saved_tnpc;
>> 239 rc = retpc_fixup(regs, insn, (unsigned long) utask->vaddr);
>> 240 } else {
>> 241 regs->tnpc = utask->vaddr+4;
>> 242 regs->tpc = autask->saved_tnpc+4;
>> 243 }
>> 244 return rc;
>> 245 }
139 246
140 /* regs == NULL is a kernel bug */ !! 247 /* Handler for uprobe traps. This is called from the traps table and
141 if (WARN_ON(!regs)) !! 248 * triggers the proper die notification.
142 return NOTIFY_DONE; !! 249 */
>> 250 asmlinkage void uprobe_trap(struct pt_regs *regs,
>> 251 unsigned long trap_level)
>> 252 {
>> 253 BUG_ON(trap_level != 0x173 && trap_level != 0x174);
>> 254
>> 255 /* We are only interested in user-mode code. Uprobe traps
>> 256 * shall not be present in kernel code.
>> 257 */
>> 258 if (!user_mode(regs)) {
>> 259 local_irq_enable();
>> 260 bad_trap(regs, trap_level);
>> 261 return;
>> 262 }
>> 263
>> 264 /* trap_level == 0x173 --> ta 0x73
>> 265 * trap_level == 0x174 --> ta 0x74
>> 266 */
>> 267 if (notify_die((trap_level == 0x173) ? DIE_BPT : DIE_SSTEP,
>> 268 (trap_level == 0x173) ? "bpt" : "sstep",
>> 269 regs, 0, trap_level, SIGTRAP) != NOTIFY_STOP)
>> 270 bad_trap(regs, trap_level);
>> 271 }
>> 272
>> 273 /* Callback routine for handling die notifications.
>> 274 */
>> 275 int arch_uprobe_exception_notify(struct notifier_block *self,
>> 276 unsigned long val, void *data)
>> 277 {
>> 278 int ret = NOTIFY_DONE;
>> 279 struct die_args *args = (struct die_args *)data;
143 280
144 /* We are only interested in userspace 281 /* We are only interested in userspace traps */
145 if (!user_mode(regs)) !! 282 if (args->regs && !user_mode(args->regs))
146 return NOTIFY_DONE; 283 return NOTIFY_DONE;
147 284
148 switch (val) { 285 switch (val) {
149 case DIE_BPT: 286 case DIE_BPT:
150 if (uprobe_pre_sstep_notifier( !! 287 if (uprobe_pre_sstep_notifier(args->regs))
151 return NOTIFY_STOP; !! 288 ret = NOTIFY_STOP;
152 break; 289 break;
>> 290
153 case DIE_SSTEP: 291 case DIE_SSTEP:
154 if (uprobe_post_sstep_notifier !! 292 if (uprobe_post_sstep_notifier(args->regs))
155 return NOTIFY_STOP; !! 293 ret = NOTIFY_STOP;
156 break; !! 294
157 default: 295 default:
158 break; 296 break;
159 } 297 }
160 return NOTIFY_DONE; !! 298
>> 299 return ret;
161 } 300 }
162 301
163 /* !! 302 /* This function gets called when a XOL instruction either gets
164 * This function gets called when XOL instruct !! 303 * trapped or the thread has a fatal signal, so reset the instruction
165 * the thread has a fatal signal, so reset the !! 304 * pointer to its probed address.
166 * probed address. <<
167 */ 305 */
168 void arch_uprobe_abort_xol(struct arch_uprobe 306 void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
169 { 307 {
170 struct uprobe_task *utask = current->u 308 struct uprobe_task *utask = current->utask;
171 309
172 current->thread.trap_nr = utask->autas <<
173 instruction_pointer_set(regs, utask->v 310 instruction_pointer_set(regs, utask->vaddr);
174 <<
175 user_disable_single_step(current); <<
176 } 311 }
177 312
178 /* !! 313 /* If xol insn itself traps and generates a signal(Say,
179 * See if the instruction can be emulated. !! 314 * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped
180 * Returns true if instruction was emulated, f !! 315 * instruction jumps back to its own address.
181 */ 316 */
182 bool arch_uprobe_skip_sstep(struct arch_uprobe !! 317 bool arch_uprobe_xol_was_trapped(struct task_struct *t)
183 { 318 {
184 int ret; <<
185 <<
186 /* <<
187 * emulate_step() returns 1 if the ins <<
188 * For all other cases, we need to sin <<
189 */ <<
190 ret = emulate_step(regs, ppc_inst_read <<
191 if (ret > 0) <<
192 return true; <<
193 <<
194 return false; 319 return false;
195 } 320 }
196 321
197 unsigned long 322 unsigned long
198 arch_uretprobe_hijack_return_addr(unsigned lon !! 323 arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr,
>> 324 struct pt_regs *regs)
199 { 325 {
200 unsigned long orig_ret_vaddr; !! 326 unsigned long orig_ret_vaddr = regs->u_regs[UREG_I7];
201 <<
202 orig_ret_vaddr = regs->link; <<
203 327
204 /* Replace the return addr with trampo !! 328 regs->u_regs[UREG_I7] = trampoline_vaddr-8;
205 regs->link = trampoline_vaddr; <<
206 329
207 return orig_ret_vaddr; !! 330 return orig_ret_vaddr + 8;
208 } <<
209 <<
210 bool arch_uretprobe_is_alive(struct return_ins <<
211 struct pt_regs <<
212 { <<
213 if (ctx == RP_CHECK_CHAIN_CALL) <<
214 return regs->gpr[1] <= ret->st <<
215 else <<
216 return regs->gpr[1] < ret->sta <<
217 } 331 }
218 332
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