1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * User-space Probes (UProbes) for powerpc !! 3 * User-space Probes (UProbes) for sparc
4 * 4 *
5 * Copyright IBM Corporation, 2007-2012 !! 5 * Copyright (C) 2013 Oracle Inc.
6 * 6 *
7 * Adapted from the x86 port by Ananth N Mavin !! 7 * Authors:
>> 8 * Jose E. Marchesi <jose.marchesi@oracle.com>
>> 9 * Eric Saint Etienne <eric.saint.etienne@oracle.com>
8 */ 10 */
>> 11
9 #include <linux/kernel.h> 12 #include <linux/kernel.h>
10 #include <linux/sched.h> !! 13 #include <linux/highmem.h>
11 #include <linux/ptrace.h> <<
12 #include <linux/uprobes.h> 14 #include <linux/uprobes.h>
13 #include <linux/uaccess.h> 15 #include <linux/uaccess.h>
>> 16 #include <linux/sched.h> /* For struct task_struct */
14 #include <linux/kdebug.h> 17 #include <linux/kdebug.h>
15 18
16 #include <asm/sstep.h> !! 19 #include <asm/cacheflush.h>
17 #include <asm/inst.h> <<
18 20
19 #define UPROBE_TRAP_NR UINT_MAX !! 21 #include "kernel.h"
20 22
21 /** !! 23 /* Compute the address of the breakpoint instruction and return it.
22 * is_trap_insn - check if the instruction is !! 24 *
23 * @insn: instruction to be checked. !! 25 * Note that uprobe_get_swbp_addr is defined as a weak symbol in
24 * Returns true if @insn is a trap variant. !! 26 * kernel/events/uprobe.c.
25 */ 27 */
26 bool is_trap_insn(uprobe_opcode_t *insn) !! 28 unsigned long uprobe_get_swbp_addr(struct pt_regs *regs)
>> 29 {
>> 30 return instruction_pointer(regs);
>> 31 }
>> 32
>> 33 static void copy_to_page(struct page *page, unsigned long vaddr,
>> 34 const void *src, int len)
27 { 35 {
28 return (is_trap(*insn)); !! 36 void *kaddr = kmap_atomic(page);
>> 37
>> 38 memcpy(kaddr + (vaddr & ~PAGE_MASK), src, len);
>> 39 kunmap_atomic(kaddr);
29 } 40 }
30 41
31 /** !! 42 /* Fill in the xol area with the probed instruction followed by the
32 * arch_uprobe_analyze_insn !! 43 * single-step trap. Some fixups in the copied instruction are
33 * @mm: the probed address space. !! 44 * performed at this point.
34 * @arch_uprobe: the probepoint information. !! 45 *
35 * @addr: vaddr to probe. !! 46 * Note that uprobe_xol_copy is defined as a weak symbol in
36 * Return 0 on success or a -ve number on erro !! 47 * kernel/events/uprobe.c.
37 */ 48 */
38 int arch_uprobe_analyze_insn(struct arch_uprob !! 49 void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
39 struct mm_struct *mm, unsigned !! 50 void *src, unsigned long len)
40 { 51 {
41 if (addr & 0x03) !! 52 const u32 stp_insn = UPROBE_STP_INSN;
42 return -EINVAL; !! 53 u32 insn = *(u32 *) src;
43 54
44 if (cpu_has_feature(CPU_FTR_ARCH_31) & !! 55 /* Branches annulling their delay slot must be fixed to not do
45 ppc_inst_prefixed(ppc_inst_read(au !! 56 * so. Clearing the annul bit on these instructions we can be
46 (addr & 0x3f) == 60) { !! 57 * sure the single-step breakpoint in the XOL slot will be
47 pr_info_ratelimited("Cannot re !! 58 * executed.
48 return -EINVAL; !! 59 */
49 } !! 60
>> 61 u32 op = (insn >> 30) & 0x3;
>> 62 u32 op2 = (insn >> 22) & 0x7;
>> 63
>> 64 if (op == 0 &&
>> 65 (op2 == 1 || op2 == 2 || op2 == 3 || op2 == 5 || op2 == 6) &&
>> 66 (insn & ANNUL_BIT) == ANNUL_BIT)
>> 67 insn &= ~ANNUL_BIT;
>> 68
>> 69 copy_to_page(page, vaddr, &insn, len);
>> 70 copy_to_page(page, vaddr+len, &stp_insn, 4);
>> 71 }
50 72
51 if (!can_single_step(ppc_inst_val(ppc_ <<
52 pr_info_ratelimited("Cannot re <<
53 return -ENOTSUPP; <<
54 } <<
55 73
>> 74 /* Instruction analysis/validity.
>> 75 *
>> 76 * This function returns 0 on success or a -ve number on error.
>> 77 */
>> 78 int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe,
>> 79 struct mm_struct *mm, unsigned long addr)
>> 80 {
>> 81 /* Any unsupported instruction? Then return -EINVAL */
56 return 0; 82 return 0;
57 } 83 }
58 84
59 /* !! 85 /* If INSN is a relative control transfer instruction, return the
60 * arch_uprobe_pre_xol - prepare to execute ou !! 86 * corrected branch destination value.
61 * @auprobe: the probepoint information. !! 87 *
62 * @regs: reflects the saved user state of cur !! 88 * Note that regs->tpc and regs->tnpc still hold the values of the
>> 89 * program counters at the time of the single-step trap due to the
>> 90 * execution of the UPROBE_STP_INSN at utask->xol_vaddr + 4.
>> 91 *
63 */ 92 */
64 int arch_uprobe_pre_xol(struct arch_uprobe *au !! 93 static unsigned long relbranch_fixup(u32 insn, struct uprobe_task *utask,
>> 94 struct pt_regs *regs)
65 { 95 {
66 struct arch_uprobe_task *autask = &cur !! 96 /* Branch not taken, no mods necessary. */
>> 97 if (regs->tnpc == regs->tpc + 0x4UL)
>> 98 return utask->autask.saved_tnpc + 0x4UL;
67 99
68 autask->saved_trap_nr = current->threa !! 100 /* The three cases are call, branch w/prediction,
69 current->thread.trap_nr = UPROBE_TRAP_ !! 101 * and traditional branch.
70 regs_set_return_ip(regs, current->utas !! 102 */
>> 103 if ((insn & 0xc0000000) == 0x40000000 ||
>> 104 (insn & 0xc1c00000) == 0x00400000 ||
>> 105 (insn & 0xc1c00000) == 0x00800000) {
>> 106 unsigned long real_pc = (unsigned long) utask->vaddr;
>> 107 unsigned long ixol_addr = utask->xol_vaddr;
>> 108
>> 109 /* The instruction did all the work for us
>> 110 * already, just apply the offset to the correct
>> 111 * instruction location.
>> 112 */
>> 113 return (real_pc + (regs->tnpc - ixol_addr));
>> 114 }
71 115
72 user_enable_single_step(current); !! 116 /* It is jmpl or some other absolute PC modification instruction,
73 return 0; !! 117 * leave NPC as-is.
>> 118 */
>> 119 return regs->tnpc;
74 } 120 }
75 121
76 /** !! 122 /* If INSN is an instruction which writes its PC location
77 * uprobe_get_swbp_addr - compute address of s !! 123 * into a destination register, fix that up.
78 * @regs: Reflects the saved state of the task <<
79 * instruction. <<
80 * Return the address of the breakpoint instru <<
81 */ 124 */
82 unsigned long uprobe_get_swbp_addr(struct pt_r !! 125 static int retpc_fixup(struct pt_regs *regs, u32 insn,
>> 126 unsigned long real_pc)
83 { 127 {
84 return instruction_pointer(regs); !! 128 unsigned long *slot = NULL;
>> 129 int rc = 0;
>> 130
>> 131 /* Simplest case is 'call', which always uses %o7 */
>> 132 if ((insn & 0xc0000000) == 0x40000000)
>> 133 slot = ®s->u_regs[UREG_I7];
>> 134
>> 135 /* 'jmpl' encodes the register inside of the opcode */
>> 136 if ((insn & 0xc1f80000) == 0x81c00000) {
>> 137 unsigned long rd = ((insn >> 25) & 0x1f);
>> 138
>> 139 if (rd <= 15) {
>> 140 slot = ®s->u_regs[rd];
>> 141 } else {
>> 142 unsigned long fp = regs->u_regs[UREG_FP];
>> 143 /* Hard case, it goes onto the stack. */
>> 144 flushw_all();
>> 145
>> 146 rd -= 16;
>> 147 if (test_thread_64bit_stack(fp)) {
>> 148 unsigned long __user *uslot =
>> 149 (unsigned long __user *) (fp + STACK_BIAS) + rd;
>> 150 rc = __put_user(real_pc, uslot);
>> 151 } else {
>> 152 unsigned int __user *uslot = (unsigned int
>> 153 __user *) fp + rd;
>> 154 rc = __put_user((u32) real_pc, uslot);
>> 155 }
>> 156 }
>> 157 }
>> 158 if (slot != NULL)
>> 159 *slot = real_pc;
>> 160 return rc;
85 } 161 }
86 162
87 /* !! 163 /* Single-stepping can be avoided for certain instructions: NOPs and
88 * If xol insn itself traps and generates a si !! 164 * instructions that can be emulated. This function determines
89 * then detect the case where a singlestepped !! 165 * whether the instruction where the uprobe is installed falls in one
90 * own address. It is assumed that anything li !! 166 * of these cases and emulates it.
91 * sets thread.trap_nr != UINT_MAX. !! 167 *
92 * !! 168 * This function returns true if the single-stepping can be skipped,
93 * arch_uprobe_pre_xol/arch_uprobe_post_xol sa !! 169 * false otherwise.
94 * arch_uprobe_xol_was_trapped() simply checks <<
95 * UPROBE_TRAP_NR == UINT_MAX set by arch_upro <<
96 */ 170 */
97 bool arch_uprobe_xol_was_trapped(struct task_s !! 171 bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
98 { 172 {
99 if (t->thread.trap_nr != UPROBE_TRAP_N !! 173 /* We currently only emulate NOP instructions.
>> 174 */
>> 175
>> 176 if (auprobe->ixol == (1 << 24)) {
>> 177 regs->tnpc += 4;
>> 178 regs->tpc += 4;
100 return true; 179 return true;
>> 180 }
101 181
102 return false; 182 return false;
103 } 183 }
104 184
105 /* !! 185 /* Prepare to execute out of line. At this point
106 * Called after single-stepping. To avoid the !! 186 * current->utask->xol_vaddr points to an allocated XOL slot properly
107 * occur when we temporarily put back the orig !! 187 * initialized with the original instruction and the single-stepping
108 * single-step, we single-stepped a copy of th !! 188 * trap instruction.
109 * 189 *
110 * This function prepares to resume execution !! 190 * This function returns 0 on success, any other number on error.
111 */ 191 */
112 int arch_uprobe_post_xol(struct arch_uprobe *a !! 192 int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
113 { 193 {
114 struct uprobe_task *utask = current->u 194 struct uprobe_task *utask = current->utask;
>> 195 struct arch_uprobe_task *autask = ¤t->utask->autask;
115 196
116 WARN_ON_ONCE(current->thread.trap_nr ! !! 197 /* Save the current program counters so they can be restored
117 !! 198 * later.
118 current->thread.trap_nr = utask->autas !! 199 */
>> 200 autask->saved_tpc = regs->tpc;
>> 201 autask->saved_tnpc = regs->tnpc;
119 202
120 /* !! 203 /* Adjust PC and NPC so the first instruction in the XOL slot
121 * On powerpc, except for loads and st !! 204 * will be executed by the user task.
122 * including ones that alter code flow <<
123 * are emulated in the kernel. We get <<
124 * support doesn't exist and have to f <<
125 * to be executed. <<
126 */ 205 */
127 regs_set_return_ip(regs, (unsigned lon !! 206 instruction_pointer_set(regs, utask->xol_vaddr);
128 207
129 user_disable_single_step(current); <<
130 return 0; 208 return 0;
131 } 209 }
132 210
133 /* callback routine for handling exceptions. * !! 211 /* Prepare to resume execution after the single-step. Called after
134 int arch_uprobe_exception_notify(struct notifi !! 212 * single-stepping. To avoid the SMP problems that can occur when we
135 unsigned long !! 213 * temporarily put back the original opcode to single-step, we
>> 214 * single-stepped a copy of the instruction.
>> 215 *
>> 216 * This function returns 0 on success, any other number on error.
>> 217 */
>> 218 int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
>> 219 {
>> 220 struct uprobe_task *utask = current->utask;
>> 221 struct arch_uprobe_task *autask = &utask->autask;
>> 222 u32 insn = auprobe->ixol;
>> 223 int rc = 0;
>> 224
>> 225 if (utask->state == UTASK_SSTEP_ACK) {
>> 226 regs->tnpc = relbranch_fixup(insn, utask, regs);
>> 227 regs->tpc = autask->saved_tnpc;
>> 228 rc = retpc_fixup(regs, insn, (unsigned long) utask->vaddr);
>> 229 } else {
>> 230 regs->tnpc = utask->vaddr+4;
>> 231 regs->tpc = autask->saved_tnpc+4;
>> 232 }
>> 233 return rc;
>> 234 }
>> 235
>> 236 /* Handler for uprobe traps. This is called from the traps table and
>> 237 * triggers the proper die notification.
>> 238 */
>> 239 asmlinkage void uprobe_trap(struct pt_regs *regs,
>> 240 unsigned long trap_level)
136 { 241 {
137 struct die_args *args = data; !! 242 BUG_ON(trap_level != 0x173 && trap_level != 0x174);
138 struct pt_regs *regs = args->regs; <<
139 243
140 /* regs == NULL is a kernel bug */ !! 244 /* We are only interested in user-mode code. Uprobe traps
141 if (WARN_ON(!regs)) !! 245 * shall not be present in kernel code.
142 return NOTIFY_DONE; !! 246 */
>> 247 if (!user_mode(regs)) {
>> 248 local_irq_enable();
>> 249 bad_trap(regs, trap_level);
>> 250 return;
>> 251 }
>> 252
>> 253 /* trap_level == 0x173 --> ta 0x73
>> 254 * trap_level == 0x174 --> ta 0x74
>> 255 */
>> 256 if (notify_die((trap_level == 0x173) ? DIE_BPT : DIE_SSTEP,
>> 257 (trap_level == 0x173) ? "bpt" : "sstep",
>> 258 regs, 0, trap_level, SIGTRAP) != NOTIFY_STOP)
>> 259 bad_trap(regs, trap_level);
>> 260 }
>> 261
>> 262 /* Callback routine for handling die notifications.
>> 263 */
>> 264 int arch_uprobe_exception_notify(struct notifier_block *self,
>> 265 unsigned long val, void *data)
>> 266 {
>> 267 int ret = NOTIFY_DONE;
>> 268 struct die_args *args = (struct die_args *)data;
143 269
144 /* We are only interested in userspace 270 /* We are only interested in userspace traps */
145 if (!user_mode(regs)) !! 271 if (args->regs && !user_mode(args->regs))
146 return NOTIFY_DONE; 272 return NOTIFY_DONE;
147 273
148 switch (val) { 274 switch (val) {
149 case DIE_BPT: 275 case DIE_BPT:
150 if (uprobe_pre_sstep_notifier( !! 276 if (uprobe_pre_sstep_notifier(args->regs))
151 return NOTIFY_STOP; !! 277 ret = NOTIFY_STOP;
152 break; 278 break;
>> 279
153 case DIE_SSTEP: 280 case DIE_SSTEP:
154 if (uprobe_post_sstep_notifier !! 281 if (uprobe_post_sstep_notifier(args->regs))
155 return NOTIFY_STOP; !! 282 ret = NOTIFY_STOP;
156 break; !! 283
157 default: 284 default:
158 break; 285 break;
159 } 286 }
160 return NOTIFY_DONE; !! 287
>> 288 return ret;
161 } 289 }
162 290
163 /* !! 291 /* This function gets called when a XOL instruction either gets
164 * This function gets called when XOL instruct !! 292 * trapped or the thread has a fatal signal, so reset the instruction
165 * the thread has a fatal signal, so reset the !! 293 * pointer to its probed address.
166 * probed address. <<
167 */ 294 */
168 void arch_uprobe_abort_xol(struct arch_uprobe 295 void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
169 { 296 {
170 struct uprobe_task *utask = current->u 297 struct uprobe_task *utask = current->utask;
171 298
172 current->thread.trap_nr = utask->autas <<
173 instruction_pointer_set(regs, utask->v 299 instruction_pointer_set(regs, utask->vaddr);
174 <<
175 user_disable_single_step(current); <<
176 } 300 }
177 301
178 /* !! 302 /* If xol insn itself traps and generates a signal(Say,
179 * See if the instruction can be emulated. !! 303 * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped
180 * Returns true if instruction was emulated, f !! 304 * instruction jumps back to its own address.
181 */ 305 */
182 bool arch_uprobe_skip_sstep(struct arch_uprobe !! 306 bool arch_uprobe_xol_was_trapped(struct task_struct *t)
183 { 307 {
184 int ret; <<
185 <<
186 /* <<
187 * emulate_step() returns 1 if the ins <<
188 * For all other cases, we need to sin <<
189 */ <<
190 ret = emulate_step(regs, ppc_inst_read <<
191 if (ret > 0) <<
192 return true; <<
193 <<
194 return false; 308 return false;
195 } 309 }
196 310
197 unsigned long 311 unsigned long
198 arch_uretprobe_hijack_return_addr(unsigned lon !! 312 arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr,
>> 313 struct pt_regs *regs)
199 { 314 {
200 unsigned long orig_ret_vaddr; !! 315 unsigned long orig_ret_vaddr = regs->u_regs[UREG_I7];
201 316
202 orig_ret_vaddr = regs->link; !! 317 regs->u_regs[UREG_I7] = trampoline_vaddr-8;
203 318
204 /* Replace the return addr with trampo !! 319 return orig_ret_vaddr + 8;
205 regs->link = trampoline_vaddr; <<
206 <<
207 return orig_ret_vaddr; <<
208 } <<
209 <<
210 bool arch_uretprobe_is_alive(struct return_ins <<
211 struct pt_regs <<
212 { <<
213 if (ctx == RP_CHECK_CHAIN_CALL) <<
214 return regs->gpr[1] <= ret->st <<
215 else <<
216 return regs->gpr[1] < ret->sta <<
217 } 320 }
218 321
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