1 # SPDX-License-Identifier: GPL-2.0
2 config CPM1
3 bool
4 select CPM
5
6 choice
7 prompt "8xx Machine Type"
8 depends on PPC_8xx
9 default MPC885ADS
10
11 config MPC8XXFADS
12 bool "FADS"
13
14 config MPC86XADS
15 bool "MPC86XADS"
16 select CPM1
17 help
18 MPC86x Application Development Syste
19 The MPC86xADS is meant to serve as a
20 development around the MPC86X proces
21
22 config MPC885ADS
23 bool "MPC885ADS"
24 select CPM1
25 select OF_DYNAMIC
26 help
27 Freescale Semiconductor MPC885 Appli
28 Also known as DUET.
29 The MPC885ADS is meant to serve as a
30 development around the MPC885 proces
31
32 config PPC_EP88XC
33 bool "Embedded Planet EP88xC (a.k.a. C
34 select CPM1
35 help
36 This enables support for the Embedde
37
38 This board is also resold by Freesca
39 MPC885 Evaluation System and/or the
40
41 config PPC_ADDER875
42 bool "Analogue & Micro Adder 875"
43 select CPM1
44 help
45 This enables support for the Analogu
46 board.
47
48 config TQM8XX
49 bool "TQM8XX"
50 select CPM1
51 help
52 support for the mpc8xx based boards
53
54 endchoice
55
56 menu "Freescale Ethernet driver platform-speci
57 depends on (FS_ENET && MPC885ADS)
58
59 config MPC8xx_SECOND_ETH
60 bool "Second Ethernet channel"
61 depends on MPC885ADS
62 default y
63 help
64 This enables support for second Ethe
65 The latter will use SCC1, for 885ADS
66
67 choice
68 prompt "Second Ethernet channe
69 depends on MPC8xx_SECOND_ETH
70 default MPC8xx_SECOND_ETH_FEC2
71
72 config MPC8xx_SECOND_ETH_FEC2
73 bool "FEC2"
74 depends on MPC885ADS
75 help
76 Enable FEC2 to serve as 2-nd
77 (often 2-nd UART) will not w
78
79 config MPC8xx_SECOND_ETH_SCC3
80 bool "SCC3"
81 depends on MPC885ADS
82 help
83 Enable SCC3 to serve as 2-nd
84 (often 1-nd UART) will not w
85
86 endchoice
87
88 endmenu
89
90 #
91 # MPC8xx Communication options
92 #
93
94 menu "MPC8xx CPM Options"
95 depends on PPC_8xx
96
97 # This doesn't really belong here, but it is c
98 # 8xx specific questions.
99 comment "Generic MPC8xx Options"
100
101 config 8xx_GPIO
102 bool "GPIO API Support"
103 select GPIOLIB
104 select OF_GPIO_MM_GPIOCHIP
105 help
106 Saying Y here will cause the ports o
107 with the GPIO API. If you say N her
108
109 If in doubt, say Y here.
110
111 config 8xx_CPU15
112 bool "CPU15 Silicon Errata"
113 depends on !HUGETLB_PAGE
114 default y
115 help
116 This enables a workaround for erratu
117 This bug can cause incorrect code ex
118 circumstances. This workaround adds
119 every time execution crosses a page
120 to disable it if you have worked aro
121 (by not placing conditional branches
122 in the last word of a page, with a t
123 line in the next page), or if you ha
124 workaround.
125
126 If in doubt, say Y here.
127
128 choice
129 prompt "Microcode patch selection"
130 default NO_UCODE_PATCH
131 help
132 Help not implemented yet, coming soo
133
134 config NO_UCODE_PATCH
135 bool "None"
136
137 config USB_SOF_UCODE_PATCH
138 bool "USB SOF patch"
139 help
140 Help not implemented yet, coming soo
141
142 config I2C_SPI_UCODE_PATCH
143 bool "I2C/SPI relocation patch"
144 help
145 Help not implemented yet, coming soo
146
147 config I2C_SPI_SMC1_UCODE_PATCH
148 bool "I2C/SPI/SMC1 relocation patch"
149 help
150 Help not implemented yet, coming soo
151
152 config SMC_UCODE_PATCH
153 bool "SMC relocation patch"
154 help
155 This microcode relocates SMC1 and SM
156 offset 0x1ec0 and 0x1fc0 to allow ex
157 for SCC3 and SCC4.
158
159 endchoice
160
161 config UCODE_PATCH
162 bool
163 default y
164 depends on !NO_UCODE_PATCH
165
166 menu "8xx advanced setup"
167 depends on PPC_8xx
168
169 config PIN_TLB
170 bool "Pinned Kernel TLBs"
171 depends on ADVANCED_OPTIONS
172 help
173 On the 8xx, we have 32 instruction T
174 table 4 TLBs can be pinned.
175
176 It reduces the amount of usable TLBs
177 reason why we make it selectable.
178
179 This option does nothing, it just ac
180 to pin.
181
182 config PIN_TLB_DATA
183 bool "Pinned TLB for DATA"
184 depends on PIN_TLB
185 default y
186 help
187 This pins the first 32 Mbytes of mem
188
189 config PIN_TLB_IMMR
190 bool "Pinned TLB for IMMR"
191 depends on PIN_TLB
192 default y
193 help
194 This pins the IMMR area with a 512kb
195 CONFIG_PIN_TLB_DATA is also selected
196 CONFIG_PIN_TLB_DATA to 24 Mbytes.
197
198 config PIN_TLB_TEXT
199 bool "Pinned TLB for TEXT"
200 depends on PIN_TLB
201 default y
202 help
203 This pins kernel text with 8M pages.
204
205 endmenu
206
207 endmenu
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