1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2006-2007 PA Semi, Inc
4 *
5 * Maintained by: Olof Johansson <olof@lixom.ne
6 */
7
8 #include <asm/processor.h>
9 #include <asm/page.h>
10 #include <asm/ppc_asm.h>
11 #include <asm/cputable.h>
12 #include <asm/cache.h>
13 #include <asm/thread_info.h>
14 #include <asm/asm-offsets.h>
15
16 /* Power savings opcodes since not all binutil
17 #define DOZE .long 0x4c000324
18 #define NAP .long 0x4c000364
19 #define SLEEP .long 0x4c0003a4
20 #define RVW .long 0x4c0003e4
21
22 /* Common sequence to do before going to any o
23 * powersavings modes.
24 */
25
26 #define PRE_SLEEP_SEQUENCE \
27 std r3,8(r1); \
28 ptesync ; \
29 ld r3,8(r1); \
30 1: cmpd r3,r3; \
31 bne 1b
32
33 _doze:
34 PRE_SLEEP_SEQUENCE
35 DOZE
36 b .
37
38
39 _GLOBAL(idle_spin)
40 blr
41
42 _GLOBAL(idle_doze)
43 LOAD_REG_ADDR(r3, _doze)
44 b sleep_common
45
46 /* Add more modes here later */
47
48 sleep_common:
49 mflr r0
50 std r0, 16(r1)
51 stdu r1,-64(r1)
52 #ifdef CONFIG_PPC_PASEMI_CPUFREQ
53 std r3, 48(r1)
54
55 /* Only do power savings when in astat
56 bl check_astate
57 cmpwi r3,0
58 bne 1f
59
60 ld r3, 48(r1)
61 #endif
62 LOAD_REG_IMMEDIATE(r6,MSR_DR|MSR_IR|MS
63 mfmsr r4
64 andc r5,r4,r6
65 mtmsrd r5,0
66
67 mtctr r3
68 bctrl
69
70 mtmsrd r4,0
71
72 1: addi r1,r1,64
73 ld r0,16(r1)
74 mtlr r0
75 blr
76
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