1 menu "CPU errata selection"
2
3 config ERRATA_ANDES
4 bool "Andes AX45MP errata"
5 depends on RISCV_ALTERNATIVE && RISCV_
6 help
7 All Andes errata Kconfig depend on t
8 this Kconfig will disable all Andes
9 here if your platform uses Andes CPU
10
11 Otherwise, please say "N" here to av
12
13 config ERRATA_ANDES_CMO
14 bool "Apply Andes cache management err
15 depends on ERRATA_ANDES && ARCH_R9A07G
16 select RISCV_DMA_NONCOHERENT
17 default y
18 help
19 This will apply the cache management
20 non-standard handling on non-coheren
21
22 If you don't know what to do here, s
23
24 config ERRATA_SIFIVE
25 bool "SiFive errata"
26 depends on RISCV_ALTERNATIVE
27 help
28 All SiFive errata Kconfig depend on
29 this Kconfig will disable all SiFive
30 here if your platform uses SiFive CP
31
32 Otherwise, please say "N" here to av
33
34 config ERRATA_SIFIVE_CIP_453
35 bool "Apply SiFive errata CIP-453"
36 depends on ERRATA_SIFIVE && 64BIT
37 default y
38 help
39 This will apply the SiFive CIP-453 e
40 to the $badaddr when exception type
41 and instruction access fault.
42
43 If you don't know what to do here, s
44
45 config ERRATA_SIFIVE_CIP_1200
46 bool "Apply SiFive errata CIP-1200"
47 depends on ERRATA_SIFIVE && 64BIT
48 default y
49 help
50 This will apply the SiFive CIP-1200
51 "sfence.vma addr" with "sfence.vma"
52 has been flushed from TLB.
53
54 If you don't know what to do here, s
55
56 config ERRATA_STARFIVE_JH7100
57 bool "StarFive JH7100 support"
58 depends on ARCH_STARFIVE
59 depends on !DMA_DIRECT_REMAP
60 depends on NONPORTABLE
61 select DMA_GLOBAL_POOL
62 select RISCV_DMA_NONCOHERENT
63 select RISCV_NONSTANDARD_CACHE_OPS
64 select SIFIVE_CCACHE
65 default n
66 help
67 The StarFive JH7100 was a test chip
68 caches that are non-coherent with re
69 It was designed before the Zicbom ex
70 cache operations through the SiFive
71
72 Say "Y" if you want to support the B
73 StarFive VisionFive V1 boards.
74
75 config ERRATA_THEAD
76 bool "T-HEAD errata"
77 depends on RISCV_ALTERNATIVE
78 help
79 All T-HEAD errata Kconfig depend on
80 this Kconfig will disable all T-HEAD
81 here if your platform uses T-HEAD CP
82
83 Otherwise, please say "N" here to av
84
85 config ERRATA_THEAD_MAE
86 bool "Apply T-Head's memory attribute
87 depends on ERRATA_THEAD && 64BIT && MM
88 select RISCV_ALTERNATIVE_EARLY
89 default y
90 help
91 This will apply the memory attribute
92 non-standard PTE utilization on T-He
93
94 If you don't know what to do here, s
95
96 config ERRATA_THEAD_CMO
97 bool "Apply T-Head cache management er
98 depends on ERRATA_THEAD && MMU
99 select DMA_DIRECT_REMAP
100 select RISCV_DMA_NONCOHERENT
101 select RISCV_NONSTANDARD_CACHE_OPS
102 default y
103 help
104 This will apply the cache management
105 non-standard handling on non-coheren
106
107 If you don't know what to do here, s
108
109 config ERRATA_THEAD_PMU
110 bool "Apply T-Head PMU errata"
111 depends on ERRATA_THEAD && RISCV_PMU_S
112 default y
113 help
114 The T-Head C9xx cores implement a PM
115 similar to the core SSCOFPMF extensi
116
117 This will apply the overflow errata
118 behaviour via the regular SBI PMU dr
119
120 If you don't know what to do here, s
121
122 endmenu # "CPU errata selection"
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