1 // SPDX-License-Identifier: GPL-2.0-only 1
2 /*
3 * Copyright (C) 2021 Heiko Stuebner <heiko@sn
4 */
5
6 #include <linux/bug.h>
7 #include <linux/kernel.h>
8 #include <linux/memory.h>
9 #include <linux/module.h>
10 #include <linux/string.h>
11 #include <linux/uaccess.h>
12 #include <asm/alternative.h>
13 #include <asm/cacheflush.h>
14 #include <asm/cpufeature.h>
15 #include <asm/dma-noncoherent.h>
16 #include <asm/errata_list.h>
17 #include <asm/hwprobe.h>
18 #include <asm/io.h>
19 #include <asm/patch.h>
20 #include <asm/vendorid_list.h>
21 #include <asm/vendor_extensions.h>
22
23 #define CSR_TH_SXSTATUS 0x5c0
24 #define SXSTATUS_MAEE _AC(0x200000,
25
26 static bool errata_probe_mae(unsigned int stag
27 unsigned long arc
28 {
29 if (!IS_ENABLED(CONFIG_ERRATA_THEAD_MA
30 return false;
31
32 if (arch_id != 0 || impid != 0)
33 return false;
34
35 if (stage != RISCV_ALTERNATIVES_EARLY_
36 stage != RISCV_ALTERNATIVES_MODULE
37 return false;
38
39 if (!(csr_read(CSR_TH_SXSTATUS) & SXST
40 return false;
41
42 return true;
43 }
44
45 /*
46 * th.dcache.ipa rs1 (invalidate, physical add
47 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 1
48 * 0000001 01010 rs1 000
49 * th.dcache.iva rs1 (invalidate, virtual addr
50 * 0000001 00110 rs1 000
51 *
52 * th.dcache.cpa rs1 (clean, physical address)
53 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 1
54 * 0000001 01001 rs1 000
55 * th.dcache.cva rs1 (clean, virtual address)
56 * 0000001 00101 rs1 000
57 *
58 * th.dcache.cipa rs1 (clean then invalidate,
59 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 1
60 * 0000001 01011 rs1 000
61 * th.dcache.civa rs1 (clean then invalidate,
62 * 0000001 00111 rs1 000
63 *
64 * th.sync.s (make sure all cache operations f
65 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 1
66 * 0000000 11001 00000 000
67 */
68 #define THEAD_INVAL_A0 ".long 0x02a5000b"
69 #define THEAD_CLEAN_A0 ".long 0x0295000b"
70 #define THEAD_FLUSH_A0 ".long 0x02b5000b"
71 #define THEAD_SYNC_S ".long 0x0190000b"
72
73 #define THEAD_CMO_OP(_op, _start, _size, _cach
74 asm volatile("mv a0, %1\n\t"
75 "j 2f\n\t"
76 "3:\n\t"
77 THEAD_##_op##_A0 "\n\t"
78 "add a0, a0, %0\n\t"
79 "2:\n\t"
80 "bltu a0, %2, 3b\n\t"
81 THEAD_SYNC_S
82 : : "r"(_cachesize),
83 "r"((unsigned long)(_start) &
84 "r"((unsigned long)(_start) +
85 : "a0")
86
87 static void thead_errata_cache_inv(phys_addr_t
88 {
89 THEAD_CMO_OP(INVAL, paddr, size, riscv
90 }
91
92 static void thead_errata_cache_wback(phys_addr
93 {
94 THEAD_CMO_OP(CLEAN, paddr, size, riscv
95 }
96
97 static void thead_errata_cache_wback_inv(phys_
98 {
99 THEAD_CMO_OP(FLUSH, paddr, size, riscv
100 }
101
102 static const struct riscv_nonstd_cache_ops the
103 .wback = &thead_errata_cache_wback,
104 .inv = &thead_errata_cache_inv,
105 .wback_inv = &thead_errata_cache_wback
106 };
107
108 static bool errata_probe_cmo(unsigned int stag
109 unsigned long arc
110 {
111 if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CM
112 return false;
113
114 if (arch_id != 0 || impid != 0)
115 return false;
116
117 if (stage == RISCV_ALTERNATIVES_EARLY_
118 return false;
119
120 if (stage == RISCV_ALTERNATIVES_BOOT)
121 riscv_cbom_block_size = L1_CAC
122 riscv_noncoherent_supported();
123 riscv_noncoherent_register_cac
124 }
125
126 return true;
127 }
128
129 static bool errata_probe_pmu(unsigned int stag
130 unsigned long arc
131 {
132 if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PM
133 return false;
134
135 /* target-c9xx cores report arch_id an
136 if (arch_id != 0 || impid != 0)
137 return false;
138
139 if (stage == RISCV_ALTERNATIVES_EARLY_
140 return false;
141
142 return true;
143 }
144
145 static u32 thead_errata_probe(unsigned int sta
146 unsigned long ar
147 {
148 u32 cpu_req_errata = 0;
149
150 if (errata_probe_mae(stage, archid, im
151 cpu_req_errata |= BIT(ERRATA_T
152
153 errata_probe_cmo(stage, archid, impid)
154
155 if (errata_probe_pmu(stage, archid, im
156 cpu_req_errata |= BIT(ERRATA_T
157
158 return cpu_req_errata;
159 }
160
161 void thead_errata_patch_func(struct alt_entry
162 unsigned long arc
163 unsigned int stag
164 {
165 struct alt_entry *alt;
166 u32 cpu_req_errata = thead_errata_prob
167 u32 tmp;
168 void *oldptr, *altptr;
169
170 BUILD_BUG_ON(ERRATA_THEAD_NUMBER >= RI
171
172 for (alt = begin; alt < end; alt++) {
173 if (alt->vendor_id != THEAD_VE
174 continue;
175 if (alt->patch_id >= ERRATA_TH
176 continue;
177
178 tmp = (1U << alt->patch_id);
179 if (cpu_req_errata & tmp) {
180 oldptr = ALT_OLD_PTR(a
181 altptr = ALT_ALT_PTR(a
182
183 /* On vm-alternatives,
184 if (stage == RISCV_ALT
185 memcpy(oldptr,
186 } else {
187 mutex_lock(&te
188 patch_text_nos
189 mutex_unlock(&
190 }
191 }
192 }
193
194 if (stage == RISCV_ALTERNATIVES_EARLY_
195 local_flush_icache_all();
196 }
197
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