1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 /*
3 * Checksum routines
4 *
5 * Copyright (C) 2023 Rivos Inc.
6 */
7 #ifndef __ASM_RISCV_CHECKSUM_H
8 #define __ASM_RISCV_CHECKSUM_H
9
10 #include <linux/in6.h>
11 #include <linux/uaccess.h>
12
13 #define ip_fast_csum ip_fast_csum
14
15 extern unsigned int do_csum(const unsigned cha
16 #define do_csum do_csum
17
18 /* Default version is sufficient for 32 bit */
19 #ifndef CONFIG_32BIT
20 #define _HAVE_ARCH_IPV6_CSUM
21 __sum16 csum_ipv6_magic(const struct in6_addr
22 const struct in6_addr
23 __u32 len, __u8 proto,
24 #endif
25
26 /* Define riscv versions of functions before i
27 #include <asm-generic/checksum.h>
28
29 /**
30 * Quickly compute an IP checksum with the ass
31 * always be in multiples of 32-bits, and have
32 *
33 * @ihl: the number of 32 bit segments and mus
34 * @iph: assumed to be word aligned given that
35 * riscv, defining IP headers to be aligned.
36 */
37 static inline __sum16 ip_fast_csum(const void
38 {
39 unsigned long csum = 0;
40 int pos = 0;
41
42 do {
43 csum += ((const unsigned int *
44 if (IS_ENABLED(CONFIG_32BIT))
45 csum += csum < ((const
46 } while (++pos < ihl);
47
48 /*
49 * ZBB only saves three instructions o
50 * worth checking if supported without
51 */
52 if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &
53 IS_ENABLED(CONFIG_RISCV_ALTERNATIV
54 unsigned long fold_temp;
55
56 asm goto(ALTERNATIVE("j %l[no_
57
58 :
59 :
60 :
61 : no_zbb);
62
63 if (IS_ENABLED(CONFIG_32BIT))
64 asm(".option push
65 .option arch,+zbb
66 not %[fold
67 rori %[csum
68 sub %[csum
69 .option pop"
70 : [csum] "+r" (csum),
71 } else {
72 asm(".option push
73 .option arch,+zbb
74 rori %[fold
75 add %[csum
76 srli %[csum
77 not %[fold
78 roriw %[csum
79 subw %[csum
80 .option pop"
81 : [csum] "+r" (csum),
82 }
83 return (__force __sum16)(csum
84 }
85 no_zbb:
86 #ifndef CONFIG_32BIT
87 csum += ror64(csum, 32);
88 csum >>= 32;
89 #endif
90 return csum_fold((__force __wsum)csum)
91 }
92
93 #endif /* __ASM_RISCV_CHECKSUM_H */
94
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