1 // SPDX-License-Identifier: GPL-2.0-only 1
2 /*
3 * Copyright (C) 2017 SiFive
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/cpu.h>
8 #include <linux/of.h>
9 #include <asm/cacheinfo.h>
10
11 static struct riscv_cacheinfo_ops *rv_cache_op
12
13 void riscv_set_cacheinfo_ops(struct riscv_cach
14 {
15 rv_cache_ops = ops;
16 }
17 EXPORT_SYMBOL_GPL(riscv_set_cacheinfo_ops);
18
19 const struct attribute_group *
20 cache_get_priv_group(struct cacheinfo *this_le
21 {
22 if (rv_cache_ops && rv_cache_ops->get_
23 return rv_cache_ops->get_priv_
24 return NULL;
25 }
26
27 static struct cacheinfo *get_cacheinfo(u32 lev
28 {
29 /*
30 * Using raw_smp_processor_id() elides
31 * is really indicative of a larger pr
32 * that cores have a homonogenous view
33 * happens to be the case for the curr
34 * likely won't be true in general. S
35 * correct information for these syste
36 * just eliding the check for now.
37 */
38 struct cpu_cacheinfo *this_cpu_ci = ge
39 struct cacheinfo *this_leaf;
40 int index;
41
42 for (index = 0; index < this_cpu_ci->n
43 this_leaf = this_cpu_ci->info_
44 if (this_leaf->level == level
45 return this_leaf;
46 }
47
48 return NULL;
49 }
50
51 uintptr_t get_cache_size(u32 level, enum cache
52 {
53 struct cacheinfo *this_leaf = get_cach
54
55 return this_leaf ? this_leaf->size : 0
56 }
57
58 uintptr_t get_cache_geometry(u32 level, enum c
59 {
60 struct cacheinfo *this_leaf = get_cach
61
62 return this_leaf ? (this_leaf->ways_of
63 this_leaf->coheren
64 0;
65 }
66
67 static void ci_leaf_init(struct cacheinfo *thi
68 enum cache_type type,
69 {
70 this_leaf->level = level;
71 this_leaf->type = type;
72 }
73
74 int init_cache_level(unsigned int cpu)
75 {
76 return init_of_cache_level(cpu);
77 }
78
79 int populate_cache_leaves(unsigned int cpu)
80 {
81 struct cpu_cacheinfo *this_cpu_ci = ge
82 struct cacheinfo *this_leaf = this_cpu
83 struct device_node *np, *prev;
84 int levels = 1, level = 1;
85
86 if (!acpi_disabled) {
87 int ret, fw_levels, split_leve
88
89 ret = acpi_get_cache_info(cpu,
90 if (ret)
91 return ret;
92
93 BUG_ON((split_levels > fw_leve
94 (split_levels + fw_leve
95
96 for (; level <= this_cpu_ci->n
97 if (level <= split_lev
98 ci_leaf_init(t
99 ci_leaf_init(t
100 } else {
101 ci_leaf_init(t
102 }
103 }
104 return 0;
105 }
106
107 np = of_cpu_device_node_get(cpu);
108 if (!np)
109 return -ENOENT;
110
111 if (of_property_read_bool(np, "cache-s
112 ci_leaf_init(this_leaf++, CACH
113 if (of_property_read_bool(np, "i-cache
114 ci_leaf_init(this_leaf++, CACH
115 if (of_property_read_bool(np, "d-cache
116 ci_leaf_init(this_leaf++, CACH
117
118 prev = np;
119 while ((np = of_find_next_cache_node(n
120 of_node_put(prev);
121 prev = np;
122 if (!of_device_is_compatible(n
123 break;
124 if (of_property_read_u32(np, "
125 break;
126 if (level <= levels)
127 break;
128 if (of_property_read_bool(np,
129 ci_leaf_init(this_leaf
130 if (of_property_read_bool(np,
131 ci_leaf_init(this_leaf
132 if (of_property_read_bool(np,
133 ci_leaf_init(this_leaf
134 levels = level;
135 }
136 of_node_put(np);
137
138 return 0;
139 }
140
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