1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Copyright (C) 2012 Regents of the Universit !! 2 * This file is subject to the terms and conditions of the GNU General Public
>> 3 * License. See the file "COPYING" in the main directory of this archive
>> 4 * for more details.
>> 5 *
>> 6 * Copyright (C) 1994, 1995 Waldorf Electronics
>> 7 * Written by Ralf Baechle and Andreas Busse
>> 8 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 Ralf Baechle
>> 9 * Copyright (C) 1996 Paul M. Antoine
>> 10 * Modified for DECStation and hence R3000 support by Paul M. Antoine
>> 11 * Further modifications by David S. Miller and Harald Koerfgen
>> 12 * Copyright (C) 1999 Silicon Graphics, Inc.
>> 13 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
>> 14 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 */ 15 */
>> 16 #include <linux/config.h>
>> 17 #include <linux/init.h>
>> 18 #include <linux/threads.h>
5 19
6 #include <asm/asm-offsets.h> <<
7 #include <asm/asm.h> 20 #include <asm/asm.h>
8 #include <linux/init.h> !! 21 #include <asm/regdef.h>
9 #include <linux/linkage.h> <<
10 #include <asm/thread_info.h> <<
11 #include <asm/page.h> 22 #include <asm/page.h>
12 #include <asm/pgtable.h> !! 23 #include <asm/processor.h>
13 #include <asm/csr.h> !! 24 #include <asm/mipsregs.h>
14 #include <asm/hwcap.h> !! 25 #include <asm/stackframe.h>
15 #include <asm/image.h> !! 26 #ifdef CONFIG_SGI_IP27
16 #include <asm/scs.h> !! 27 #include <asm/sn/addrs.h>
17 #include <asm/xip_fixup.h> !! 28 #include <asm/sn/sn0/hubni.h>
18 #include "efi-header.S" !! 29 #include <asm/sn/klkernvars.h>
19 !! 30 #endif
20 __HEAD !! 31
21 SYM_CODE_START(_start) !! 32 .macro ARC64_TWIDDLE_PC
22 /* !! 33 #if defined(CONFIG_ARC64) || defined(CONFIG_MAPPED_KERNEL)
23 * Image header expected by Linux boot !! 34 /* We get launched at a XKPHYS address but the kernel is linked to
24 * structure is described in asm/image !! 35 run at a KSEG0 address, so jump there. */
25 * Do not modify it without modifying !! 36 PTR_LA t0, \@f
26 * that expects this header format!! !! 37 jr t0
27 */ !! 38 \@:
28 #ifdef CONFIG_EFI !! 39 #endif
29 /* !! 40 .endm
30 * This instruction decodes to "MZ" AS !! 41
31 */ !! 42 #ifdef CONFIG_SGI_IP27
32 c.li s4,-13 !! 43 /*
33 j _start_kernel !! 44 * outputs the local nasid into res. IP27 stuff.
34 #else !! 45 */
35 /* jump to start kernel */ !! 46 .macro GET_NASID_ASM res
36 j _start_kernel !! 47 dli \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
37 /* reserved */ !! 48 ld \res, (\res)
38 .word 0 !! 49 and \res, NSRI_NODEID_MASK
39 #endif !! 50 dsrl \res, NSRI_NODEID_SHFT
40 .balign 8 !! 51 .endm
41 #ifdef CONFIG_RISCV_M_MODE !! 52 #endif /* CONFIG_SGI_IP27 */
42 /* Image load offset (0MB) from start !! 53
43 .dword 0 !! 54 /*
44 #else !! 55 * inputs are the text nasid in t1, data nasid in t2.
45 #if __riscv_xlen == 64 !! 56 */
46 /* Image load offset(2MB) from start o !! 57 .macro MAPPED_KERNEL_SETUP_TLB
47 .dword 0x200000 !! 58 #ifdef CONFIG_MAPPED_KERNEL
48 #else !! 59 /*
49 /* Image load offset(4MB) from start o !! 60 * This needs to read the nasid - assume 0 for now.
50 .dword 0x400000 !! 61 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
51 #endif !! 62 * 0+DVG in tlblo_1.
52 #endif !! 63 */
53 /* Effective size of kernel image */ !! 64 dli t0, 0xffffffffc0000000
54 .dword _end - _start !! 65 dmtc0 t0, CP0_ENTRYHI
55 .dword __HEAD_FLAGS !! 66 li t0, 0x1c000 # Offset of text into node memory
56 .word RISCV_HEADER_VERSION !! 67 dsll t1, NASID_SHFT # Shift text nasid into place
57 .word 0 !! 68 dsll t2, NASID_SHFT # Same for data nasid
58 .dword 0 !! 69 or t1, t1, t0 # Physical load address of kernel text
59 .ascii RISCV_IMAGE_MAGIC !! 70 or t2, t2, t0 # Physical load address of kernel data
60 .balign 4 !! 71 dsrl t1, 12 # 4K pfn
61 .ascii RISCV_IMAGE_MAGIC2 !! 72 dsrl t2, 12 # 4K pfn
62 #ifdef CONFIG_EFI !! 73 dsll t1, 6 # Get pfn into place
63 .word pe_head_start - _start !! 74 dsll t2, 6 # Get pfn into place
64 pe_head_start: !! 75 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
65 !! 76 or t0, t0, t1
66 __EFI_PE_HEADER !! 77 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
67 #else !! 78 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
68 .word 0 !! 79 or t0, t0, t2
69 #endif !! 80 mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
70 !! 81 li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
71 .align 2 !! 82 mtc0 t0, CP0_PAGEMASK
72 #ifdef CONFIG_MMU !! 83 li t0, 0 # KMAP_INX
73 .global relocate_enable_mmu !! 84 mtc0 t0, CP0_INDEX
74 relocate_enable_mmu: !! 85 li t0, 1
75 /* Relocate return address */ !! 86 mtc0 t0, CP0_WIRED
76 la a1, kernel_map !! 87 tlbwi
77 XIP_FIXUP_OFFSET a1 !! 88 #else
78 REG_L a1, KERNEL_MAP_VIRT_ADDR(a1) !! 89 mtc0 zero, CP0_WIRED
79 la a2, _start !! 90 #endif
80 sub a1, a1, a2 !! 91 .endm
81 add ra, ra, a1 !! 92
82 !! 93 /*
83 /* Point stvec to virtual address of i !! 94 * Reserved space for exception handlers.
84 la a2, 1f !! 95 * Necessary for machines which link their kernels at KSEG0.
85 add a2, a2, a1 !! 96 */
86 csrw CSR_TVEC, a2 !! 97 .fill 0x400
87 !! 98
88 /* Compute satp for kernel page tables !! 99 EXPORT(stext) # used for profiling
89 srl a2, a0, PAGE_SHIFT !! 100 EXPORT(_stext)
90 la a1, satp_mode !! 101
91 XIP_FIXUP_OFFSET a1 !! 102 __INIT
92 REG_L a1, 0(a1) !! 103
93 or a2, a2, a1 !! 104 NESTED(kernel_entry, 16, sp) # kernel entry point
94 !! 105 #ifdef CONFIG_SGI_IP27
95 /* !! 106 GET_NASID_ASM t1
96 * Load trampoline page directory, whi !! 107 move t2, t1 # text and data are here
97 * stvec if VA != PA, or simply fall t !! 108 MAPPED_KERNEL_SETUP_TLB
98 * full fence here because setup_vm() !! 109 #endif /* IP27 */
99 * to ensure the new translations are !! 110
100 */ !! 111 ARC64_TWIDDLE_PC
101 la a0, trampoline_pg_dir !! 112
102 XIP_FIXUP_OFFSET a0 !! 113 CLI # disable interrupts
103 srl a0, a0, PAGE_SHIFT !! 114
104 or a0, a0, a1 !! 115 PTR_LA $28, init_thread_union
105 sfence.vma !! 116 PTR_ADDIU sp, $28, _THREAD_SIZE - 32
106 csrw CSR_SATP, a0 !! 117 set_saved_sp sp, t0, t1
107 .align 2 !! 118 PTR_SUBU sp, 4 * SZREG # init stack pointer
>> 119
>> 120 /*
>> 121 * The firmware/bootloader passes argc/argp/envp
>> 122 * to us as arguments. But clear bss first because
>> 123 * the romvec and other important info is stored there
>> 124 * by prom_init().
>> 125 */
>> 126 PTR_LA t0, __bss_start
>> 127 LONG_S zero, (t0)
>> 128 PTR_LA t1, __bss_stop - LONGSIZE
108 1: 129 1:
109 /* Set trap vector to spin forever to !! 130 PTR_ADDIU t0, LONGSIZE
110 la a0, .Lsecondary_park !! 131 LONG_S zero, (t0)
111 csrw CSR_TVEC, a0 !! 132 bne t0, t1, 1b
112 133
113 /* Reload the global pointer */ !! 134 jal init_arch
114 load_global_pointer !! 135 END(kernel_entry)
115 136
116 /* <<
117 * Switch to kernel page tables. A fu <<
118 * avoid using the trampoline translat <<
119 * the first superpage. Fetching the <<
120 * because that first superpage is tra <<
121 */ <<
122 csrw CSR_SATP, a2 <<
123 sfence.vma <<
124 <<
125 ret <<
126 #endif /* CONFIG_MMU */ <<
127 #ifdef CONFIG_SMP 137 #ifdef CONFIG_SMP
128 .global secondary_start_sbi !! 138 /*
129 secondary_start_sbi: !! 139 * SMP slave cpus entry point. Board specific code for bootstrap calls this
130 /* Mask all interrupts */ !! 140 * function after setting up the stack and gp registers.
131 csrw CSR_IE, zero !! 141 */
132 csrw CSR_IP, zero !! 142 NESTED(smp_bootstrap, 16, sp)
133 !! 143 #ifdef CONFIG_SGI_IP27
134 /* Load the global pointer */ !! 144 GET_NASID_ASM t1
135 load_global_pointer !! 145 li t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \
136 !! 146 KLDIR_OFF_POINTER + K0BASE
137 /* !! 147 dsll t1, NASID_SHFT
138 * Disable FPU & VECTOR to detect ille !! 148 or t0, t0, t1
139 * floating point or vector in kernel !! 149 ld t0, 0(t0) # t0 points to kern_vars struct
140 */ !! 150 lh t1, KV_RO_NASID_OFFSET(t0)
141 li t0, SR_FS_VS !! 151 lh t2, KV_RW_NASID_OFFSET(t0)
142 csrc CSR_STATUS, t0 !! 152 MAPPED_KERNEL_SETUP_TLB
143 !! 153 ARC64_TWIDDLE_PC
144 /* Set trap vector to spin forever to !! 154 #endif /* CONFIG_SGI_IP27 */
145 la a3, .Lsecondary_park !! 155
146 csrw CSR_TVEC, a3 !! 156 CLI
147 !! 157
148 /* a0 contains the hartid & a1 contain !! 158 #ifdef CONFIG_MIPS64
149 li a2, SBI_HART_BOOT_TASK_PTR_OFFSET !! 159 /*
150 XIP_FIXUP_OFFSET a2 !! 160 * For the moment set ST0_KU so the CPU will not spit fire when
151 add a2, a2, a1 !! 161 * executing 64-bit instructions. The full initialization of the
152 REG_L tp, (a2) !! 162 * CPU's status register is done later in per_cpu_trap_init().
153 li a3, SBI_HART_BOOT_STACK_PTR_OFFSET !! 163 */
154 XIP_FIXUP_OFFSET a3 !! 164 mfc0 t0, CP0_STATUS
155 add a3, a3, a1 !! 165 or t0, ST0_KX
156 REG_L sp, (a3) !! 166 mtc0 t0, CP0_STATUS
157 <<
158 .Lsecondary_start_common: <<
159 <<
160 #ifdef CONFIG_MMU <<
161 /* Enable virtual memory and relocate <<
162 la a0, swapper_pg_dir <<
163 XIP_FIXUP_OFFSET a0 <<
164 call relocate_enable_mmu <<
165 #endif 167 #endif
166 call .Lsetup_trap_vector !! 168 jal start_secondary
167 scs_load_current !! 169 END(smp_bootstrap)
168 call smp_callin <<
169 #endif /* CONFIG_SMP */ 170 #endif /* CONFIG_SMP */
170 171
171 .align 2 !! 172 __FINIT
172 .Lsecondary_park: <<
173 /* <<
174 * Park this hart if we: <<
175 * - have too many harts on CONFIG_RI <<
176 * - receive an early trap, before se <<
177 * - fail in smp_callin(), as a succe <<
178 */ <<
179 wfi <<
180 j .Lsecondary_park <<
181 <<
182 .align 2 <<
183 .Lsetup_trap_vector: <<
184 /* Set trap vector to exception handle <<
185 la a0, handle_exception <<
186 csrw CSR_TVEC, a0 <<
187 <<
188 /* <<
189 * Set sup0 scratch register to 0, ind <<
190 * we are presently executing in kerne <<
191 */ <<
192 csrw CSR_SCRATCH, zero <<
193 ret <<
194 173
195 SYM_CODE_END(_start) !! 174 .comm kernelsp, NR_CPUS * 8, 8
>> 175 .comm pgd_current, NR_CPUS * 8, 8
196 176
197 SYM_CODE_START(_start_kernel) !! 177 .macro page name, order=0
198 /* Mask all interrupts */ !! 178 .globl \name
199 csrw CSR_IE, zero !! 179 \name: .size \name, (_PAGE_SIZE << \order)
200 csrw CSR_IP, zero !! 180 .org . + (_PAGE_SIZE << \order)
201 !! 181 .type \name, @object
202 #ifdef CONFIG_RISCV_M_MODE !! 182 .endm
203 /* flush the instruction cache */ <<
204 fence.i <<
205 183
206 /* Reset all registers except ra, a0, !! 184 .data
207 call reset_regs !! 185 .align PAGE_SHIFT
208 186
>> 187 #ifdef CONFIG_MIPS32
209 /* 188 /*
210 * Setup a PMP to permit access to all !! 189 * Here we only have a two-level pagetable structure ...
211 * not implement PMPs, so we set up a <<
212 * touching the PMPs on any trap. <<
213 */ 190 */
214 la a0, .Lpmp_done !! 191 page swapper_pg_dir, _PGD_ORDER
215 csrw CSR_TVEC, a0 !! 192 page invalid_pte_table, _PTE_ORDER
216 <<
217 li a0, -1 <<
218 csrw CSR_PMPADDR0, a0 <<
219 li a0, (PMP_A_NAPOT | PMP_R | PMP_W | <<
220 csrw CSR_PMPCFG0, a0 <<
221 .align 2 <<
222 .Lpmp_done: <<
223 <<
224 /* <<
225 * The hartid in a0 is expected later <<
226 * to hand it to us. <<
227 */ <<
228 csrr a0, CSR_MHARTID <<
229 #endif /* CONFIG_RISCV_M_MODE */ <<
230 <<
231 /* Load the global pointer */ <<
232 load_global_pointer <<
233 <<
234 /* <<
235 * Disable FPU & VECTOR to detect ille <<
236 * floating point or vector in kernel <<
237 */ <<
238 li t0, SR_FS_VS <<
239 csrc CSR_STATUS, t0 <<
240 <<
241 #ifdef CONFIG_RISCV_BOOT_SPINWAIT <<
242 li t0, CONFIG_NR_CPUS <<
243 blt a0, t0, .Lgood_cores <<
244 tail .Lsecondary_park <<
245 .Lgood_cores: <<
246 <<
247 /* The lottery system is only required <<
248 #ifndef CONFIG_XIP_KERNEL <<
249 /* Pick one hart to run the main boot <<
250 la a3, hart_lottery <<
251 li a2, 1 <<
252 amoadd.w a3, a2, (a3) <<
253 bnez a3, .Lsecondary_start <<
254 <<
255 #else <<
256 /* hart_lottery in flash contains a ma <<
257 la a3, hart_lottery <<
258 mv a2, a3 <<
259 XIP_FIXUP_OFFSET a2 <<
260 XIP_FIXUP_FLASH_OFFSET a3 <<
261 lw t1, (a3) <<
262 amoswap.w t0, t1, (a2) <<
263 /* first time here if hart_lottery in <<
264 beq t0, t1, .Lsecondary_start <<
265 <<
266 #endif /* CONFIG_XIP */ <<
267 #endif /* CONFIG_RISCV_BOOT_SPINWAIT */ <<
268 <<
269 #ifdef CONFIG_XIP_KERNEL <<
270 la sp, _end + THREAD_SIZE <<
271 XIP_FIXUP_OFFSET sp <<
272 mv s0, a0 <<
273 mv s1, a1 <<
274 call __copy_data <<
275 <<
276 /* Restore a0 & a1 copy */ <<
277 mv a0, s0 <<
278 mv a1, s1 <<
279 #endif 193 #endif
280 !! 194 #ifdef CONFIG_MIPS64
281 #ifndef CONFIG_XIP_KERNEL <<
282 /* Clear BSS for flat non-ELF images * <<
283 la a3, __bss_start <<
284 la a4, __bss_stop <<
285 ble a4, a3, .Lclear_bss_done <<
286 .Lclear_bss: <<
287 REG_S zero, (a3) <<
288 add a3, a3, RISCV_SZPTR <<
289 blt a3, a4, .Lclear_bss <<
290 .Lclear_bss_done: <<
291 #endif <<
292 la a2, boot_cpu_hartid <<
293 XIP_FIXUP_OFFSET a2 <<
294 REG_S a0, (a2) <<
295 <<
296 /* Initialize page tables and relocate <<
297 la tp, init_task <<
298 la sp, init_thread_union + THREAD_SIZE <<
299 XIP_FIXUP_OFFSET sp <<
300 addi sp, sp, -PT_SIZE_ON_STACK <<
301 scs_load_init_stack <<
302 #ifdef CONFIG_BUILTIN_DTB <<
303 la a0, __dtb_start <<
304 XIP_FIXUP_OFFSET a0 <<
305 #else <<
306 mv a0, a1 <<
307 #endif /* CONFIG_BUILTIN_DTB */ <<
308 /* Set trap vector to spin forever to <<
309 la a3, .Lsecondary_park <<
310 csrw CSR_TVEC, a3 <<
311 call setup_vm <<
312 #ifdef CONFIG_MMU <<
313 la a0, early_pg_dir <<
314 XIP_FIXUP_OFFSET a0 <<
315 call relocate_enable_mmu <<
316 #endif /* CONFIG_MMU */ <<
317 <<
318 call .Lsetup_trap_vector <<
319 /* Restore C environment */ <<
320 la tp, init_task <<
321 la sp, init_thread_union + THREAD_SIZE <<
322 addi sp, sp, -PT_SIZE_ON_STACK <<
323 scs_load_current <<
324 <<
325 #ifdef CONFIG_KASAN <<
326 call kasan_early_init <<
327 #endif <<
328 /* Start the kernel */ <<
329 call soc_early_init <<
330 tail start_kernel <<
331 <<
332 #ifdef CONFIG_RISCV_BOOT_SPINWAIT <<
333 .Lsecondary_start: <<
334 /* Set trap vector to spin forever to <<
335 la a3, .Lsecondary_park <<
336 csrw CSR_TVEC, a3 <<
337 <<
338 slli a3, a0, LGREG <<
339 la a1, __cpu_spinwait_stack_pointer <<
340 XIP_FIXUP_OFFSET a1 <<
341 la a2, __cpu_spinwait_task_pointer <<
342 XIP_FIXUP_OFFSET a2 <<
343 add a1, a3, a1 <<
344 add a2, a3, a2 <<
345 <<
346 /* 195 /*
347 * This hart didn't win the lottery, s !! 196 * ... but on 64-bit we've got three-level pagetables with a
348 * get far enough along the boot proce !! 197 * slightly different layout ...
349 */ 198 */
350 .Lwait_for_cpu_up: !! 199 page swapper_pg_dir, _PGD_ORDER
351 /* FIXME: We should WFI to save some e !! 200 page invalid_pmd_table, _PMD_ORDER
352 REG_L sp, (a1) !! 201 page invalid_pte_table, _PTE_ORDER
353 REG_L tp, (a2) <<
354 beqz sp, .Lwait_for_cpu_up <<
355 beqz tp, .Lwait_for_cpu_up <<
356 fence <<
357 <<
358 tail .Lsecondary_start_common <<
359 #endif /* CONFIG_RISCV_BOOT_SPINWAIT */ <<
360 <<
361 SYM_CODE_END(_start_kernel) <<
362 <<
363 #ifdef CONFIG_RISCV_M_MODE <<
364 SYM_CODE_START_LOCAL(reset_regs) <<
365 li sp, 0 <<
366 li gp, 0 <<
367 li tp, 0 <<
368 li t0, 0 <<
369 li t1, 0 <<
370 li t2, 0 <<
371 li s0, 0 <<
372 li s1, 0 <<
373 li a2, 0 <<
374 li a3, 0 <<
375 li a4, 0 <<
376 li a5, 0 <<
377 li a6, 0 <<
378 li a7, 0 <<
379 li s2, 0 <<
380 li s3, 0 <<
381 li s4, 0 <<
382 li s5, 0 <<
383 li s6, 0 <<
384 li s7, 0 <<
385 li s8, 0 <<
386 li s9, 0 <<
387 li s10, 0 <<
388 li s11, 0 <<
389 li t3, 0 <<
390 li t4, 0 <<
391 li t5, 0 <<
392 li t6, 0 <<
393 csrw CSR_SCRATCH, 0 <<
394 <<
395 #ifdef CONFIG_FPU <<
396 csrr t0, CSR_MISA <<
397 andi t0, t0, (COMPAT_HWCAP_ISA_F | <<
398 beqz t0, .Lreset_regs_done_fpu <<
399 <<
400 li t1, SR_FS <<
401 csrs CSR_STATUS, t1 <<
402 fmv.s.x f0, zero <<
403 fmv.s.x f1, zero <<
404 fmv.s.x f2, zero <<
405 fmv.s.x f3, zero <<
406 fmv.s.x f4, zero <<
407 fmv.s.x f5, zero <<
408 fmv.s.x f6, zero <<
409 fmv.s.x f7, zero <<
410 fmv.s.x f8, zero <<
411 fmv.s.x f9, zero <<
412 fmv.s.x f10, zero <<
413 fmv.s.x f11, zero <<
414 fmv.s.x f12, zero <<
415 fmv.s.x f13, zero <<
416 fmv.s.x f14, zero <<
417 fmv.s.x f15, zero <<
418 fmv.s.x f16, zero <<
419 fmv.s.x f17, zero <<
420 fmv.s.x f18, zero <<
421 fmv.s.x f19, zero <<
422 fmv.s.x f20, zero <<
423 fmv.s.x f21, zero <<
424 fmv.s.x f22, zero <<
425 fmv.s.x f23, zero <<
426 fmv.s.x f24, zero <<
427 fmv.s.x f25, zero <<
428 fmv.s.x f26, zero <<
429 fmv.s.x f27, zero <<
430 fmv.s.x f28, zero <<
431 fmv.s.x f29, zero <<
432 fmv.s.x f30, zero <<
433 fmv.s.x f31, zero <<
434 csrw fcsr, 0 <<
435 /* note that the caller must clear SR_ <<
436 .Lreset_regs_done_fpu: <<
437 #endif /* CONFIG_FPU */ <<
438 <<
439 #ifdef CONFIG_RISCV_ISA_V <<
440 csrr t0, CSR_MISA <<
441 li t1, COMPAT_HWCAP_ISA_V <<
442 and t0, t0, t1 <<
443 beqz t0, .Lreset_regs_done_vector <<
444 202
445 /* 203 /*
446 * Clear vector registers and reset vc !! 204 * 64-bit kernel mappings are really screwed up ...
447 * VLMAX has a defined value, VLEN is <<
448 * and this form of vsetvli is defined <<
449 */ 205 */
450 li t1, SR_VS !! 206 page kptbl, _PGD_ORDER
451 csrs CSR_STATUS, t1 !! 207 .globl ekptbl
452 csrs CSR_VCSR, x0 !! 208 page kpmdtbl, 0
453 vsetvli t1, x0, e8, m8, ta, ma !! 209 ekptbl:
454 vmv.v.i v0, 0 !! 210 #endif
455 vmv.v.i v8, 0 <<
456 vmv.v.i v16, 0 <<
457 vmv.v.i v24, 0 <<
458 /* note that the caller must clear SR_ <<
459 .Lreset_regs_done_vector: <<
460 #endif /* CONFIG_RISCV_ISA_V */ <<
461 ret <<
462 SYM_CODE_END(reset_regs) <<
463 #endif /* CONFIG_RISCV_M_MODE */ <<
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