1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Copyright (C) 2013 Regents of the Universit !! 2 * linux/arch/alpha/memset.S
>> 3 *
>> 4 * This is an efficient (and small) implementation of the C library "memset()"
>> 5 * function for the alpha.
>> 6 *
>> 7 * (C) Copyright 1996 Linus Torvalds
>> 8 *
>> 9 * This routine is "moral-ware": you are free to use it any way you wish, and
>> 10 * the only obligation I put on you is a moral one: if you make any improvements
>> 11 * to the routine, please send me your improvements for me to use similarly.
>> 12 *
>> 13 * The scheduling comments are according to the EV5 documentation (and done by
>> 14 * hand, so they might well be incorrect, please do tell me about it..)
4 */ 15 */
5 16
6 !! 17 .set noat
7 #include <linux/linkage.h> !! 18 .set noreorder
8 #include <asm/asm.h> !! 19 .text
9 !! 20 .globl __memset
10 /* void *memset(void *, int, size_t) */ !! 21 .globl __memsetw
11 SYM_FUNC_START(__memset) !! 22 .globl __constant_c_memset
12 move t0, a0 /* Preserve return value !! 23 .ent __memset
13 !! 24 .align 5
14 /* Defer to byte-oriented fill for sma !! 25 __memset:
15 sltiu a3, a2, 16 !! 26 .frame $30,0,$26,0
16 bnez a3, 4f !! 27 .prologue 0
17 !! 28
18 /* !! 29 and $17,255,$1 /* E1 */
19 * Round to nearest XLEN-aligned addre !! 30 insbl $17,1,$17 /* .. E0 */
20 * greater than or equal to start addr !! 31 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
21 */ !! 32 sll $17,16,$1 /* E1 (p-c latency, next cycle) */
22 addi a3, t0, SZREG-1 !! 33
23 andi a3, a3, ~(SZREG-1) !! 34 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
24 beq a3, t0, 2f /* Skip if already ali !! 35 sll $17,32,$1 /* E1 (p-c latency, next cycle) */
25 /* Handle initial misalignment */ !! 36 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
26 sub a4, a3, t0 !! 37 ldq_u $31,0($30) /* .. E1 */
27 1: !! 38
28 sb a1, 0(t0) !! 39 .align 5
29 addi t0, t0, 1 !! 40 __constant_c_memset:
30 bltu t0, a3, 1b !! 41 addq $18,$16,$6 /* E0 */
31 sub a2, a2, a4 /* Update count */ !! 42 bis $16,$16,$0 /* .. E1 */
32 !! 43 xor $16,$6,$1 /* E0 */
33 2: /* Duff's device with 32 XLEN stores per it !! 44 ble $18,end /* .. E1 */
34 /* Broadcast value into all bytes */ !! 45
35 andi a1, a1, 0xff !! 46 bic $1,7,$1 /* E0 */
36 slli a3, a1, 8 !! 47 beq $1,within_one_quad /* .. E1 (note EV5 zero-latency forwarding) */
37 or a1, a3, a1 !! 48 and $16,7,$3 /* E0 */
38 slli a3, a1, 16 !! 49 beq $3,aligned /* .. E1 (note EV5 zero-latency forwarding) */
39 or a1, a3, a1 !! 50
40 #ifdef CONFIG_64BIT !! 51 ldq_u $4,0($16) /* E0 */
41 slli a3, a1, 32 !! 52 bis $16,$16,$5 /* .. E1 */
42 or a1, a3, a1 !! 53 insql $17,$16,$2 /* E0 */
43 #endif !! 54 subq $3,8,$3 /* .. E1 */
44 !! 55
45 /* Calculate end address */ !! 56 addq $18,$3,$18 /* E0 $18 is new count ($3 is negative) */
46 andi a4, a2, ~(SZREG-1) !! 57 mskql $4,$16,$4 /* .. E1 (and possible load stall) */
47 add a3, t0, a4 !! 58 subq $16,$3,$16 /* E0 $16 is new aligned destination */
48 !! 59 bis $2,$4,$1 /* .. E1 */
49 andi a4, a4, 31*SZREG /* Calculate re !! 60
50 beqz a4, 3f /* Shortcut if !! 61 bis $31,$31,$31 /* E0 */
51 neg a4, a4 !! 62 ldq_u $31,0($30) /* .. E1 */
52 addi a4, a4, 32*SZREG /* Calculate in !! 63 stq_u $1,0($5) /* E0 */
53 !! 64 bis $31,$31,$31 /* .. E1 */
54 /* Adjust start address with offset */ !! 65
55 sub t0, t0, a4 !! 66 .align 4
56 !! 67 aligned:
57 /* Jump into loop body */ !! 68 sra $18,3,$3 /* E0 */
58 /* Assumes 32-bit instruction lengths !! 69 and $18,7,$18 /* .. E1 */
59 la a5, 3f !! 70 bis $16,$16,$5 /* E0 */
60 #ifdef CONFIG_64BIT !! 71 beq $3,no_quad /* .. E1 */
61 srli a4, a4, 1 !! 72
>> 73 .align 3
>> 74 loop:
>> 75 stq $17,0($5) /* E0 */
>> 76 subq $3,1,$3 /* .. E1 */
>> 77 addq $5,8,$5 /* E0 */
>> 78 bne $3,loop /* .. E1 */
>> 79
>> 80 no_quad:
>> 81 bis $31,$31,$31 /* E0 */
>> 82 beq $18,end /* .. E1 */
>> 83 ldq $7,0($5) /* E0 */
>> 84 mskqh $7,$6,$2 /* .. E1 (and load stall) */
>> 85
>> 86 insqh $17,$6,$4 /* E0 */
>> 87 bis $2,$4,$1 /* .. E1 */
>> 88 stq $1,0($5) /* E0 */
>> 89 ret $31,($26),1 /* .. E1 */
>> 90
>> 91 .align 3
>> 92 within_one_quad:
>> 93 ldq_u $1,0($16) /* E0 */
>> 94 insql $17,$16,$2 /* E1 */
>> 95 mskql $1,$16,$4 /* E0 (after load stall) */
>> 96 bis $2,$4,$2 /* E0 */
>> 97
>> 98 mskql $2,$6,$4 /* E0 */
>> 99 mskqh $1,$6,$2 /* .. E1 */
>> 100 bis $2,$4,$1 /* E0 */
>> 101 stq_u $1,0($16) /* E0 */
>> 102
>> 103 end:
>> 104 ret $31,($26),1 /* E1 */
>> 105 .end __memset
>> 106
>> 107 .align 5
>> 108 .ent __memsetw
>> 109 __memsetw:
>> 110 .prologue 0
>> 111
>> 112 inswl $17,0,$1 /* E0 */
>> 113 inswl $17,2,$2 /* E0 */
>> 114 inswl $17,4,$3 /* E0 */
>> 115 or $1,$2,$1 /* .. E1 */
>> 116 inswl $17,6,$4 /* E0 */
>> 117 or $1,$3,$1 /* .. E1 */
>> 118 or $1,$4,$17 /* E0 */
>> 119 br __constant_c_memset /* .. E1 */
>> 120
>> 121 .end __memsetw
>> 122
>> 123 #ifdef __ELF__
>> 124 .weak memset; memset = __memset
>> 125 #else
>> 126 .weakext memset, __memset
62 #endif 127 #endif
63 add a5, a5, a4 <<
64 jr a5 <<
65 3: <<
66 REG_S a1, 0(t0) <<
67 REG_S a1, SZREG(t0) <<
68 REG_S a1, 2*SZREG(t0) <<
69 REG_S a1, 3*SZREG(t0) <<
70 REG_S a1, 4*SZREG(t0) <<
71 REG_S a1, 5*SZREG(t0) <<
72 REG_S a1, 6*SZREG(t0) <<
73 REG_S a1, 7*SZREG(t0) <<
74 REG_S a1, 8*SZREG(t0) <<
75 REG_S a1, 9*SZREG(t0) <<
76 REG_S a1, 10*SZREG(t0) <<
77 REG_S a1, 11*SZREG(t0) <<
78 REG_S a1, 12*SZREG(t0) <<
79 REG_S a1, 13*SZREG(t0) <<
80 REG_S a1, 14*SZREG(t0) <<
81 REG_S a1, 15*SZREG(t0) <<
82 REG_S a1, 16*SZREG(t0) <<
83 REG_S a1, 17*SZREG(t0) <<
84 REG_S a1, 18*SZREG(t0) <<
85 REG_S a1, 19*SZREG(t0) <<
86 REG_S a1, 20*SZREG(t0) <<
87 REG_S a1, 21*SZREG(t0) <<
88 REG_S a1, 22*SZREG(t0) <<
89 REG_S a1, 23*SZREG(t0) <<
90 REG_S a1, 24*SZREG(t0) <<
91 REG_S a1, 25*SZREG(t0) <<
92 REG_S a1, 26*SZREG(t0) <<
93 REG_S a1, 27*SZREG(t0) <<
94 REG_S a1, 28*SZREG(t0) <<
95 REG_S a1, 29*SZREG(t0) <<
96 REG_S a1, 30*SZREG(t0) <<
97 REG_S a1, 31*SZREG(t0) <<
98 addi t0, t0, 32*SZREG <<
99 bltu t0, a3, 3b <<
100 andi a2, a2, SZREG-1 /* Update count <<
101 <<
102 4: <<
103 /* Handle trailing misalignment */ <<
104 beqz a2, 6f <<
105 add a3, t0, a2 <<
106 5: <<
107 sb a1, 0(t0) <<
108 addi t0, t0, 1 <<
109 bltu t0, a3, 5b <<
110 6: <<
111 ret <<
112 SYM_FUNC_END(__memset) <<
113 SYM_FUNC_ALIAS_WEAK(memset, __memset) <<
114 SYM_FUNC_ALIAS(__pi_memset, __memset) <<
115 SYM_FUNC_ALIAS(__pi___memset, __memset) <<
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