1 // SPDX-License-Identifier: GPL-2.0 1
2 /*
3 * Extract CPU cache information and expose th
4 *
5 * Copyright IBM Corp. 2012
6 */
7
8 #include <linux/seq_file.h>
9 #include <linux/cpu.h>
10 #include <linux/cacheinfo.h>
11 #include <asm/facility.h>
12
13 enum {
14 CACHE_SCOPE_NOTEXISTS,
15 CACHE_SCOPE_PRIVATE,
16 CACHE_SCOPE_SHARED,
17 CACHE_SCOPE_RESERVED,
18 };
19
20 enum {
21 CTYPE_SEPARATE,
22 CTYPE_DATA,
23 CTYPE_INSTRUCTION,
24 CTYPE_UNIFIED,
25 };
26
27 enum {
28 EXTRACT_TOPOLOGY,
29 EXTRACT_LINE_SIZE,
30 EXTRACT_SIZE,
31 EXTRACT_ASSOCIATIVITY,
32 };
33
34 enum {
35 CACHE_TI_UNIFIED = 0,
36 CACHE_TI_DATA = 0,
37 CACHE_TI_INSTRUCTION,
38 };
39
40 struct cache_info {
41 unsigned char : 4;
42 unsigned char scope : 2;
43 unsigned char type : 2;
44 };
45
46 #define CACHE_MAX_LEVEL 8
47 union cache_topology {
48 struct cache_info ci[CACHE_MAX_LEVEL];
49 unsigned long raw;
50 };
51
52 static const char * const cache_type_string[]
53 "",
54 "Instruction",
55 "Data",
56 "",
57 "Unified",
58 };
59
60 static const enum cache_type cache_type_map[]
61 [CTYPE_SEPARATE] = CACHE_TYPE_SEPARATE
62 [CTYPE_DATA] = CACHE_TYPE_DATA,
63 [CTYPE_INSTRUCTION] = CACHE_TYPE_INST,
64 [CTYPE_UNIFIED] = CACHE_TYPE_UNIFIED,
65 };
66
67 void show_cacheinfo(struct seq_file *m)
68 {
69 struct cpu_cacheinfo *this_cpu_ci;
70 struct cacheinfo *cache;
71 int idx;
72
73 this_cpu_ci = get_cpu_cacheinfo(cpumas
74 for (idx = 0; idx < this_cpu_ci->num_l
75 cache = this_cpu_ci->info_list
76 seq_printf(m, "cache%-11d: ",
77 seq_printf(m, "level=%d ", cac
78 seq_printf(m, "type=%s ", cach
79 seq_printf(m, "scope=%s ",
80 cache->disable_sysf
81 seq_printf(m, "size=%dK ", cac
82 seq_printf(m, "line_size=%u ",
83 seq_printf(m, "associativity=%
84 seq_puts(m, "\n");
85 }
86 }
87
88 static inline enum cache_type get_cache_type(s
89 {
90 if (level >= CACHE_MAX_LEVEL)
91 return CACHE_TYPE_NOCACHE;
92 ci += level;
93 if (ci->scope != CACHE_SCOPE_SHARED &&
94 return CACHE_TYPE_NOCACHE;
95 return cache_type_map[ci->type];
96 }
97
98 static inline unsigned long ecag(int ai, int l
99 {
100 return __ecag(ECAG_CACHE_ATTRIBUTE, ai
101 }
102
103 static void ci_leaf_init(struct cacheinfo *thi
104 enum cache_type type,
105 {
106 int ti, num_sets;
107
108 if (type == CACHE_TYPE_INST)
109 ti = CACHE_TI_INSTRUCTION;
110 else
111 ti = CACHE_TI_UNIFIED;
112 this_leaf->level = level + 1;
113 this_leaf->type = type;
114 this_leaf->coherency_line_size = ecag(
115 this_leaf->ways_of_associativity = eca
116 this_leaf->size = ecag(EXTRACT_SIZE, l
117 num_sets = this_leaf->size / this_leaf
118 num_sets /= this_leaf->ways_of_associa
119 this_leaf->number_of_sets = num_sets;
120 cpumask_set_cpu(cpu, &this_leaf->share
121 if (!private)
122 this_leaf->disable_sysfs = tru
123 }
124
125 int init_cache_level(unsigned int cpu)
126 {
127 struct cpu_cacheinfo *this_cpu_ci = ge
128 unsigned int level = 0, leaves = 0;
129 union cache_topology ct;
130 enum cache_type ctype;
131
132 if (!this_cpu_ci)
133 return -EINVAL;
134 ct.raw = ecag(EXTRACT_TOPOLOGY, 0, 0);
135 do {
136 ctype = get_cache_type(&ct.ci[
137 if (ctype == CACHE_TYPE_NOCACH
138 break;
139 /* Separate instruction and da
140 leaves += (ctype == CACHE_TYPE
141 } while (++level < CACHE_MAX_LEVEL);
142 this_cpu_ci->num_levels = level;
143 this_cpu_ci->num_leaves = leaves;
144 return 0;
145 }
146
147 int populate_cache_leaves(unsigned int cpu)
148 {
149 struct cpu_cacheinfo *this_cpu_ci = ge
150 struct cacheinfo *this_leaf = this_cpu
151 unsigned int level, idx, pvt;
152 union cache_topology ct;
153 enum cache_type ctype;
154
155 ct.raw = ecag(EXTRACT_TOPOLOGY, 0, 0);
156 for (idx = 0, level = 0; level < this_
157 idx < this_cpu_ci->num_leaves; id
158 if (!this_leaf)
159 return -EINVAL;
160 pvt = (ct.ci[level].scope == C
161 ctype = get_cache_type(&ct.ci[
162 if (ctype == CACHE_TYPE_SEPARA
163 ci_leaf_init(this_leaf
164 ci_leaf_init(this_leaf
165 } else {
166 ci_leaf_init(this_leaf
167 }
168 }
169 this_cpu_ci->cpu_map_populated = true;
170 return 0;
171 }
172
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