1 /*
2 * This file is subject to the terms and condi
3 * License. See the file "COPYING" in the mai
4 * for more details.
5 *
6 * arch/shmedia/boot/compressed/head.S
7 *
8 * Copied from
9 * arch/shmedia/kernel/head.S
10 * which carried the copyright:
11 * Copyright (C) 2000, 2001 Paolo Alberelli
12 *
13 * Modification for compressed loader:
14 * Copyright (C) 2002 Stuart Menefy (stuart.
15 */
16 #include <asm/cache.h>
17 #include <asm/tlb.h>
18 #include <cpu/mmu_context.h>
19 #include <cpu/registers.h>
20
21 /*
22 * Fixed TLB entries to identity map the begin
23 */
24 #define MMUIR_TEXT_H 0x0000000000000003 | C
25 /* Enabled, Shared, AS
26 #define MMUIR_TEXT_L 0x000000000000009a | C
27 /* 512 Mb, Cacheable (
28
29 #define MMUDR_CACHED_H 0x0000000000000003 | C
30 /* Enabled, Shared, AS
31 #define MMUDR_CACHED_L 0x000000000000015a | C
32 /* 512 Mb, Cacheable (
33
34 #define ICCR0_INIT_VAL ICCR0_ON | ICCR0_ICI
35 #define ICCR1_INIT_VAL ICCR1_NOLOCK
36
37 #define OCCR0_INIT_VAL OCCR0_ON | OCCR0_OCI |
38 #define OCCR1_INIT_VAL OCCR1_NOLOCK
39
40 .text
41
42 .global startup
43 startup:
44 /*
45 * Prevent speculative fetch on device
46 * uninitialized target registers.
47 * This must be executed before the fi
48 */
49 ptabs/u r63, tr0
50 ptabs/u r63, tr1
51 ptabs/u r63, tr2
52 ptabs/u r63, tr3
53 ptabs/u r63, tr4
54 ptabs/u r63, tr5
55 ptabs/u r63, tr6
56 ptabs/u r63, tr7
57 synci
58
59 /*
60 * Set initial TLB entries for cached
61 * Note: PTA/BLINK is PIC code, PTABS/
62 */
63 /* Clear ITLBs */
64 pta 1f, tr1
65 movi ITLB_FIXED, r21
66 movi ITLB_LAST_VAR_UNRESTRICTED+TLB
67 1: putcfg r21, 0, r63 /* Cle
68 addi r21, TLB_STEP, r21
69 bne r21, r22, tr1
70
71 /* Clear DTLBs */
72 pta 1f, tr1
73 movi DTLB_FIXED, r21
74 movi DTLB_LAST_VAR_UNRESTRICTED+TLB
75 1: putcfg r21, 0, r63 /* Cle
76 addi r21, TLB_STEP, r21
77 bne r21, r22, tr1
78
79 /* Map one big (512Mb) page for ITLB *
80 movi ITLB_FIXED, r21
81 movi MMUIR_TEXT_L, r22 /* PTE
82 putcfg r21, 1, r22 /* Set
83 movi MMUIR_TEXT_H, r22 /* PTE
84 putcfg r21, 0, r22 /* Set
85
86 /* Map one big CACHED (512Mb) page for
87 movi DTLB_FIXED, r21
88 movi MMUDR_CACHED_L, r22 /* PTE
89 putcfg r21, 1, r22 /* Set
90 movi MMUDR_CACHED_H, r22 /* PTE
91 putcfg r21, 0, r22 /* Set
92
93 /* ICache */
94 movi ICCR_BASE, r21
95 movi ICCR0_INIT_VAL, r22
96 movi ICCR1_INIT_VAL, r23
97 putcfg r21, ICCR_REG0, r22
98 putcfg r21, ICCR_REG1, r23
99 synci
100
101 /* OCache */
102 movi OCCR_BASE, r21
103 movi OCCR0_INIT_VAL, r22
104 movi OCCR1_INIT_VAL, r23
105 putcfg r21, OCCR_REG0, r22
106 putcfg r21, OCCR_REG1, r23
107 synco
108
109 /*
110 * Enable the MMU.
111 * From here-on code can be non-PIC.
112 */
113 movi SR_HARMLESS | SR_ENABLE_MMU, r
114 putcon r22, SSR
115 movi 1f, r22
116 putcon r22, SPC
117 synco
118 rte /* And
119 1: /* ...
120
121 /* Set initial stack pointer */
122 movi datalabel stack_start, r0
123 ld.l r0, 0, r15
124
125 /*
126 * Clear bss
127 */
128 pt 1f, tr1
129 movi datalabel __bss_start, r22
130 movi datalabel _end, r23
131 1: st.l r22, 0, r63
132 addi r22, 4, r22
133 bne r22, r23, tr1
134
135 /*
136 * Decompress the kernel.
137 */
138 pt decompress_kernel, tr0
139 blink tr0, r18
140
141 /*
142 * Disable the MMU.
143 */
144 movi SR_HARMLESS, r22
145 putcon r22, SSR
146 movi 1f, r22
147 putcon r22, SPC
148 synco
149 rte /* And
150 1: /* ...
151
152 /* Jump into the decompressed kernel *
153 movi datalabel (CONFIG_MEMORY_START
154 ptabs r19, tr0
155 blink tr0, r18
156
157 /* Shouldn't return here, but just in
158 pt 1f, tr0
159 1: blink tr0, r63
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