1 // SPDX-License-Identifier: GPL-2.0 1
2 #include <linux/kernel.h>
3 #include <linux/types.h>
4 #include <linux/init.h>
5 #include <linux/delay.h>
6 #include <linux/pci.h>
7 #include <linux/io.h>
8 #include <linux/sh_intc.h>
9 #include "pci-sh4.h"
10
11 int pcibios_map_platform_irq(const struct pci_
12 {
13 switch (slot) {
14 case 0: return evt2irq(0x3a0);
15 case 1: return evt2irq(0x3a0); /* AMD
16 case 2: return -1;
17 case 3: return -1;
18 case 4: return -1;
19 default:
20 printk("PCI: Bad IRQ mapping r
21 return -1;
22 }
23 }
24
25 #define PCIMCR_MRSET_OFF 0xBFFFFFFF
26 #define PCIMCR_RFSH_OFF 0xFFFFFFFB
27
28 /*
29 * Only long word accesses of the PCIC's inter
30 * configuration registers from the CPU is sup
31 */
32 #define PCIC_WRITE(x,v) writel((v), PCI_REG(x)
33 #define PCIC_READ(x) readl(PCI_REG(x))
34
35 /*
36 * Description: This function sets up and ini
37 * up the BARS, maps the DRAM into the address
38 */
39 int pci_fixup_pcic(struct pci_channel *chan)
40 {
41 unsigned long bcr1, wcr1, wcr2, wcr3,
42 unsigned short bcr2;
43
44 /*
45 * Initialize the slave bus controller
46 * here should not be hardcoded, but th
47 * on the processor, to make this funct
48 * (i.e. Another sbc may usr different
49 * for the pcic to work, its settings n
50 */
51 bcr1 = (*(volatile unsigned long*)(SH7
52 bcr2 = (*(volatile unsigned short*)(SH
53 wcr1 = (*(volatile unsigned long*)(SH7
54 wcr2 = (*(volatile unsigned long*)(SH7
55 wcr3 = (*(volatile unsigned long*)(SH7
56 mcr = (*(volatile unsigned long*)(SH77
57
58 bcr1 = bcr1 | 0x00080000; /* Enable B
59 (*(volatile unsigned long*)(SH7751_BCR
60
61 bcr1 = bcr1 | 0x40080000; /* Enable B
62 PCIC_WRITE(SH7751_PCIBCR1, bcr1);
63 PCIC_WRITE(SH7751_PCIBCR2, bcr2);
64 PCIC_WRITE(SH7751_PCIWCR1, wcr1);
65 PCIC_WRITE(SH7751_PCIWCR2, wcr2);
66 PCIC_WRITE(SH7751_PCIWCR3, wcr3);
67 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMC
68 PCIC_WRITE(SH7751_PCIMCR, mcr); /
69
70
71 /* Enable all interrupts, so we know w
72 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff)
73 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f
74
75 /* Set up standard PCI config register
76 PCIC_WRITE(SH7751_PCICONF1, 0xF390
77 PCIC_WRITE(SH7751_PCICONF2, 0x0000
78 PCIC_WRITE(SH7751_PCICONF4, 0xab00
79 PCIC_WRITE(SH7751_PCICONF5, 0x0c00
80 PCIC_WRITE(SH7751_PCICONF6, 0xd000
81 PCIC_WRITE(SH7751_PCICONF11, 0x3505105
82 PCIC_WRITE(SH7751_PCILSR0, 0x03f00000)
83 PCIC_WRITE(SH7751_PCILSR1, 0x00000000)
84 PCIC_WRITE(SH7751_PCILAR0, 0x0c000000)
85 PCIC_WRITE(SH7751_PCILAR1, 0x00000000)
86
87 /* Now turn it on... */
88 PCIC_WRITE(SH7751_PCICR, 0xa5000001);
89
90 /*
91 * Set PCIMBR and PCIIOBR here, assumin
92 * (16M MEM, 256K IO) is enough. If a
93 * needed, the readx/writex and inx/out
94 * have to do more (e.g. setting regist
95 */
96
97 /*
98 * Set the MBR so PCI address is one-to
99 * meaning all calls go straight throug
100 * catch erroneous assumption.
101 */
102 BUG_ON(chan->resources[1].start != SH7
103
104 PCIC_WRITE(SH7751_PCIMBR, chan->resour
105
106 /* Set IOBR for window containing area
107 PCIC_WRITE(SH7751_PCIIOBR, (chan->reso
108
109 /* All done, may as well say so... */
110 printk("SH7751 PCI: Finished initializ
111
112 return 1;
113 }
114
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