1 /* SPDX-License-Identifier: GPL-2.0 1 2 * 3 * Low-Level PCI Support for SH7751 targe 4 * 5 * Dustin McIntire (dustin@sensoria.com) (c) 6 * Paul Mundt (lethal@linux-sh.org) (c) 2003 7 */ 8 9 #ifndef _PCI_SH7751_H_ 10 #define _PCI_SH7751_H_ 11 12 /* Platform Specific Values */ 13 #define SH7751_VENDOR_ID 0x1054 14 #define SH7751_DEVICE_ID 0x3505 15 #define SH7751R_DEVICE_ID 0x350e 16 17 /* SH7751 Specific Values */ 18 #define SH7751_PCI_CONFIG_BASE 0xFD00000 19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 20 #define SH7751_PCI_MEMORY_BASE 0xFD00000 21 #define SH7751_PCI_MEM_SIZE 0x0100000 22 #define SH7751_PCI_IO_BASE 0xFE24000 23 #define SH7751_PCI_IO_SIZE 0x40000 24 25 #define SH7751_PCIREG_BASE 0xFE20000 26 27 #define SH7751_PCICONF0 0x0 28 #define SH7751_PCICONF0_DEVID 0xFFFF000 29 #define SH7751_PCICONF0_VNDID 0x0000FFF 30 #define SH7751_PCICONF1 0x4 31 #define SH7751_PCICONF1_DPE 0x8000000 32 #define SH7751_PCICONF1_SSE 0x4000000 33 #define SH7751_PCICONF1_RMA 0x2000000 34 #define SH7751_PCICONF1_RTA 0x1000000 35 #define SH7751_PCICONF1_STA 0x0800000 36 #define SH7751_PCICONF1_DEV 0x0600000 37 #define SH7751_PCICONF1_DPD 0x0100000 38 #define SH7751_PCICONF1_FBBC 0x0080000 39 #define SH7751_PCICONF1_UDF 0x0040000 40 #define SH7751_PCICONF1_66M 0x0020000 41 #define SH7751_PCICONF1_PM 0x0010000 42 #define SH7751_PCICONF1_PBBE 0x0000020 43 #define SH7751_PCICONF1_SER 0x0000010 44 #define SH7751_PCICONF1_WCC 0x0000008 45 #define SH7751_PCICONF1_PER 0x0000004 46 #define SH7751_PCICONF1_VPS 0x0000002 47 #define SH7751_PCICONF1_MWIE 0x0000001 48 #define SH7751_PCICONF1_SPC 0x0000000 49 #define SH7751_PCICONF1_BUM 0x0000000 50 #define SH7751_PCICONF1_MES 0x0000000 51 #define SH7751_PCICONF1_IOS 0x0000000 52 #define SH7751_PCICONF2 0x8 53 #define SH7751_PCICONF2_BCC 0xFF00000 54 #define SH7751_PCICONF2_SCC 0x00FF000 55 #define SH7751_PCICONF2_RLPI 0x0000FF0 56 #define SH7751_PCICONF2_REV 0x000000F 57 #define SH7751_PCICONF3 0xC 58 #define SH7751_PCICONF3_BIST7 0x8000000 59 #define SH7751_PCICONF3_BIST6 0x4000000 60 #define SH7751_PCICONF3_BIST3_0 0x0F00000 61 #define SH7751_PCICONF3_HD7 0x0080000 62 #define SH7751_PCICONF3_HD6_0 0x007F000 63 #define SH7751_PCICONF3_LAT 0x0000FF0 64 #define SH7751_PCICONF3_CLS 0x000000F 65 #define SH7751_PCICONF4 0x10 66 #define SH7751_PCICONF4_BASE 0xFFFFFFF 67 #define SH7751_PCICONF4_ASI 0x0000000 68 #define SH7751_PCICONF5 0x14 69 #define SH7751_PCICONF5_BASE 0xFFFFFFF 70 #define SH7751_PCICONF5_LAP 0x0000000 71 #define SH7751_PCICONF5_LAT 0x0000000 72 #define SH7751_PCICONF5_ASI 0x0000000 73 #define SH7751_PCICONF6 0x18 74 #define SH7751_PCICONF6_BASE 0xFFFFFFF 75 #define SH7751_PCICONF6_LAP 0x0000000 76 #define SH7751_PCICONF6_LAT 0x0000000 77 #define SH7751_PCICONF6_ASI 0x0000000 78 /* PCICONF7 - PCICONF10 are undefined */ 79 #define SH7751_PCICONF11 0x2C 80 #define SH7751_PCICONF11_SSID 0xFFFF000 81 #define SH7751_PCICONF11_SVID 0x0000FFF 82 /* PCICONF12 is undefined */ 83 #define SH7751_PCICONF13 0x34 84 #define SH7751_PCICONF13_CPTR 0x000000F 85 /* PCICONF14 is undefined */ 86 #define SH7751_PCICONF15 0x3C 87 #define SH7751_PCICONF15_IPIN 0x000000F 88 #define SH7751_PCICONF16 0x40 89 #define SH7751_PCICONF16_PMES 0xF800000 90 #define SH7751_PCICONF16_D2S 0x0400000 91 #define SH7751_PCICONF16_D1S 0x0200000 92 #define SH7751_PCICONF16_DSI 0x0020000 93 #define SH7751_PCICONF16_PMCK 0x0008000 94 #define SH7751_PCICONF16_VER 0x0007000 95 #define SH7751_PCICONF16_NIP 0x0000FF0 96 #define SH7751_PCICONF16_CID 0x000000F 97 #define SH7751_PCICONF17 0x44 98 #define SH7751_PCICONF17_DATA 0xFF00000 99 #define SH7751_PCICONF17_PMES 0x0080000 100 #define SH7751_PCICONF17_DSCL 0x0060000 101 #define SH7751_PCICONF17_DSEL 0x001E000 102 #define SH7751_PCICONF17_PMEN 0x0001000 103 #define SH7751_PCICONF17_PWST 0x0000000 104 /* SH7715 Internal PCI Registers */ 105 106 /* Memory Control Registers */ 107 #define SH7751_BCR1 0xFF800000 108 #define SH7751_BCR2 0xFF800004 109 #define SH7751_BCR3 0xFF800050 110 #define SH7751_BCR4 0xFE0A00F0 111 #define SH7751_WCR1 0xFF800008 112 #define SH7751_WCR2 0xFF80000C 113 #define SH7751_WCR3 0xFF800010 114 #define SH7751_MCR 0xFF800014 115 116 /* General Memory Config Addresses */ 117 #define SH7751_CS0_BASE_ADDR 0x0 118 #define SH7751_MEM_REGION_SIZE 0x04000000 119 #define SH7751_CS1_BASE_ADDR (SH7751_CS0 120 #define SH7751_CS2_BASE_ADDR (SH7751_CS1 121 #define SH7751_CS3_BASE_ADDR (SH7751_CS2 122 #define SH7751_CS4_BASE_ADDR (SH7751_CS3 123 #define SH7751_CS5_BASE_ADDR (SH7751_CS4 124 #define SH7751_CS6_BASE_ADDR (SH7751_CS5 125 126 #endif /* _PCI_SH7751_H_ */ 127
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