1 /* SPDX-License-Identifier: GPL-2.0 1
2 *
3 * SH7786 PCI-Express controller definitions.
4 *
5 * Copyright (C) 2008, 2009 Renesas Technology
6 * All rights reserved.
7 */
8 #ifndef __PCI_SH7786_H
9 #define __PCI_SH7786_H
10
11 /* PCIe bus-0(x4) on SH7786 */
12 #define SH4A_PCIE_SPW_BASE 0xFE000000
13 #define SH4A_PCIE_SPW_BASE1 0xFE200000
14 #define SH4A_PCIE_SPW_BASE2 0xFCC00000
15 #define SH4A_PCIE_SPW_BASE_LEN 0x00080000
16
17 #define SH4A_PCI_CNFG_BASE 0xFE040000
18 #define SH4A_PCI_CNFG_BASE1 0xFE240000
19 #define SH4A_PCI_CNFG_BASE2 0xFCC40000
20 #define SH4A_PCI_CNFG_BASE_LEN 0x00040000
21
22 #define SH4A_PCIPIO_ADDR_OFFSET 0x000001c0
23 #define SH4A_PCIPIO_DATA_OFFSET 0x00000220
24
25 /*
26 * for PEX8111(Max Payload Size=128B,PCIIO_SIZ
27 * for other(Max Payload Size=4096B,PCIIO_SIZE
28 */
29
30 /* PCI0: PCI memory target transfer 32-bit add
31 #define SH4A_PCIBMSTR_TRANSLATION 0x2000
32
33 /* SPVCR0 */
34 #define SH4A_PCIEVCR0 (0x000000)
35 #define BITS_TOP_MB (24)
36 #define MASK_TOP_MB (0xff<<BITS_TO
37 #define BITS_BOT_MB (16)
38 #define MASK_BOT_MB (0xff<<BITS_BO
39 #define BITS_VC_ID (0)
40 #define MASK_VC_ID (0xffff<<BITS_
41
42 /* SPVCR1 */
43 #define SH4A_PCIEVCR1 (0x000004)
44 #define BITS_BADOPC (5)
45 #define MASK_BADOPC (1<<BITS_BADOP
46 #define BITS_BADDEST (4)
47 #define MASK_BADDEST (1<<BITS_BADDE
48 #define BITS_UNSOLRESP (3)
49 #define MASK_UNSOLRESP (1<<BITS_UNSOL
50 #define BITS_ERRSNT (1)
51 #define MASK_ERRSNT (1<<BITS_ERRSN
52 #define BITS_ERRRCV (0)
53 #define MASK_ERRRCV (1<<BITS_ERRRC
54
55 /* PCIEENBLR */
56 #define SH4A_PCIEENBLR (0x000008)
57
58 /* PCIEECR */
59 #define SH4A_PCIEECR (0x00000C)
60 #define BITS_ENBL (0) /* 0 E
61 #define MASK_ENBL (1<<BITS_ENBL)
62
63 /* PCIEPAR */
64 #define SH4A_PCIEPAR (0x000010)
65 #define BITS_BN (24)
66 #define MASK_BN (0xff<<BITS_BN
67 #define BITS_DN (19)
68 #define MASK_DN (0x1f<<BITS_DN
69 #define BITS_FN (16)
70 #define MASK_FN (0x7<<BITS_FN)
71 #define BITS_EREGNO (8)
72 #define MASK_EREGNO (0xff<<BITS_ER
73 #define BITS_REGNO (2)
74 #define MASK_REGNO (0x3f<<BITS_RE
75
76 /* PCIEPCTLR */
77 #define SH4A_PCIEPCTLR (0x000018)
78 #define BITS_CCIE (31) /* 31
79 #define MASK_CCIE (1<<BITS_CCIE)
80 #define BITS_TYPE (8)
81 #define MASK_TYPE (1<<BITS_TYPE)
82 #define BITS_C_VC (0)
83 #define MASK_C_VC (1<<BITS_C_VC)
84
85 /* PCIEPDR */
86 #define SH4A_PCIEPDR (0x000020)
87 #define BITS_PDR (0)
88 #define MASK_PDR (0xffffffff<<B
89
90 /* PCIEMSGALR */
91 #define SH4A_PCIEMSGALR (0x000030)
92 #define BITS_MSGADRL (0)
93 #define MASK_MSGADRL (0xffffffff<<B
94
95 /* PCIEMSGAHR */
96 #define SH4A_PCIEMSGAHR (0x000034)
97 #define BITS_MSGADRH (0)
98 #define MASK_MSGADRH (0xffffffff<<B
99
100 /* PCIEMSGCTLR */
101 #define SH4A_PCIEMSGCTLR (0x000038)
102 #define BITS_MSGIE (31)
103 #define MASK_MSGIE (1<<BITS_MSGIE
104 #define BITS_MROUTE (16)
105 #define MASK_MROUTE (0x7<<BITS_MRO
106 #define BITS_MCODE (8)
107 #define MASK_MCODE (0xff<<BITS_MC
108 #define BITS_M_VC (0)
109 #define MASK_M_VC (1<<BITS_M_VC)
110
111 /* PCIEMSG */
112 #define SH4A_PCIEMSG (0x000040)
113 #define BITS_MDATA (0)
114 #define MASK_MDATA (0xffffffff<<B
115
116 /* PCIEUNLOCKCR */
117 #define SH4A_PCIEUNLOCKCR (0x000048)
118
119 /* PCIEIDR */
120 #define SH4A_PCIEIDR (0x000060)
121
122 /* PCIEDBGCTLR */
123 #define SH4A_PCIEDBGCTLR (0x000100)
124
125 /* PCIEINTXR */
126 #define SH4A_PCIEINTXR (0x004000)
127
128 /* PCIERMSGR */
129 #define SH4A_PCIERMSGR (0x004010)
130
131 /* PCIERSTR */
132 #define SH4A_PCIERSTR(x) (0x008000 + ((
133
134 /* PCIESRSTR */
135 #define SH4A_PCIESRSTR (0x008040)
136
137 /* PCIEPHYCTLR */
138 #define SH4A_PCIEPHYCTLR (0x010000)
139 #define BITS_CKE (0)
140 #define MASK_CKE (1<<BITS_CKE)
141
142 /* PCIERMSGIER */
143 #define SH4A_PCIERMSGIER (0x004040)
144
145 /* PCIEPHYADRR */
146 #define SH4A_PCIEPHYADRR (0x010004)
147 #define BITS_ACK (24)
148 #define MASK_ACK (1<<BITS_ACK)
149 #define BITS_CMD (16)
150 #define MASK_CMD (0x03<<BITS_CM
151 #define BITS_LANE (8)
152 #define MASK_LANE (0x0f<<BITS_LA
153 #define BITS_ADR (0)
154 #define MASK_ADR (0xff<<BITS_AD
155
156 /* PCIEPHYDINR */
157 #define SH4A_PCIEPHYDINR (0x010008)
158
159 /* PCIEPHYDOUTR */
160 #define SH4A_PCIEPHYDOUTR (0x01000C)
161
162 /* PCIEPHYSR */
163 #define SH4A_PCIEPHYSR (0x010010)
164
165 /* PCIEPHYDATAR */
166 #define SH4A_PCIEPHYDATAR (0x00008)
167 #define BITS_DATA (0)
168 #define MASK_DATA (0xffffffff<<B
169
170 /* PCIETCTLR */
171 #define SH4A_PCIETCTLR (0x020000)
172 #define BITS_CFINT (0)
173 #define MASK_CFINT (1<<BITS_CFINT
174
175 /* PCIETSTR */
176 #define SH4A_PCIETSTR (0x020004)
177
178 /* PCIEINTR */
179 #define SH4A_PCIEINTR (0x020008)
180 #define BITS_INT_RX_ERP
181 #define MASK_INT_RX_ERP
182 #define BITS_INT_RX_VCX_Posted
183 #define MASK_INT_RX_VCX_Posted
184 #define BITS_INT_RX_VCX_NonPosted
185 #define MASK_INT_RX_VCX_NonPosted
186 #define BITS_INT_RX_VCX_CPL
187 #define MASK_INT_RX_VCX_CPL
188 #define BITS_INT_TX_VCX_Posted
189 #define MASK_INT_TX_VCX_Posted
190 #define BITS_INT_TX_VCX_NonPosted
191 #define MASK_INT_TX_VCX_NonPosted
192 #define BITS_INT_TX_VCX_CPL
193 #define MASK_INT_TX_VCX_CPL
194 #define BITS_INT_RX_VC0_Posted
195 #define MASK_INT_RX_VC0_Posted
196 #define BITS_INT_RX_VC0_NonPosted
197 #define MASK_INT_RX_VC0_NonPosted
198 #define BITS_INT_RX_VC0_CPL
199 #define MASK_INT_RX_VC0_CPL
200 #define BITS_INT_TX_VC0_Posted
201 #define MASK_INT_TX_VC0_Posted
202 #define BITS_INT_TX_VC0_NonPosted
203 #define MASK_INT_TX_VC0_NonPosted
204 #define BITS_INT_TX_VC0_CPL
205 #define MASK_INT_TX_VC0_CPL
206 #define BITS_INT_RX_CTRL
207 #define MASK_INT_RX_CTRL
208 #define BITS_INT_TX_CTRL
209 #define MASK_INT_TX_CTRL
210 #define BITS_INTTL
211 #define MASK_INTTL
212 #define BITS_INTDL
213 #define MASK_INTDL
214 #define BITS_INTMAC
215 #define MASK_INTMAC
216 #define BITS_INTPM
217 #define MASK_INTPM
218
219 /* PCIEINTER */
220 #define SH4A_PCIEINTER (0x02000C)
221 #define BITS_INT_RX_ERP
222 #define MASK_INT_RX_ERP
223 #define BITS_INT_RX_VCX_Posted
224 #define MASK_INT_RX_VCX_Posted
225 #define BITS_INT_RX_VCX_NonPosted
226 #define MASK_INT_RX_VCX_NonPosted
227 #define BITS_INT_RX_VCX_CPL
228 #define MASK_INT_RX_VCX_CPL
229 #define BITS_INT_TX_VCX_Posted
230 #define MASK_INT_TX_VCX_Posted
231 #define BITS_INT_TX_VCX_NonPosted
232 #define MASK_INT_TX_VCX_NonPosted
233 #define BITS_INT_TX_VCX_CPL
234 #define MASK_INT_TX_VCX_CPL
235 #define BITS_INT_RX_VC0_Posted
236 #define MASK_INT_RX_VC0_Posted
237 #define BITS_INT_RX_VC0_NonPosted
238 #define MASK_INT_RX_VC0_NonPosted
239 #define BITS_INT_RX_VC0_CPL
240 #define MASK_INT_RX_VC0_CPL
241 #define BITS_INT_TX_VC0_Posted
242 #define MASK_INT_TX_VC0_Posted
243 #define BITS_INT_TX_VC0_NonPosted
244 #define MASK_INT_TX_VC0_NonPosted
245 #define BITS_INT_TX_VC0_CPL
246 #define MASK_INT_TX_VC0_CPL
247 #define BITS_INT_RX_CTRL
248 #define MASK_INT_RX_CTRL
249 #define BITS_INT_TX_CTRL
250 #define MASK_INT_TX_CTRL
251 #define BITS_INTTL
252 #define MASK_INTTL
253 #define BITS_INTDL
254 #define MASK_INTDL
255 #define BITS_INTMAC
256 #define MASK_INTMAC
257 #define BITS_INTPM
258 #define MASK_INTPM
259
260 /* PCIEEH0R */
261 #define SH4A_PCIEEHR(x) (0x020010 + ((
262
263 /* PCIEAIR */
264 #define SH4A_PCIEAIR (SH4A_PCIE_BAS
265
266 /* PCIECIR */
267 #define SH4A_PCIECIR (SH4A_PCIE_BAS
268
269 /* PCIEERRFR */
270 #define SH4A_PCIEERRFR (0x020020)
271
272 /* PCIEERRFER */
273 #define SH4A_PCIEERRFER (0x020024)
274
275 /* PCIEERRFR2 */
276 #define SH4A_PCIEERRFR2 (0x020028)
277
278 /* PCIEMSIR */
279 #define SH4A_PCIEMSIR (0x020040)
280
281 /* PCIEMSIFR */
282 #define SH4A_PCIEMSIFR (0x020044)
283
284 /* PCIEPWRCTLR */
285 #define SH4A_PCIEPWRCTLR (0x020100)
286
287 /* PCIEPCCTLR */
288 #define SH4A_PCIEPCCTLR (0x020180)
289
290
291 /* PCIELAR0 */
292 #define SH4A_PCIELAR0 (0x020200)
293 #define BITS_LARn (20)
294 #define MASK_LARn (0xfff<<BITS_L
295
296 #define SH4A_PCIE_020204 (0x020204)
297
298 /* PCIELAMR0 */
299 #define SH4A_PCIELAMR0 (0x020208)
300 #define BITS_LAMRn (20)
301 #define MASK_LAMRn (0x1ff<<BITS_L
302 #define BITS_LAREn (0)
303 #define MASK_LAREn (0x1<<BITS_LAR
304
305 /* PCIECSCR0 */
306 #define SH4A_PCIECSCR0 (0x020210)
307 #define BITS_RANGE (2)
308 #define MASK_RANGE (0x7<<BITS_RAN
309 #define BITS_SNPMD (0)
310 #define MASK_SNPMD (0x3<<BITS_SNP
311
312 /* PCIECSAR0 */
313 #define SH4A_PCIECSAR0 (0x020214)
314 #define BITS_CSADR (0)
315 #define MASK_CSADR (0xffffffff<<B
316
317 /* PCIESTCTLR0 */
318 #define SH4A_PCIESTCTLR0 (0x020218)
319 #define BITS_SHPRI (8)
320 #define MASK_SHPRI (0x0f<<BITS_SH
321
322 #define SH4A_PCIE_020224 (0x020224)
323
324 #define SH4A_PCIELAR1 (0x020220)
325 #define SH4A_PCIELAMR1 (0x020228)
326 #define SH4A_PCIECSCR1 (0x020230)
327 #define SH4A_PCIECSAR1 (0x020234)
328 #define SH4A_PCIESTCTLR1 (0x020238)
329
330 #define SH4A_PCIELAR2 (0x020240)
331 #define SH4A_PCIE_020244 (0x020244)
332 #define SH4A_PCIELAMR2 (0x020248)
333 #define SH4A_PCIECSCR2 (0x020250)
334 #define SH4A_PCIECSAR2 (0x020254)
335 #define SH4A_PCIESTCTLR2 (0x020258)
336
337 #define SH4A_PCIELAR3 (0x020260)
338 #define SH4A_PCIE_020264 (0x020264)
339 #define SH4A_PCIELAMR3 (0x020268)
340 #define SH4A_PCIECSCR3 (0x020270)
341 #define SH4A_PCIECSAR3 (0x020274)
342 #define SH4A_PCIESTCTLR3 (0x020278)
343
344 #define SH4A_PCIELAR4 (0x020280)
345 #define SH4A_PCIE_020284 (0x020284)
346 #define SH4A_PCIELAMR4 (0x020288)
347 #define SH4A_PCIECSCR4 (0x020290)
348 #define SH4A_PCIECSAR4 (0x020294)
349 #define SH4A_PCIESTCTLR4 (0x020298)
350
351 #define SH4A_PCIELAR5 (0x0202A0)
352 #define SH4A_PCIE_0202A4 (0x0202A4)
353 #define SH4A_PCIELAMR5 (0x0202A8)
354 #define SH4A_PCIECSCR5 (0x0202B0)
355 #define SH4A_PCIECSAR5 (0x0202B4)
356 #define SH4A_PCIESTCTLR5 (0x0202B8)
357
358 /* PCIEPARL */
359 #define SH4A_PCIEPARL(x) (0x020400 + ((
360 #define BITS_PAL (18)
361 #define MASK_PAL (0x3fff<<BITS_
362
363 /* PCIEPARH */
364 #define SH4A_PCIEPARH(x) (0x020404 + ((
365 #define BITS_PAH (0)
366 #define MASK_PAH (0xffffffff<<B
367
368 /* PCIEPAMR */
369 #define SH4A_PCIEPAMR(x) (0x020408 + ((
370 #define BITS_PAM (18)
371 #define MASK_PAM (0x3fff<<BITS_
372
373 /* PCIEPTCTLR */
374 #define SH4A_PCIEPTCTLR(x) (0x02040C + ((
375 #define BITS_PARE (31)
376 #define MASK_PARE (0x1<<BITS_PAR
377 #define BITS_TC (20)
378 #define MASK_TC (0x7<<BITS_TC)
379 #define BITS_T_VC (16)
380 #define MASK_T_VC (0x1<<BITS_T_V
381 #define BITS_LOCK (12)
382 #define MASK_LOCK (0x1<<BITS_LOC
383 #define BITS_SPC (8)
384 #define MASK_SPC (0x1<<BITS_SPC
385
386 #define SH4A_PCIEDMAOR (0x021000)
387 #define SH4A_PCIEDMSAR0 (0x021100)
388 #define SH4A_PCIEDMSAHR0 (0x021104)
389 #define SH4A_PCIEDMDAR0 (0x021108)
390 #define SH4A_PCIEDMDAHR0 (0x02110C)
391 #define SH4A_PCIEDMBCNTR0 (0x021110)
392 #define SH4A_PCIEDMSBCNTR0 (0x021114)
393 #define SH4A_PCIEDMSTRR0 (0x021118)
394 #define SH4A_PCIEDMCCAR0 (0x02111C)
395 #define SH4A_PCIEDMCCR0 (0x021120)
396 #define SH4A_PCIEDMCC2R0 (0x021124)
397 #define SH4A_PCIEDMCCCR0 (0x021128)
398 #define SH4A_PCIEDMCHSR0 (0x02112C)
399 #define SH4A_PCIEDMSAR1 (0x021140)
400 #define SH4A_PCIEDMSAHR1 (0x021144)
401 #define SH4A_PCIEDMDAR1 (0x021148)
402 #define SH4A_PCIEDMDAHR1 (0x02114C)
403 #define SH4A_PCIEDMBCNTR1 (0x021150)
404 #define SH4A_PCIEDMSBCNTR1 (0x021154)
405 #define SH4A_PCIEDMSTRR1 (0x021158)
406 #define SH4A_PCIEDMCCAR1 (0x02115C)
407 #define SH4A_PCIEDMCCR1 (0x021160)
408 #define SH4A_PCIEDMCC2R1 (0x021164)
409 #define SH4A_PCIEDMCCCR1 (0x021168)
410 #define SH4A_PCIEDMCHSR1 (0x02116C)
411 #define SH4A_PCIEDMSAR2 (0x021180)
412 #define SH4A_PCIEDMSAHR2 (0x021184)
413 #define SH4A_PCIEDMDAR2 (0x021188)
414 #define SH4A_PCIEDMDAHR2 (0x02118C)
415 #define SH4A_PCIEDMBCNTR2 (0x021190)
416 #define SH4A_PCIEDMSBCNTR2 (0x021194)
417 #define SH4A_PCIEDMSTRR2 (0x021198)
418 #define SH4A_PCIEDMCCAR2 (0x02119C)
419 #define SH4A_PCIEDMCCR2 (0x0211A0)
420 #define SH4A_PCIEDMCC2R2 (0x0211A4)
421 #define SH4A_PCIEDMCCCR2 (0x0211A8)
422 #define SH4A_PCIEDMSAR3 (0x0211C0)
423 #define SH4A_PCIEDMSAHR3 (0x0211C4)
424 #define SH4A_PCIEDMDAR3 (0x0211C8)
425 #define SH4A_PCIEDMDAHR3 (0x0211CC)
426 #define SH4A_PCIEDMBCNTR3 (0x0211D0)
427 #define SH4A_PCIEDMSBCNTR3 (0x0211D4)
428 #define SH4A_PCIEDMSTRR3 (0x0211D8)
429 #define SH4A_PCIEDMCCAR3 (0x0211DC)
430 #define SH4A_PCIEDMCCR3 (0x0211E0)
431 #define SH4A_PCIEDMCC2R3 (0x0211E4)
432 #define SH4A_PCIEDMCCCR3 (0x0211E8)
433 #define SH4A_PCIEDMCHSR3 (0x0211EC)
434 #define SH4A_PCIEPCICONF0 (0x040000)
435 #define SH4A_PCIEPCICONF1 (0x040004)
436 #define SH4A_PCIEPCICONF2 (0x040008)
437 #define SH4A_PCIEPCICONF3 (0x04000C)
438 #define SH4A_PCIEPCICONF4 (0x040010)
439 #define SH4A_PCIEPCICONF5 (0x040014)
440 #define SH4A_PCIEPCICONF6 (0x040018)
441 #define SH4A_PCIEPCICONF7 (0x04001C)
442 #define SH4A_PCIEPCICONF8 (0x040020)
443 #define SH4A_PCIEPCICONF9 (0x040024)
444 #define SH4A_PCIEPCICONF10 (0x040028)
445 #define SH4A_PCIEPCICONF11 (0x04002C)
446 #define SH4A_PCIEPCICONF12 (0x040030)
447 #define SH4A_PCIEPCICONF13 (0x040034)
448 #define SH4A_PCIEPCICONF14 (0x040038)
449 #define SH4A_PCIEPCICONF15 (0x04003C)
450 #define SH4A_PCIEPMCAP0 (0x040040)
451 #define SH4A_PCIEPMCAP1 (0x040044)
452 #define SH4A_PCIEMSICAP0 (0x040050)
453 #define SH4A_PCIEMSICAP1 (0x040054)
454 #define SH4A_PCIEMSICAP2 (0x040058)
455 #define SH4A_PCIEMSICAP3 (0x04005C)
456 #define SH4A_PCIEMSICAP4 (0x040060)
457 #define SH4A_PCIEMSICAP5 (0x040064)
458 #define SH4A_PCIEEXPCAP0 (0x040070)
459 #define SH4A_PCIEEXPCAP1 (0x040074)
460 #define SH4A_PCIEEXPCAP2 (0x040078)
461 #define SH4A_PCIEEXPCAP3 (0x04007C)
462 #define SH4A_PCIEEXPCAP4 (0x040080)
463 #define SH4A_PCIEEXPCAP5 (0x040084)
464 #define SH4A_PCIEEXPCAP6 (0x040088)
465 #define SH4A_PCIEEXPCAP7 (0x04008C)
466 #define SH4A_PCIEEXPCAP8 (0x040090)
467 #define SH4A_PCIEVCCAP0 (0x040100)
468 #define SH4A_PCIEVCCAP1 (0x040104)
469 #define SH4A_PCIEVCCAP2 (0x040108)
470 #define SH4A_PCIEVCCAP3 (0x04010C)
471 #define SH4A_PCIEVCCAP4 (0x040110)
472 #define SH4A_PCIEVCCAP5 (0x040114)
473 #define SH4A_PCIEVCCAP6 (0x040118)
474 #define SH4A_PCIEVCCAP7 (0x04011C)
475 #define SH4A_PCIEVCCAP8 (0x040120)
476 #define SH4A_PCIEVCCAP9 (0x040124)
477 #define SH4A_PCIENUMCAP0 (0x0001B0)
478 #define SH4A_PCIENUMCAP1 (0x0001B4)
479 #define SH4A_PCIENUMCAP2 (0x0001B8)
480 #define SH4A_PCIEIDSETR0 (0x041000)
481 #define SH4A_PCIEIDSETR1 (0x041004)
482 #define SH4A_PCIEBAR0SETR (0x041008)
483 #define SH4A_PCIEBAR1SETR (0x04100C)
484 #define SH4A_PCIEBAR2SETR (0x041010)
485 #define SH4A_PCIEBAR3SETR (0x041014)
486 #define SH4A_PCIEBAR4SETR (0x041018)
487 #define SH4A_PCIEBAR5SETR (0x04101C)
488 #define SH4A_PCIECISSETR (0x041020)
489 #define SH4A_PCIEIDSETR2 (0x041024)
490 #define SH4A_PCIEEROMSETR (0x041028)
491 #define SH4A_PCIEDSERSETR0 (0x04102C)
492 #define SH4A_PCIEDSERSETR1 (0x041030)
493 #define SH4A_PCIECTLR (0x041040)
494 #define SH4A_PCIETLSR (0x041044)
495 #define SH4A_PCIETLCTLR (0x041048)
496 #define SH4A_PCIEDLSR (0x04104C)
497 #define SH4A_PCIEDLCTLR (0x041050)
498 #define SH4A_PCIEMACSR (0x041054)
499 #define SH4A_PCIEMACCTLR (0x041058)
500 #define PCIEMACCTLR_SCR_DIS (1 <<
501 #define SH4A_PCIEPMSTR (0x04105C)
502 #define SH4A_PCIEPMCTLR (0x041060)
503 #define SH4A_PCIETLINTENR (0x041064)
504 #define SH4A_PCIEDLINTENR (0x041068)
505 #define PCIEDLINTENR_DLL_ACT_ENABLE
506 #define SH4A_PCIEMACINTENR (0x04106C)
507 #define SH4A_PCIEPMINTENR (0x041070)
508 #define SH4A_PCIETXDCTLR (0x044000)
509 #define SH4A_PCIETXCTLR (0x044020)
510 #define SH4A_PCIETXSR (0x044028)
511 #define SH4A_PCIETXVC0DCTLR (0x044100)
512 #define SH4A_PCIETXVC0SR (0x044108)
513 #define SH4A_PCIEVC0PDTXR (0x044110)
514 #define SH4A_PCIEVC0PHTXR (0x044118)
515 #define SH4A_PCIEVC0NPDTXR (0x044120)
516 #define SH4A_PCIEVC0NPHTXR (0x044128)
517 #define SH4A_PCIEVC0CDTXR (0x044130)
518 #define SH4A_PCIEVC0CHTXR (0x044138)
519 #define SH4A_PCIETXVCXDCTLR (0x044200)
520 #define SH4A_PCIETXVCXSR (0x044208)
521 #define SH4A_PCIEVCXPDTXR (0x044210)
522 #define SH4A_PCIEVCXPHTXR (0x044218)
523 #define SH4A_PCIEVCXNPDTXR (0x044220)
524 #define SH4A_PCIEVCXNPHTXR (0x044228)
525 #define SH4A_PCIEVCXCDTXR (0x044230)
526 #define SH4A_PCIEVCXCHTXR (0x044238)
527 #define SH4A_PCIERDCTLR (0x046000)
528 #define SH4A_PCIEERPCTLR (0x046008)
529 #define SH4A_PCIEERPHR (0x046010)
530 #define SH4A_PCIEERPERR (0x046018)
531 #define SH4A_PCIERXVC0DCTLR (0x046100)
532 #define SH4A_PCIERXVC0SR (0x046108)
533 #define SH4A_PCIEVC0PDRXR (0x046140)
534 #define SH4A_PCIEVC0PHRXR (0x046148)
535 #define SH4A_PCIEVC0PERR (0x046150)
536 #define SH4A_PCIEVC0NPDRXR (0x046158)
537 #define SH4A_PCIEVC0NPHRXR (0x046160)
538 #define SH4A_PCIEVC0NPERR (0x046168)
539 #define SH4A_PCIEVC0CDRXR (0x046170)
540 #define SH4A_PCIEVC0CHRXR (0x046178)
541 #define SH4A_PCIEVC0CERR (0x046180)
542 #define SH4A_PCIERXVCXDCTLR (0x046200)
543 #define SH4A_PCIERXVCXSR (0x046208)
544 #define SH4A_PCIEVCXPDRXR (0x046240)
545 #define SH4A_PCIEVCXPHRXR (0x046248)
546 #define SH4A_PCIEVCXPERR (0x046250)
547 #define SH4A_PCIEVCXNPDRXR (0x046258)
548 #define SH4A_PCIEVCXNPHRXR (0x046260)
549 #define SH4A_PCIEVCXNPERR (0x046268)
550 #define SH4A_PCIEVCXCDRXR (0x046270)
551 #define SH4A_PCIEVCXCHRXR (0x046278)
552 #define SH4A_PCIEVCXCERR (0x046280)
553
554 /* SSI Register Definition for MSI WORK AROUND
555 #define SH4A_PCI_SSI_BASE 0xFFE00000
556 #define SH4A_PCI_SSI_BASE_LEN 0x00100000
557
558 #define SH4A_SSICR0 (0x000000)
559 #define SH4A_SSICR1 (0x010000)
560 #define SH4A_SSICR2 (0x020000)
561 #define SH4A_SSICR3 (0x030000)
562
563 #define PCI_REG(x) ((x) + 0x40000
564
565 static inline void
566 pci_write_reg(struct pci_channel *chan, unsign
567 {
568 __raw_writel(val, chan->reg_base + reg
569 }
570
571 static inline unsigned long
572 pci_read_reg(struct pci_channel *chan, unsigne
573 {
574 return __raw_readl(chan->reg_base + re
575 }
576
577 #endif /* __PCI_SH7786_H */
578
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.