1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 #ifndef __ASM_SH_HD64461 3 #define __ASM_SH_HD64461 4 /* 5 * Copyright (C) 2007 Kristoffer Ericson 6 * Copyright (C) 2004 Paul Mundt 7 * Copyright (C) 2000 YAEGASHI Takeshi 8 * 9 * Hitachi HD64461 companion chip 10 * (please note manual reference 0x100000 11 */ 12 13 /* Constants for PCMCIA mappings */ 14 #define HD64461_PCC_WINDOW 0x01000000 15 16 /* Area 6 - Slot 0 - memory and/or IO card */ 17 #define HD64461_IOBASE 0xb0000000 18 #define HD64461_IO_OFFSET(x) (HD64461_IOBAS 19 #define HD64461_PCC0_BASE HD64461_IO_OFF 20 #define HD64461_PCC0_ATTR (HD64461_PCC0_ 21 #define HD64461_PCC0_COMM (HD64461_PCC0_ 22 #define HD64461_PCC0_IO (HD64461_PCC0_ 23 24 /* Area 5 - Slot 1 - memory card only */ 25 #define HD64461_PCC1_BASE HD64461_IO_OFF 26 #define HD64461_PCC1_ATTR (HD64461_PCC1_ 27 #define HD64461_PCC1_COMM (HD64461_PCC1_ 28 29 /* Standby Control Register for HD64461 */ 30 #define HD64461_STBCR HD6446 31 #define HD64461_STBCR_CKIO_STBY 0x2000 32 #define HD64461_STBCR_SAFECKE_IST 0x1000 33 #define HD64461_STBCR_SLCKE_IST 0x0800 34 #define HD64461_STBCR_SAFECKE_OST 0x0400 35 #define HD64461_STBCR_SLCKE_OST 0x0200 36 #define HD64461_STBCR_SMIAST 0x0100 37 #define HD64461_STBCR_SLCDST 0x0080 38 #define HD64461_STBCR_SPC0ST 0x0040 39 #define HD64461_STBCR_SPC1ST 0x0020 40 #define HD64461_STBCR_SAFEST 0x0010 41 #define HD64461_STBCR_STM0ST 0x0008 42 #define HD64461_STBCR_STM1ST 0x0004 43 #define HD64461_STBCR_SIRST 0x0002 44 #define HD64461_STBCR_SURTST 0x0001 45 46 /* System Configuration Register */ 47 #define HD64461_SYSCR HD64461_IO_OFF 48 49 /* CPU Data Bus Control Register */ 50 #define HD64461_SCPUCR HD64461_IO_OFF 51 52 /* Base Address Register */ 53 #define HD64461_LCDCBAR HD64461_IO_OFF 54 55 /* Line increment address */ 56 #define HD64461_LCDCLOR HD64461_IO_OFF 57 58 /* Controls LCD controller */ 59 #define HD64461_LCDCCR HD64461_IO_OFF 60 61 /* LCCDR control bits */ 62 #define HD64461_LCDCCR_STBACK 0x0400 /* Sta 63 #define HD64461_LCDCCR_STREQ 0x0100 /* Sta 64 #define HD64461_LCDCCR_MOFF 0x0080 /* Mem 65 #define HD64461_LCDCCR_REFSEL 0x0040 /* Ref 66 #define HD64461_LCDCCR_EPON 0x0020 /* End 67 #define HD64461_LCDCCR_SPON 0x0010 /* Sta 68 69 /* Controls LCD (1) */ 70 #define HD64461_LDR1 HD64461_IO_OFF 71 #define HD64461_LDR1_DON 0x01 /* Dis 72 #define HD64461_LDR1_DINV 0x80 /* Dis 73 74 /* Controls LCD (2) */ 75 #define HD64461_LDR2 HD64461_IO_OFF 76 #define HD64461_LDHNCR HD64461_IO_OFF 77 #define HD64461_LDHNSR HD64461_IO_OFF 78 #define HD64461_LDVNTR HD64461_IO_OFF 79 #define HD64461_LDVNDR HD64461_IO_OFF 80 #define HD64461_LDVSPR HD64461_IO_OFF 81 82 /* Controls LCD (3) */ 83 #define HD64461_LDR3 HD64461_IO_OFF 84 85 /* Palette Registers */ 86 #define HD64461_CPTWAR HD64461_IO_OFF 87 #define HD64461_CPTWDR HD64461_IO_OFF 88 #define HD64461_CPTRAR HD64461_IO_OFF 89 #define HD64461_CPTRDR HD64461_IO_OFF 90 91 #define HD64461_GRDOR HD64461_IO_OFF 92 #define HD64461_GRSCR HD64461_IO_OFF 93 #define HD64461_GRCFGR HD64461_IO_OFF 94 95 #define HD64461_GRCFGR_ACCSTATUS 0x10 96 #define HD64461_GRCFGR_ACCRESET 0x08 97 #define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 98 #define HD64461_GRCFGR_ACCSTART_LINE 0x04 99 #define HD64461_GRCFGR_COLORDEPTH16 0x01 100 #define HD64461_GRCFGR_COLORDEPTH8 0x01 101 102 /* Line Drawing Registers */ 103 #define HD64461_LNSARH HD64461_IO_OFF 104 #define HD64461_LNSARL HD64461_IO_OFF 105 #define HD64461_LNAXLR HD64461_IO_OFF 106 #define HD64461_LNDGR HD64461_IO_OFF 107 #define HD64461_LNAXR HD64461_IO_OFF 108 #define HD64461_LNERTR HD64461_IO_OFF 109 #define HD64461_LNMDR HD64461_IO_OFF 110 111 /* BitBLT Registers */ 112 #define HD64461_BBTSSARH HD64461_IO_OFF 113 #define HD64461_BBTSSARL HD64461_IO_OFF 114 #define HD64461_BBTDSARH HD64461_IO_OFF 115 #define HD64461_BBTDSARL HD64461_IO_OFF 116 #define HD64461_BBTDWR HD64461_IO_OFF 117 #define HD64461_BBTDHR HD64461_IO_OFF 118 #define HD64461_BBTPARH HD64461_IO_OFF 119 #define HD64461_BBTPARL HD64461_IO_OFF 120 #define HD64461_BBTMARH HD64461_IO_OFF 121 #define HD64461_BBTMARL HD64461_IO_OFF 122 #define HD64461_BBTROPR HD64461_IO_OFF 123 #define HD64461_BBTMDR HD64461_IO_OFF 124 125 /* PC Card Controller Registers */ 126 /* Maps to Physical Area 6 */ 127 #define HD64461_PCC0ISR HD64461_IO_OFF 128 #define HD64461_PCC0GCR HD64461_IO_OFF 129 #define HD64461_PCC0CSCR HD64461_IO_OFF 130 #define HD64461_PCC0CSCIER HD64461_IO_OFF 131 #define HD64461_PCC0SCR HD64461_IO_OFF 132 /* Maps to Physical Area 5 */ 133 #define HD64461_PCC1ISR HD64461_IO_OFF 134 #define HD64461_PCC1GCR HD64461_IO_OFF 135 #define HD64461_PCC1CSCR HD64461_IO_OFF 136 #define HD64461_PCC1CSCIER HD64461_IO_OFF 137 #define HD64461_PCC1SCR HD64461_IO_OFF 138 139 /* PCC Interface Status Register */ 140 #define HD64461_PCCISR_READY 0x80 141 #define HD64461_PCCISR_MWP 0x40 142 #define HD64461_PCCISR_VS2 0x20 143 #define HD64461_PCCISR_VS1 0x10 144 #define HD64461_PCCISR_CD2 0x08 145 #define HD64461_PCCISR_CD1 0x04 146 #define HD64461_PCCISR_BVD2 0x02 147 #define HD64461_PCCISR_BVD1 0x01 148 149 #define HD64461_PCCISR_PCD_MASK 0x0c 150 #define HD64461_PCCISR_BVD_MASK 0x03 151 #define HD64461_PCCISR_BVD_BATGOOD 0x03 152 #define HD64461_PCCISR_BVD_BATWARN 0x01 153 #define HD64461_PCCISR_BVD_BATDEAD1 0x02 154 #define HD64461_PCCISR_BVD_BATDEAD2 0x00 155 156 /* PCC General Control Register */ 157 #define HD64461_PCCGCR_DRVE 0x80 158 #define HD64461_PCCGCR_PCCR 0x40 159 #define HD64461_PCCGCR_PCCT 0x20 160 #define HD64461_PCCGCR_VCC0 0x10 161 #define HD64461_PCCGCR_PMMOD 0x08 162 #define HD64461_PCCGCR_PA25 0x04 163 #define HD64461_PCCGCR_PA24 0x02 164 #define HD64461_PCCGCR_REG 0x01 165 166 /* PCC Card Status Change Register */ 167 #define HD64461_PCCCSCR_SCDI 0x80 168 #define HD64461_PCCCSCR_SRV1 0x40 169 #define HD64461_PCCCSCR_IREQ 0x20 170 #define HD64461_PCCCSCR_SC 0x10 171 #define HD64461_PCCCSCR_CDC 0x08 172 #define HD64461_PCCCSCR_RC 0x04 173 #define HD64461_PCCCSCR_BW 0x02 174 #define HD64461_PCCCSCR_BD 0x01 175 176 /* PCC Card Status Change Interrupt Enable Reg 177 #define HD64461_PCCCSCIER_CRE 0x80 178 #define HD64461_PCCCSCIER_IREQE_MASK 0x60 179 #define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 180 #define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 181 #define HD64461_PCCCSCIER_IREQE_FALLING 0x40 182 #define HD64461_PCCCSCIER_IREQE_RISING 0x60 183 184 #define HD64461_PCCCSCIER_SCE 0x10 185 #define HD64461_PCCCSCIER_CDE 0x08 186 #define HD64461_PCCCSCIER_RE 0x04 187 #define HD64461_PCCCSCIER_BWE 0x02 188 #define HD64461_PCCCSCIER_BDE 0x01 189 190 /* PCC Software Control Register */ 191 #define HD64461_PCCSCR_VCC1 0x02 192 #define HD64461_PCCSCR_SWP 0x01 193 194 /* PCC0 Output Pins Control Register */ 195 #define HD64461_P0OCR HD64461_IO_OFF 196 197 /* PCC1 Output Pins Control Register */ 198 #define HD64461_P1OCR HD64461_IO_OFF 199 200 /* PC Card General Control Register */ 201 #define HD64461_PGCR HD64461_IO_OFF 202 203 /* Port Control Registers */ 204 #define HD64461_GPACR HD64461_IO_OFF 205 #define HD64461_GPBCR HD64461_IO_OFF 206 #define HD64461_GPCCR HD64461_IO_OFF 207 #define HD64461_GPDCR HD64461_IO_OFF 208 209 /* Port Control Data Registers */ 210 #define HD64461_GPADR HD64461_IO_OFF 211 #define HD64461_GPBDR HD64461_IO_OFF 212 #define HD64461_GPCDR HD64461_IO_OFF 213 #define HD64461_GPDDR HD64461_IO_OFF 214 215 /* Interrupt Control Registers */ 216 #define HD64461_GPAICR HD64461_IO_OFF 217 #define HD64461_GPBICR HD64461_IO_OFF 218 #define HD64461_GPCICR HD64461_IO_OFF 219 #define HD64461_GPDICR HD64461_IO_OFF 220 221 /* Interrupt Status Registers */ 222 #define HD64461_GPAISR HD64461_IO_OFF 223 #define HD64461_GPBISR HD64461_IO_OFF 224 #define HD64461_GPCISR HD64461_IO_OFF 225 #define HD64461_GPDISR HD64461_IO_OFF 226 227 /* Interrupt Request Register & Interrupt Mask 228 #define HD64461_NIRR HD64461_IO_OFF 229 #define HD64461_NIMR HD64461_IO_OFF 230 231 #define HD64461_IRQBASE OFFCHIP_IRQ_BA 232 #define OFFCHIP_IRQ_BASE (64 + 16) 233 #define HD64461_IRQ_NUM 16 234 235 #define HD64461_IRQ_UART (HD64461_IRQBA 236 #define HD64461_IRQ_IRDA (HD64461_IRQBA 237 #define HD64461_IRQ_TMU1 (HD64461_IRQBA 238 #define HD64461_IRQ_TMU0 (HD64461_IRQBA 239 #define HD64461_IRQ_GPIO (HD64461_IRQBA 240 #define HD64461_IRQ_AFE (HD64461_IRQBA 241 #define HD64461_IRQ_PCC1 (HD64461_IRQBA 242 #define HD64461_IRQ_PCC0 (HD64461_IRQBA 243 244 #define __IO_PREFIX hd64461 245 #include <asm/io_generic.h> 246 247 /* arch/sh/cchips/hd6446x/hd64461/setup.c */ 248 void hd64461_register_irq_demux(int irq, 249 int (*demux) ( 250 void hd64461_unregister_irq_demux(int irq); 251 252 #endif 253
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