1 /* SPDX-License-Identifier: GPL-2.0 1
2 *
3 * include/asm-sh/spinlock-cas.h
4 *
5 * Copyright (C) 2015 SEI
6 */
7 #ifndef __ASM_SH_SPINLOCK_CAS_H
8 #define __ASM_SH_SPINLOCK_CAS_H
9
10 #include <asm/barrier.h>
11 #include <asm/processor.h>
12
13 static inline unsigned __sl_cas(volatile unsig
14 {
15 __asm__ __volatile__("cas.l %1,%0,@r0"
16 : "+r"(new)
17 : "r"(old), "z"(p)
18 : "t", "memory" );
19 return new;
20 }
21
22 /*
23 * Your basic SMP spinlocks, allowing only a s
24 */
25
26 #define arch_spin_is_locked(x) ((x)->
27
28 static inline void arch_spin_lock(arch_spinloc
29 {
30 while (!__sl_cas(&lock->lock, 1, 0));
31 }
32
33 static inline void arch_spin_unlock(arch_spinl
34 {
35 __sl_cas(&lock->lock, 0, 1);
36 }
37
38 static inline int arch_spin_trylock(arch_spinl
39 {
40 return __sl_cas(&lock->lock, 1, 0);
41 }
42
43 /*
44 * Read-write spinlocks, allowing multiple rea
45 *
46 * NOTE! it is quite common to have readers in
47 * writers. For those circumstances we can "mi
48 * needs to get a irq-safe write-lock, but rea
49 * read-locks.
50 */
51
52 static inline void arch_read_lock(arch_rwlock_
53 {
54 unsigned old;
55 do old = rw->lock;
56 while (!old || __sl_cas(&rw->lock, old
57 }
58
59 static inline void arch_read_unlock(arch_rwloc
60 {
61 unsigned old;
62 do old = rw->lock;
63 while (__sl_cas(&rw->lock, old, old+1)
64 }
65
66 static inline void arch_write_lock(arch_rwlock
67 {
68 while (__sl_cas(&rw->lock, RW_LOCK_BIA
69 }
70
71 static inline void arch_write_unlock(arch_rwlo
72 {
73 __sl_cas(&rw->lock, 0, RW_LOCK_BIAS);
74 }
75
76 static inline int arch_read_trylock(arch_rwloc
77 {
78 unsigned old;
79 do old = rw->lock;
80 while (old && __sl_cas(&rw->lock, old,
81 return !!old;
82 }
83
84 static inline int arch_write_trylock(arch_rwlo
85 {
86 return __sl_cas(&rw->lock, RW_LOCK_BIA
87 }
88
89 #endif /* __ASM_SH_SPINLOCK_CAS_H */
90
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