1 // SPDX-License-Identifier: GPL-2.0 1
2 /*
3 * arch/sh/kernel/cpu/sh4a/clock-sh7366.c
4 *
5 * SH7366 clock framework support
6 *
7 * Copyright (C) 2009 Magnus Damm
8 */
9 #include <linux/init.h>
10 #include <linux/kernel.h>
11 #include <linux/io.h>
12 #include <linux/clkdev.h>
13 #include <asm/clock.h>
14
15 /* SH7366 registers */
16 #define FRQCR 0xa4150000
17 #define VCLKCR 0xa4150004
18 #define SCLKACR 0xa4150008
19 #define SCLKBCR 0xa415000c
20 #define PLLCR 0xa4150024
21 #define MSTPCR0 0xa4150030
22 #define MSTPCR1 0xa4150034
23 #define MSTPCR2 0xa4150038
24 #define DLLFRQ 0xa4150050
25
26 /* Fixed 32 KHz root clock for RTC and Power M
27 static struct clk r_clk = {
28 .rate = 32768,
29 };
30
31 /*
32 * Default rate for the root input clock, rese
33 * from the platform code.
34 */
35 struct clk extal_clk = {
36 .rate = 33333333,
37 };
38
39 /* The dll block multiplies the 32khz r_clk, m
40 static unsigned long dll_recalc(struct clk *cl
41 {
42 unsigned long mult;
43
44 if (__raw_readl(PLLCR) & 0x1000)
45 mult = __raw_readl(DLLFRQ);
46 else
47 mult = 0;
48
49 return clk->parent->rate * mult;
50 }
51
52 static struct sh_clk_ops dll_clk_ops = {
53 .recalc = dll_recalc,
54 };
55
56 static struct clk dll_clk = {
57 .ops = &dll_clk_ops,
58 .parent = &r_clk,
59 .flags = CLK_ENABLE_ON_INIT,
60 };
61
62 static unsigned long pll_recalc(struct clk *cl
63 {
64 unsigned long mult = 1;
65 unsigned long div = 1;
66
67 if (__raw_readl(PLLCR) & 0x4000)
68 mult = (((__raw_readl(FRQCR) >
69 else
70 div = 2;
71
72 return (clk->parent->rate * mult) / di
73 }
74
75 static struct sh_clk_ops pll_clk_ops = {
76 .recalc = pll_recalc,
77 };
78
79 static struct clk pll_clk = {
80 .ops = &pll_clk_ops,
81 .flags = CLK_ENABLE_ON_INIT,
82 };
83
84 struct clk *main_clks[] = {
85 &r_clk,
86 &extal_clk,
87 &dll_clk,
88 &pll_clk,
89 };
90
91 static int multipliers[] = { 1, 2, 1, 2, 1, 1,
92 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5,
93
94 static struct clk_div_mult_table div4_div_mult
95 .divisors = divisors,
96 .nr_divisors = ARRAY_SIZE(divisors),
97 .multipliers = multipliers,
98 .nr_multipliers = ARRAY_SIZE(multiplie
99 };
100
101 static struct clk_div4_table div4_table = {
102 .div_mult_table = &div4_div_mult_table
103 };
104
105 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B
106 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
107
108 #define DIV4(_reg, _bit, _mask, _flags) \
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _fl
110
111 struct clk div4_clks[DIV4_NR] = {
112 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK
113 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK
114 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CL
115 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_
116 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK
117 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
118 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff,
119 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff,
120 };
121
122 enum { DIV6_V, DIV6_NR };
123
124 struct clk div6_clks[DIV6_NR] = {
125 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKC
126 };
127
128 #define MSTP(_parent, _reg, _bit, _flags) \
129 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
130
131 enum { MSTP031, MSTP030, MSTP029, MSTP028, MST
132 MSTP023, MSTP022, MSTP021, MSTP020, MST
133 MSTP015, MSTP014, MSTP013, MSTP012, MST
134 MSTP007, MSTP006, MSTP005, MSTP002, MST
135 MSTP109, MSTP100,
136 MSTP227, MSTP226, MSTP224, MSTP223, MST
137 MSTP211, MSTP207, MSTP205, MSTP204, MST
138 MSTP_NR };
139
140 static struct clk mstp_clks[MSTP_NR] = {
141 /* See page 52 of Datasheet V0.40: Ove
142 [MSTP031] = MSTP(&div4_clks[DIV4_I], M
143 [MSTP030] = MSTP(&div4_clks[DIV4_I], M
144 [MSTP029] = MSTP(&div4_clks[DIV4_I], M
145 [MSTP028] = MSTP(&div4_clks[DIV4_SH],
146 [MSTP026] = MSTP(&div4_clks[DIV4_B], M
147 [MSTP023] = MSTP(&div4_clks[DIV4_P], M
148 [MSTP022] = MSTP(&div4_clks[DIV4_P], M
149 [MSTP021] = MSTP(&div4_clks[DIV4_P], M
150 [MSTP020] = MSTP(&div4_clks[DIV4_P], M
151 [MSTP019] = MSTP(&div4_clks[DIV4_P], M
152 [MSTP017] = MSTP(&div4_clks[DIV4_P], M
153 [MSTP015] = MSTP(&div4_clks[DIV4_P], M
154 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14,
155 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13,
156 [MSTP011] = MSTP(&div4_clks[DIV4_P], M
157 [MSTP010] = MSTP(&div4_clks[DIV4_P], M
158 [MSTP007] = MSTP(&div4_clks[DIV4_P], M
159 [MSTP006] = MSTP(&div4_clks[DIV4_P], M
160 [MSTP005] = MSTP(&div4_clks[DIV4_P], M
161 [MSTP002] = MSTP(&div4_clks[DIV4_P], M
162 [MSTP001] = MSTP(&div4_clks[DIV4_P], M
163
164 [MSTP109] = MSTP(&div4_clks[DIV4_P], M
165
166 [MSTP227] = MSTP(&div4_clks[DIV4_P], M
167 [MSTP226] = MSTP(&div4_clks[DIV4_P], M
168 [MSTP224] = MSTP(&div4_clks[DIV4_P], M
169 [MSTP223] = MSTP(&div4_clks[DIV4_P], M
170 [MSTP222] = MSTP(&div4_clks[DIV4_P], M
171 [MSTP218] = MSTP(&div4_clks[DIV4_P], M
172 [MSTP217] = MSTP(&div4_clks[DIV4_P], M
173 [MSTP211] = MSTP(&div4_clks[DIV4_P], M
174 [MSTP207] = MSTP(&div4_clks[DIV4_B], M
175 [MSTP205] = MSTP(&div4_clks[DIV4_B], M
176 [MSTP204] = MSTP(&div4_clks[DIV4_B], M
177 [MSTP203] = MSTP(&div4_clks[DIV4_B], M
178 [MSTP202] = MSTP(&div4_clks[DIV4_B], M
179 [MSTP201] = MSTP(&div4_clks[DIV4_B], M
180 [MSTP200] = MSTP(&div4_clks[DIV4_B], M
181 };
182
183 static struct clk_lookup lookups[] = {
184 /* main clocks */
185 CLKDEV_CON_ID("rclk", &r_clk),
186 CLKDEV_CON_ID("extal", &extal_clk),
187 CLKDEV_CON_ID("dll_clk", &dll_clk),
188 CLKDEV_CON_ID("pll_clk", &pll_clk),
189
190 /* DIV4 clocks */
191 CLKDEV_CON_ID("cpu_clk", &div4_clks[DI
192 CLKDEV_CON_ID("umem_clk", &div4_clks[D
193 CLKDEV_CON_ID("shyway_clk", &div4_clks
194 CLKDEV_CON_ID("bus_clk", &div4_clks[DI
195 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV
196 CLKDEV_CON_ID("peripheral_clk", &div4_
197 CLKDEV_CON_ID("siua_clk", &div4_clks[D
198 CLKDEV_CON_ID("siub_clk", &div4_clks[D
199
200 /* DIV6 clocks */
201 CLKDEV_CON_ID("video_clk", &div6_clks[
202
203 /* MSTP32 clocks */
204 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP0
205 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP03
206 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP02
207 CLKDEV_CON_ID("rsmem0", &mstp_clks[MST
208 CLKDEV_CON_ID("xymem0", &mstp_clks[MST
209 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP
210 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP
211 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP
212 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP02
213 CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP
214 CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP0
215 CLKDEV_CON_ID("tmu_fck", &mstp_clks[MS
216 CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &m
217 CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP
218 CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP0
219 CLKDEV_CON_ID("flctl0", &mstp_clks[MST
220
221 CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp
222 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp
223 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp
224
225 CLKDEV_CON_ID("msiof0", &mstp_clks[MST
226 CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP0
227 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp
228 CLKDEV_CON_ID("icb0", &mstp_clks[MSTP2
229 CLKDEV_CON_ID("meram0", &mstp_clks[MST
230 CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP
231 CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP
232 CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP
233 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP
234 CLKDEV_CON_ID("mmcif0", &mstp_clks[MST
235 CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP
236 CLKDEV_CON_ID("veu1", &mstp_clks[MSTP2
237 CLKDEV_CON_ID("vou0", &mstp_clks[MSTP2
238 CLKDEV_CON_ID("beu0", &mstp_clks[MSTP2
239 CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP2
240 CLKDEV_CON_ID("veu0", &mstp_clks[MSTP2
241 CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP2
242 CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP
243 };
244
245 int __init arch_clk_init(void)
246 {
247 int k, ret = 0;
248
249 /* autodetect extal or dll configurati
250 if (__raw_readl(PLLCR) & 0x1000)
251 pll_clk.parent = &dll_clk;
252 else
253 pll_clk.parent = &extal_clk;
254
255 for (k = 0; !ret && (k < ARRAY_SIZE(ma
256 ret = clk_register(main_clks[k
257
258 clkdev_add_table(lookups, ARRAY_SIZE(l
259
260 if (!ret)
261 ret = sh_clk_div4_register(div
262
263 if (!ret)
264 ret = sh_clk_div6_register(div
265
266 if (!ret)
267 ret = sh_clk_mstp_register(mst
268
269 return ret;
270 }
271
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