1 // SPDX-License-Identifier: GPL-2.0 1
2 /*
3 * arch/sh/kernel/cpu/sh4a/clock-sh7723.c
4 *
5 * SH7723 clock framework support
6 *
7 * Copyright (C) 2009 Magnus Damm
8 */
9 #include <linux/init.h>
10 #include <linux/kernel.h>
11 #include <linux/io.h>
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/sh_clk.h>
15 #include <asm/clock.h>
16 #include <cpu/sh7723.h>
17
18 /* SH7723 registers */
19 #define FRQCR 0xa4150000
20 #define VCLKCR 0xa4150004
21 #define SCLKACR 0xa4150008
22 #define SCLKBCR 0xa415000c
23 #define IRDACLKCR 0xa4150018
24 #define PLLCR 0xa4150024
25 #define MSTPCR0 0xa4150030
26 #define MSTPCR1 0xa4150034
27 #define MSTPCR2 0xa4150038
28 #define DLLFRQ 0xa4150050
29
30 /* Fixed 32 KHz root clock for RTC and Power M
31 static struct clk r_clk = {
32 .rate = 32768,
33 };
34
35 /*
36 * Default rate for the root input clock, rese
37 * from the platform code.
38 */
39 struct clk extal_clk = {
40 .rate = 33333333,
41 };
42
43 /* The dll multiplies the 32khz r_clk, may be
44 static unsigned long dll_recalc(struct clk *cl
45 {
46 unsigned long mult;
47
48 if (__raw_readl(PLLCR) & 0x1000)
49 mult = __raw_readl(DLLFRQ);
50 else
51 mult = 0;
52
53 return clk->parent->rate * mult;
54 }
55
56 static struct sh_clk_ops dll_clk_ops = {
57 .recalc = dll_recalc,
58 };
59
60 static struct clk dll_clk = {
61 .ops = &dll_clk_ops,
62 .parent = &r_clk,
63 .flags = CLK_ENABLE_ON_INIT,
64 };
65
66 static unsigned long pll_recalc(struct clk *cl
67 {
68 unsigned long mult = 1;
69 unsigned long div = 1;
70
71 if (__raw_readl(PLLCR) & 0x4000)
72 mult = (((__raw_readl(FRQCR) >
73 else
74 div = 2;
75
76 return (clk->parent->rate * mult) / di
77 }
78
79 static struct sh_clk_ops pll_clk_ops = {
80 .recalc = pll_recalc,
81 };
82
83 static struct clk pll_clk = {
84 .ops = &pll_clk_ops,
85 .flags = CLK_ENABLE_ON_INIT,
86 };
87
88 struct clk *main_clks[] = {
89 &r_clk,
90 &extal_clk,
91 &dll_clk,
92 &pll_clk,
93 };
94
95 static int multipliers[] = { 1, 2, 1, 2, 1, 1,
96 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5,
97
98 static struct clk_div_mult_table div4_div_mult
99 .divisors = divisors,
100 .nr_divisors = ARRAY_SIZE(divisors),
101 .multipliers = multipliers,
102 .nr_multipliers = ARRAY_SIZE(multiplie
103 };
104
105 static struct clk_div4_table div4_table = {
106 .div_mult_table = &div4_div_mult_table
107 };
108
109 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B
110
111 #define DIV4(_reg, _bit, _mask, _flags) \
112 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _fl
113
114 struct clk div4_clks[DIV4_NR] = {
115 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK
116 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK
117 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CL
118 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_
119 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK
120 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
121 };
122
123 enum { DIV4_IRDA, DIV4_ENABLE_NR };
124
125 struct clk div4_enable_clks[DIV4_ENABLE_NR] =
126 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0db
127 };
128
129 enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR
130
131 struct clk div4_reparent_clks[DIV4_REPARENT_NR
132 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf,
133 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf,
134 };
135 enum { DIV6_V, DIV6_NR };
136
137 struct clk div6_clks[DIV6_NR] = {
138 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKC
139 };
140
141 static struct clk mstp_clks[] = {
142 /* See page 60 of Datasheet V1.0: Over
143 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_c
144 [HWBLK_IC] = SH_CLK_MSTP32(&div4_c
145 [HWBLK_OC] = SH_CLK_MSTP32(&div4_c
146 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_c
147 [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_c
148 [HWBLK_FPU] = SH_CLK_MSTP32(&div4_c
149 [HWBLK_INTC] = SH_CLK_MSTP32(&div4_c
150 [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_c
151 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_c
152 [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_c
153 [HWBLK_UBC] = SH_CLK_MSTP32(&div4_c
154 [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_c
155 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk,
156 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk,
157 [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_c
158 [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_c
159 [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_c
160 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_c
161 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_c
162 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_c
163 [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_c
164 [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_c
165 [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_c
166 [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_c
167 [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_c
168 [HWBLK_MERAM] = SH_CLK_MSTP32(&div4_c
169
170 [HWBLK_IIC] = SH_CLK_MSTP32(&div4_c
171 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk,
172
173 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_c
174 [HWBLK_ADC] = SH_CLK_MSTP32(&div4_c
175 [HWBLK_TPU] = SH_CLK_MSTP32(&div4_c
176 [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_c
177 [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_c
178 [HWBLK_ICB] = SH_CLK_MSTP32(&div4_c
179 [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_c
180 [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_c
181 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk,
182 [HWBLK_USB] = SH_CLK_MSTP32(&div4_c
183 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_c
184 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_c
185 [HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_c
186 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_c
187 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_c
188 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_c
189 [HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_c
190 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_c
191 [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_c
192 };
193
194 static struct clk_lookup lookups[] = {
195 /* main clocks */
196 CLKDEV_CON_ID("rclk", &r_clk),
197 CLKDEV_CON_ID("extal", &extal_clk),
198 CLKDEV_CON_ID("dll_clk", &dll_clk),
199 CLKDEV_CON_ID("pll_clk", &pll_clk),
200
201 /* DIV4 clocks */
202 CLKDEV_CON_ID("cpu_clk", &div4_clks[DI
203 CLKDEV_CON_ID("umem_clk", &div4_clks[D
204 CLKDEV_CON_ID("shyway_clk", &div4_clks
205 CLKDEV_CON_ID("bus_clk", &div4_clks[DI
206 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV
207 CLKDEV_CON_ID("peripheral_clk", &div4_
208 CLKDEV_CON_ID("irda_clk", &div4_enable
209 CLKDEV_CON_ID("siua_clk", &div4_repare
210 CLKDEV_CON_ID("siub_clk", &div4_repare
211
212 /* DIV6 clocks */
213 CLKDEV_CON_ID("video_clk", &div6_clks[
214
215 /* MSTP clocks */
216 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK
217 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_
218 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_
219 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK
220 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWB
221 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK
222 CLKDEV_CON_ID("intc0", &mstp_clks[HWBL
223 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp
224 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_
225 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBL
226 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK
227 CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &m
228 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[H
229 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp
230 CLKDEV_CON_ID("flctl0", &mstp_clks[HWB
231 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_
232 CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_
233 CLKDEV_DEV_ID("sh_mobile_meram.0", &ms
234 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp
235 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK
236 CLKDEV_CON_ID("atapi0", &mstp_clks[HWB
237 CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK
238 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK
239 CLKDEV_CON_ID("irda0", &mstp_clks[HWBL
240 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBL
241 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK
242 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mst
243 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mst
244 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks
245 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK
246 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK
247 CLKDEV_DEV_ID("siu-pcm-audio", &mstp_c
248 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK
249 CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[H
250 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK
251 CLKDEV_DEV_ID("ceu.0", &mstp_clks[HWBL
252 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK
253 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK
254
255 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp
256 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp
257
258 CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp
259 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp
260 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp
261 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp
262 CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp
263 CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp
264
265 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &
266 };
267
268 int __init arch_clk_init(void)
269 {
270 int k, ret = 0;
271
272 /* autodetect extal or dll configurati
273 if (__raw_readl(PLLCR) & 0x1000)
274 pll_clk.parent = &dll_clk;
275 else
276 pll_clk.parent = &extal_clk;
277
278 for (k = 0; !ret && (k < ARRAY_SIZE(ma
279 ret |= clk_register(main_clks[
280
281 clkdev_add_table(lookups, ARRAY_SIZE(l
282
283 if (!ret)
284 ret = sh_clk_div4_register(div
285
286 if (!ret)
287 ret = sh_clk_div4_enable_regis
288 DIV4_E
289
290 if (!ret)
291 ret = sh_clk_div4_reparent_reg
292 DIV4_R
293
294 if (!ret)
295 ret = sh_clk_div6_register(div
296
297 if (!ret)
298 ret = sh_clk_mstp_register(mst
299
300 return ret;
301 }
302
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