1 // SPDX-License-Identifier: GPL-2.0 1
2 /*
3 * arch/sh/kernel/cpu/sh4/clock-shx3.c
4 *
5 * SH-X3 support for the clock framework
6 *
7 * Copyright (C) 2006-2007 Renesas Technolog
8 * Copyright (C) 2006-2007 Renesas Solutions
9 * Copyright (C) 2006-2010 Paul Mundt
10 */
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/io.h>
14 #include <linux/clkdev.h>
15 #include <asm/clock.h>
16 #include <asm/freq.h>
17
18 /*
19 * Default rate for the root input clock, rese
20 * from the platform code.
21 */
22 static struct clk extal_clk = {
23 .rate = 16666666,
24 };
25
26 static unsigned long pll_recalc(struct clk *cl
27 {
28 /* PLL1 has a fixed x72 multiplier. *
29 return clk->parent->rate * 72;
30 }
31
32 static struct sh_clk_ops pll_clk_ops = {
33 .recalc = pll_recalc,
34 };
35
36 static struct clk pll_clk = {
37 .ops = &pll_clk_ops,
38 .parent = &extal_clk,
39 .flags = CLK_ENABLE_ON_INIT,
40 };
41
42 static struct clk *clks[] = {
43 &extal_clk,
44 &pll_clk,
45 };
46
47 static unsigned int div2[] = { 1, 2, 4, 6, 8,
48 24, 32, 36, 48
49
50 static struct clk_div_mult_table div4_div_mult
51 .divisors = div2,
52 .nr_divisors = ARRAY_SIZE(div2),
53 };
54
55 static struct clk_div4_table div4_table = {
56 .div_mult_table = &div4_div_mult_table
57 };
58
59 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4
60
61 #define DIV4(_bit, _mask, _flags) \
62 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _
63
64 struct clk div4_clks[DIV4_NR] = {
65 [DIV4_P] = DIV4(0, 0x0f80, 0),
66 [DIV4_SHA] = DIV4(4, 0x0ff0, 0),
67 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENAB
68 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE
69 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABL
70 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE
71 };
72
73 #define MSTPCR0 0xffc00030
74 #define MSTPCR1 0xffc00034
75
76 enum { MSTP027, MSTP026, MSTP025, MSTP024,
77 MSTP009, MSTP008, MSTP003, MSTP002,
78 MSTP001, MSTP000, MSTP119, MSTP105,
79 MSTP104, MSTP_NR };
80
81 static struct clk mstp_clks[MSTP_NR] = {
82 /* MSTPCR0 */
83 [MSTP027] = SH_CLK_MSTP32(&div4_clks[D
84 [MSTP026] = SH_CLK_MSTP32(&div4_clks[D
85 [MSTP025] = SH_CLK_MSTP32(&div4_clks[D
86 [MSTP024] = SH_CLK_MSTP32(&div4_clks[D
87 [MSTP009] = SH_CLK_MSTP32(&div4_clks[D
88 [MSTP008] = SH_CLK_MSTP32(&div4_clks[D
89 [MSTP003] = SH_CLK_MSTP32(&div4_clks[D
90 [MSTP002] = SH_CLK_MSTP32(&div4_clks[D
91 [MSTP001] = SH_CLK_MSTP32(&div4_clks[D
92 [MSTP000] = SH_CLK_MSTP32(&div4_clks[D
93
94 /* MSTPCR1 */
95 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR
96 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR
97 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR
98 };
99
100 static struct clk_lookup lookups[] = {
101 /* main clocks */
102 CLKDEV_CON_ID("extal", &extal_clk),
103 CLKDEV_CON_ID("pll_clk", &pll_clk),
104
105 /* DIV4 clocks */
106 CLKDEV_CON_ID("peripheral_clk", &div4_
107 CLKDEV_CON_ID("shywaya_clk", &div4_clk
108 CLKDEV_CON_ID("ddr_clk", &div4_clks[DI
109 CLKDEV_CON_ID("bus_clk", &div4_clks[DI
110 CLKDEV_CON_ID("shyway_clk", &div4_clks
111 CLKDEV_CON_ID("cpu_clk", &div4_clks[DI
112
113 /* MSTP32 clocks */
114 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp
115 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp
116 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp
117 CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp
118
119 CLKDEV_CON_ID("h8ex_fck", &mstp_clks[M
120 CLKDEV_CON_ID("csm_fck", &mstp_clks[MS
121 CLKDEV_CON_ID("fe1_fck", &mstp_clks[MS
122 CLKDEV_CON_ID("fe0_fck", &mstp_clks[MS
123
124 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp
125 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp
126
127 CLKDEV_CON_ID("hudi_fck", &mstp_clks[M
128 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_c
129 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_cl
130 };
131
132 int __init arch_clk_init(void)
133 {
134 int i, ret = 0;
135
136 for (i = 0; i < ARRAY_SIZE(clks); i++)
137 ret |= clk_register(clks[i]);
138
139 clkdev_add_table(lookups, ARRAY_SIZE(l
140
141 if (!ret)
142 ret = sh_clk_div4_register(div
143 &di
144 if (!ret)
145 ret = sh_clk_mstp_register(mst
146
147 return ret;
148 }
149
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