1 // SPDX-License-Identifier: GPL-2.0 1
2 /*
3 * SH7785 Setup
4 *
5 * Copyright (C) 2007 Paul Mundt
6 */
7 #include <linux/platform_device.h>
8 #include <linux/init.h>
9 #include <linux/serial.h>
10 #include <linux/serial_sci.h>
11 #include <linux/io.h>
12 #include <linux/mm.h>
13 #include <linux/sh_dma.h>
14 #include <linux/sh_timer.h>
15 #include <linux/sh_intc.h>
16 #include <asm/mmzone.h>
17 #include <asm/platform_early.h>
18 #include <cpu/dma-register.h>
19
20 static struct plat_sci_port scif0_platform_dat
21 .scscr = SCSCR_REIE | SCSCR_C
22 .type = PORT_SCIF,
23 .regtype = SCIx_SH4_SCIF_FIFODA
24 };
25
26 static struct resource scif0_resources[] = {
27 DEFINE_RES_MEM(0xffea0000, 0x100),
28 DEFINE_RES_IRQ(evt2irq(0x700)),
29 };
30
31 static struct platform_device scif0_device = {
32 .name = "sh-sci",
33 .id = 0,
34 .resource = scif0_resources,
35 .num_resources = ARRAY_SIZE(scif0_res
36 .dev = {
37 .platform_data = &scif0_platf
38 },
39 };
40
41 static struct plat_sci_port scif1_platform_dat
42 .scscr = SCSCR_REIE | SCSCR_C
43 .type = PORT_SCIF,
44 .regtype = SCIx_SH4_SCIF_FIFODA
45 };
46
47 static struct resource scif1_resources[] = {
48 DEFINE_RES_MEM(0xffeb0000, 0x100),
49 DEFINE_RES_IRQ(evt2irq(0x780)),
50 };
51
52 static struct platform_device scif1_device = {
53 .name = "sh-sci",
54 .id = 1,
55 .resource = scif1_resources,
56 .num_resources = ARRAY_SIZE(scif1_res
57 .dev = {
58 .platform_data = &scif1_platf
59 },
60 };
61
62 static struct plat_sci_port scif2_platform_dat
63 .scscr = SCSCR_REIE | SCSCR_C
64 .type = PORT_SCIF,
65 .regtype = SCIx_SH4_SCIF_FIFODA
66 };
67
68 static struct resource scif2_resources[] = {
69 DEFINE_RES_MEM(0xffec0000, 0x100),
70 DEFINE_RES_IRQ(evt2irq(0x980)),
71 };
72
73 static struct platform_device scif2_device = {
74 .name = "sh-sci",
75 .id = 2,
76 .resource = scif2_resources,
77 .num_resources = ARRAY_SIZE(scif2_res
78 .dev = {
79 .platform_data = &scif2_platf
80 },
81 };
82
83 static struct plat_sci_port scif3_platform_dat
84 .scscr = SCSCR_REIE | SCSCR_C
85 .type = PORT_SCIF,
86 .regtype = SCIx_SH4_SCIF_FIFODA
87 };
88
89 static struct resource scif3_resources[] = {
90 DEFINE_RES_MEM(0xffed0000, 0x100),
91 DEFINE_RES_IRQ(evt2irq(0x9a0)),
92 };
93
94 static struct platform_device scif3_device = {
95 .name = "sh-sci",
96 .id = 3,
97 .resource = scif3_resources,
98 .num_resources = ARRAY_SIZE(scif3_res
99 .dev = {
100 .platform_data = &scif3_platf
101 },
102 };
103
104 static struct plat_sci_port scif4_platform_dat
105 .scscr = SCSCR_REIE | SCSCR_C
106 .type = PORT_SCIF,
107 .regtype = SCIx_SH4_SCIF_FIFODA
108 };
109
110 static struct resource scif4_resources[] = {
111 DEFINE_RES_MEM(0xffee0000, 0x100),
112 DEFINE_RES_IRQ(evt2irq(0x9c0)),
113 };
114
115 static struct platform_device scif4_device = {
116 .name = "sh-sci",
117 .id = 4,
118 .resource = scif4_resources,
119 .num_resources = ARRAY_SIZE(scif4_res
120 .dev = {
121 .platform_data = &scif4_platf
122 },
123 };
124
125 static struct plat_sci_port scif5_platform_dat
126 .scscr = SCSCR_REIE | SCSCR_C
127 .type = PORT_SCIF,
128 .regtype = SCIx_SH4_SCIF_FIFODA
129 };
130
131 static struct resource scif5_resources[] = {
132 DEFINE_RES_MEM(0xffef0000, 0x100),
133 DEFINE_RES_IRQ(evt2irq(0x9e0)),
134 };
135
136 static struct platform_device scif5_device = {
137 .name = "sh-sci",
138 .id = 5,
139 .resource = scif5_resources,
140 .num_resources = ARRAY_SIZE(scif5_res
141 .dev = {
142 .platform_data = &scif5_platf
143 },
144 };
145
146 static struct sh_timer_config tmu0_platform_da
147 .channels_mask = 7,
148 };
149
150 static struct resource tmu0_resources[] = {
151 DEFINE_RES_MEM(0xffd80000, 0x30),
152 DEFINE_RES_IRQ(evt2irq(0x580)),
153 DEFINE_RES_IRQ(evt2irq(0x5a0)),
154 DEFINE_RES_IRQ(evt2irq(0x5c0)),
155 };
156
157 static struct platform_device tmu0_device = {
158 .name = "sh-tmu",
159 .id = 0,
160 .dev = {
161 .platform_data = &tmu0_platfo
162 },
163 .resource = tmu0_resources,
164 .num_resources = ARRAY_SIZE(tmu0_reso
165 };
166
167 static struct sh_timer_config tmu1_platform_da
168 .channels_mask = 7,
169 };
170
171 static struct resource tmu1_resources[] = {
172 DEFINE_RES_MEM(0xffdc0000, 0x2c),
173 DEFINE_RES_IRQ(evt2irq(0xe00)),
174 DEFINE_RES_IRQ(evt2irq(0xe20)),
175 DEFINE_RES_IRQ(evt2irq(0xe40)),
176 };
177
178 static struct platform_device tmu1_device = {
179 .name = "sh-tmu",
180 .id = 1,
181 .dev = {
182 .platform_data = &tmu1_platfo
183 },
184 .resource = tmu1_resources,
185 .num_resources = ARRAY_SIZE(tmu1_reso
186 };
187
188 /* DMA */
189 static const struct sh_dmae_channel sh7785_dma
190 {
191 .offset = 0,
192 .dmars = 0,
193 .dmars_bit = 0,
194 }, {
195 .offset = 0x10,
196 .dmars = 0,
197 .dmars_bit = 8,
198 }, {
199 .offset = 0x20,
200 .dmars = 4,
201 .dmars_bit = 0,
202 }, {
203 .offset = 0x30,
204 .dmars = 4,
205 .dmars_bit = 8,
206 }, {
207 .offset = 0x50,
208 .dmars = 8,
209 .dmars_bit = 0,
210 }, {
211 .offset = 0x60,
212 .dmars = 8,
213 .dmars_bit = 8,
214 }
215 };
216
217 static const struct sh_dmae_channel sh7785_dma
218 {
219 .offset = 0,
220 }, {
221 .offset = 0x10,
222 }, {
223 .offset = 0x20,
224 }, {
225 .offset = 0x30,
226 }, {
227 .offset = 0x50,
228 }, {
229 .offset = 0x60,
230 }
231 };
232
233 static const unsigned int ts_shift[] = TS_SHIF
234
235 static struct sh_dmae_pdata dma0_platform_data
236 .channel = sh7785_dmae0_channel
237 .channel_num = ARRAY_SIZE(sh7785_dm
238 .ts_low_shift = CHCR_TS_LOW_SHIFT,
239 .ts_low_mask = CHCR_TS_LOW_MASK,
240 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
241 .ts_high_mask = CHCR_TS_HIGH_MASK,
242 .ts_shift = ts_shift,
243 .ts_shift_num = ARRAY_SIZE(ts_shift)
244 .dmaor_init = DMAOR_INIT,
245 };
246
247 static struct sh_dmae_pdata dma1_platform_data
248 .channel = sh7785_dmae1_channel
249 .channel_num = ARRAY_SIZE(sh7785_dm
250 .ts_low_shift = CHCR_TS_LOW_SHIFT,
251 .ts_low_mask = CHCR_TS_LOW_MASK,
252 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
253 .ts_high_mask = CHCR_TS_HIGH_MASK,
254 .ts_shift = ts_shift,
255 .ts_shift_num = ARRAY_SIZE(ts_shift)
256 .dmaor_init = DMAOR_INIT,
257 };
258
259 static struct resource sh7785_dmae0_resources[
260 [0] = {
261 /* Channel registers and DMAOR
262 .start = 0xfc808020,
263 .end = 0xfc80808f,
264 .flags = IORESOURCE_MEM,
265 },
266 [1] = {
267 /* DMARSx */
268 .start = 0xfc809000,
269 .end = 0xfc80900b,
270 .flags = IORESOURCE_MEM,
271 },
272 {
273 /*
274 * Real DMA error vector is 0x
275 * vectors are 0x620-0x6c0
276 */
277 .name = "error_irq",
278 .start = evt2irq(0x620),
279 .end = evt2irq(0x620),
280 .flags = IORESOURCE_IRQ | IOR
281 },
282 };
283
284 static struct resource sh7785_dmae1_resources[
285 [0] = {
286 /* Channel registers and DMAOR
287 .start = 0xfcc08020,
288 .end = 0xfcc0808f,
289 .flags = IORESOURCE_MEM,
290 },
291 /* DMAC1 has no DMARS */
292 {
293 /*
294 * Real DMA error vector is 0x
295 * vectors are 0x880-0x920
296 */
297 .name = "error_irq",
298 .start = evt2irq(0x880),
299 .end = evt2irq(0x880),
300 .flags = IORESOURCE_IRQ | IOR
301 },
302 };
303
304 static struct platform_device dma0_device = {
305 .name = "sh-dma-engine",
306 .id = 0,
307 .resource = sh7785_dmae0_resourc
308 .num_resources = ARRAY_SIZE(sh7785_dm
309 .dev = {
310 .platform_data = &dma0_platfo
311 },
312 };
313
314 static struct platform_device dma1_device = {
315 .name = "sh-dma-engine",
316 .id = 1,
317 .resource = sh7785_dmae1_resourc
318 .num_resources = ARRAY_SIZE(sh7785_dm
319 .dev = {
320 .platform_data = &dma1_platfo
321 },
322 };
323
324 static struct platform_device *sh7785_devices[
325 &scif0_device,
326 &scif1_device,
327 &scif2_device,
328 &scif3_device,
329 &scif4_device,
330 &scif5_device,
331 &tmu0_device,
332 &tmu1_device,
333 &dma0_device,
334 &dma1_device,
335 };
336
337 static int __init sh7785_devices_setup(void)
338 {
339 return platform_add_devices(sh7785_dev
340 ARRAY_SIZE
341 }
342 arch_initcall(sh7785_devices_setup);
343
344 static struct platform_device *sh7785_early_de
345 &scif0_device,
346 &scif1_device,
347 &scif2_device,
348 &scif3_device,
349 &scif4_device,
350 &scif5_device,
351 &tmu0_device,
352 &tmu1_device,
353 };
354
355 void __init plat_early_device_setup(void)
356 {
357 sh_early_platform_add_devices(sh7785_e
358 ARRAY_SIZE(
359 }
360
361 enum {
362 UNUSED = 0,
363
364 /* interrupt sources */
365
366 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_
367 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_
368 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_
369 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
370
371 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_
372 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_
373 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_
374 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
375
376 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IR
377 WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
378 HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI
379 SCIF2, SCIF3, SCIF4, SCIF5,
380 PCISERR, PCIINTA, PCIINTB, PCIINTC, PC
381 SIOF, MMCIF, DU, GDTA,
382 TMU3, TMU4, TMU5,
383 SSI0, SSI1,
384 HAC0, HAC1,
385 FLCTL, GPIO,
386
387 /* interrupt groups */
388
389 TMU012, TMU345
390 };
391
392 static struct intc_vect vectors[] __initdata =
393 INTC_VECT(WDT, 0x560),
394 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1
395 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2
396 INTC_VECT(HUDI, 0x600),
397 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMA
398 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMA
399 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMA
400 INTC_VECT(DMAC0, 0x6e0),
401 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCI
402 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCI
403 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCI
404 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCI
405 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMA
406 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMA
407 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMA
408 INTC_VECT(DMAC1, 0x940),
409 INTC_VECT(HSPI, 0x960),
410 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCI
411 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCI
412 INTC_VECT(PCISERR, 0xa00), INTC_VECT(P
413 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(P
414 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(P
415 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCI
416 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCI
417 INTC_VECT(SIOF, 0xc00),
418 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMC
419 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMC
420 INTC_VECT(DU, 0xd80),
421 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA
422 INTC_VECT(GDTA, 0xde0),
423 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4
424 INTC_VECT(TMU5, 0xe40),
425 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1
426 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1
427 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLC
428 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLC
429 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO
430 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO
431 };
432
433 static struct intc_group groups[] __initdata =
434 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, T
435 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
436 };
437
438 static struct intc_mask_reg mask_registers[] _
439 { 0xffd00044, 0xffd00064, 32, /* INTMS
440 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5
441
442 { 0xffd40080, 0xffd40084, 32, /* INTMS
443 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, I
444 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, I
445 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, I
446 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0
447 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, I
448 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, I
449 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, I
450 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0
451
452 { 0xffd40038, 0xffd4003c, 32, /* INT2M
453 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPI
454 FLCTL, MMCIF, HSPI, SIOF, PCIC5, P
455 PCIINTA, PCISERR, HAC1, HAC0, DMAC
456 SCIF5, SCIF4, SCIF3, SCIF2, SCIF1,
457 };
458
459 static struct intc_prio_reg prio_registers[] _
460 { 0xffd00010, 0, 32, 4, /* INTPRI */
461
462 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */
463
464 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */
465 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */
466
467 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */
468 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */
469 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */
470
471 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */
472
473 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */
474 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */
475 { 0xffd40024, 0, 32, 8, /* INT2PRI9 */
476 };
477
478 static DECLARE_INTC_DESC(intc_desc, "sh7785",
479 mask_registers, prio_
480
481 /* Support for external interrupt pins in IRQ
482
483 static struct intc_vect vectors_irq0123[] __in
484 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1
485 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3
486 };
487
488 static struct intc_vect vectors_irq4567[] __in
489 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5
490 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7
491 };
492
493 static struct intc_sense_reg sense_registers[]
494 { 0xffd0001c, 32, 2, /* ICR1 */ { IR
495 IR
496 };
497
498 static struct intc_mask_reg ack_registers[] __
499 { 0xffd00024, 0, 32, /* INTREQ */
500 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5
501 };
502
503 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123
504 vectors_irq0123,
505 prio_registers, s
506
507 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567
508 vectors_irq4567,
509 prio_registers, s
510
511 /* External interrupt pins in IRL mode */
512
513 static struct intc_vect vectors_irl0123[] __in
514 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT
515 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT
516 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT
517 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT
518 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT
519 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT
520 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT
521 INTC_VECT(IRL0_HHHL, 0x3c0),
522 };
523
524 static struct intc_vect vectors_irl4567[] __in
525 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT
526 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT
527 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT
528 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT
529 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT
530 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT
531 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT
532 INTC_VECT(IRL4_HHHL, 0xcc0),
533 };
534
535 static DECLARE_INTC_DESC(intc_desc_irl0123, "s
536 NULL, mask_registers,
537
538 static DECLARE_INTC_DESC(intc_desc_irl4567, "s
539 NULL, mask_registers,
540
541 #define INTC_ICR0 0xffd00000
542 #define INTC_INTMSK0 0xffd00044
543 #define INTC_INTMSK1 0xffd00048
544 #define INTC_INTMSK2 0xffd40080
545 #define INTC_INTMSKCLR1 0xffd00068
546 #define INTC_INTMSKCLR2 0xffd40084
547
548 void __init plat_irq_setup(void)
549 {
550 /* disable IRQ3-0 + IRQ7-4 */
551 __raw_writel(0xff000000, INTC_INTMSK0)
552
553 /* disable IRL3-0 + IRL7-4 */
554 __raw_writel(0xc0000000, INTC_INTMSK1)
555 __raw_writel(0xfffefffe, INTC_INTMSK2)
556
557 /* select IRL mode for IRL3-0 + IRL7-4
558 __raw_writel(__raw_readl(INTC_ICR0) &
559
560 /* disable holding function, ie enable
561 __raw_writel(__raw_readl(INTC_ICR0) |
562
563 register_intc_controller(&intc_desc);
564 }
565
566 void __init plat_irq_setup_pins(int mode)
567 {
568 switch (mode) {
569 case IRQ_MODE_IRQ7654:
570 /* select IRQ mode for IRL7-4
571 __raw_writel(__raw_readl(INTC_
572 register_intc_controller(&intc
573 break;
574 case IRQ_MODE_IRQ3210:
575 /* select IRQ mode for IRL3-0
576 __raw_writel(__raw_readl(INTC_
577 register_intc_controller(&intc
578 break;
579 case IRQ_MODE_IRL7654:
580 /* enable IRL7-4 but don't pro
581 __raw_writel(0x40000000, INTC_
582 __raw_writel(0x0000fffe, INTC_
583 break;
584 case IRQ_MODE_IRL3210:
585 /* enable IRL0-3 but don't pro
586 __raw_writel(0x80000000, INTC_
587 __raw_writel(0xfffe0000, INTC_
588 break;
589 case IRQ_MODE_IRL7654_MASK:
590 /* enable IRL7-4 and mask usin
591 __raw_writel(0x40000000, INTC_
592 register_intc_controller(&intc
593 break;
594 case IRQ_MODE_IRL3210_MASK:
595 /* enable IRL0-3 and mask usin
596 __raw_writel(0x80000000, INTC_
597 register_intc_controller(&intc
598 break;
599 default:
600 BUG();
601 }
602 }
603
604 void __init plat_mem_setup(void)
605 {
606 /* Register the URAM space as Node 1 *
607 setup_bootmem_node(1, 0xe55f0000, 0xe5
608 }
609
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