1 // SPDX-License-Identifier: GPL-2.0 1
2 /*
3 * Disassemble SuperH instructions.
4 *
5 * Copyright (C) 1999 kaz Kojima
6 * Copyright (C) 2008 Paul Mundt
7 */
8 #include <linux/kernel.h>
9 #include <linux/string.h>
10 #include <linux/uaccess.h>
11
12 #include <asm/ptrace.h>
13
14 /*
15 * Format of an instruction in memory.
16 */
17 typedef enum {
18 HEX_0, HEX_1, HEX_2, HEX_3, HEX_4, HEX
19 HEX_8, HEX_9, HEX_A, HEX_B, HEX_C, HEX
20 REG_N, REG_M, REG_NM, REG_B,
21 BRANCH_12, BRANCH_8,
22 DISP_8, DISP_4,
23 IMM_4, IMM_4BY2, IMM_4BY4, PCRELIMM_8B
24 IMM_8, IMM_8BY2, IMM_8BY4,
25 } sh_nibble_type;
26
27 typedef enum {
28 A_END, A_BDISP12, A_BDISP8,
29 A_DEC_M, A_DEC_N,
30 A_DISP_GBR, A_DISP_PC, A_DISP_REG_M, A
31 A_GBR,
32 A_IMM,
33 A_INC_M, A_INC_N,
34 A_IND_M, A_IND_N, A_IND_R0_REG_M, A_IN
35 A_MACH, A_MACL,
36 A_PR, A_R0, A_R0_GBR, A_REG_M, A_REG_N
37 A_SR, A_VBR, A_SSR, A_SPC, A_SGR, A_DB
38 F_REG_N, F_REG_M, D_REG_N, D_REG_M,
39 X_REG_N, /* Only used for argument par
40 X_REG_M, /* Only used for argument par
41 DX_REG_N, DX_REG_M, V_REG_N, V_REG_M,
42 FD_REG_N,
43 XMTRX_M4,
44 F_FR0,
45 FPUL_N, FPUL_M, FPSCR_N, FPSCR_M,
46 } sh_arg_type;
47
48 static struct sh_opcode_info {
49 char *name;
50 sh_arg_type arg[7];
51 sh_nibble_type nibbles[4];
52 } sh_table[] = {
53 {"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IM
54 {"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N
55 {"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_
56 {"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_
57 {"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8
58 {"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N
59 {"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D
60 {"bra",{A_BDISP12},{HEX_A,BRANCH_12}},
61 {"bsr",{A_BDISP12},{HEX_B,BRANCH_12}},
62 {"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8
63 {"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8
64 {"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH
65 {"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH
66 {"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH
67 {"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH
68 {"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8
69 {"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}}
70 {"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}}
71 {"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IM
72 {"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,RE
73 {"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,RE
74 {"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,RE
75 {"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,RE
76 {"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,RE
77 {"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1
78 {"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1
79 {"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,R
80 {"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG
81 {"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}
82 {"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_
83 {"exts.b",{ A_REG_M,A_REG_N},{HEX_6,RE
84 {"exts.w",{ A_REG_M,A_REG_N},{HEX_6,RE
85 {"extu.b",{ A_REG_M,A_REG_N},{HEX_6,RE
86 {"extu.w",{ A_REG_M,A_REG_N},{HEX_6,RE
87 {"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HE
88 {"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HE
89 {"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX
90 {"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HE
91 {"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HE
92 {"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HE
93 {"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HE
94 {"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HE
95 {"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,
96 {"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,H
97 {"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,
98 {"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,
99 {"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,
100 {"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,
101 {"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,
102 {"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_
103 {"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,H
104 {"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,H
105 {"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX
106 {"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,H
107 {"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,
108 {"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N
109 {"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N
110 {"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,H
111 {"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M
112 {"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_
113 {"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}
114 {"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_
115 {"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IM
116 {"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N
117 {"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HE
118 {"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG
119 {"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG
120 {"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HE
121 {"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_
122 {"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX
123 {"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_
124 {"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_
125 {"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HE
126 {"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_
127 {"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_
128 {"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HE
129 {"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG
130 {"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG
131 {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5
132 {"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_
133 {"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,RE
134 {"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX
135 {"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_
136 {"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_
137 {"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_
138 {"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HE
139 {"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG
140 {"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG
141 {"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HE
142 {"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_
143 {"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,RE
144 {"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX
145 {"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_
146 {"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_
147 {"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HE
148 {"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_
149 {"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,
150 {"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N
151 {"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,H
152 {"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_
153 {"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG
154 {"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_
155 {"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N
156 {"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_
157 {"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}},
158 {"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N
159 {"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,H
160 {"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,H
161 {"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,
162 {"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}
163 {"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,
164 {"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,
165 {"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,H
166 {"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,
167 {"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,
168 {"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,H
169 {"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,H
170 {"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}},
171 {"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}},
172 {"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}}
173 {"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}}
174 {"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_
175 {"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_
176 {"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,H
177 {"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,H
178 {"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,H
179 {"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2
180 {"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,
181 {"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,
182 {"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,H
183 {"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2
184 {"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,
185 {"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,
186 {"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}
187 {"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX
188 {"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HE
189 {"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HE
190 {"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HE
191 {"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HE
192 {"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HE
193 {"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HE
194 {"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,
195 {"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,H
196 {"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,
197 {"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,
198 {"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,
199 {"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,
200 {"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,
201 {"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,
202 {"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_
203 {"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,H
204 {"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,H
205 {"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX
206 {"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,H
207 {"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,
208 {"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N
209 {"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N
210 {"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,H
211 {"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N
212 {"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_
213 {"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N
214 {"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_
215 {"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_
216 {"swap.b",{ A_REG_M,A_REG_N},{HEX_6,RE
217 {"swap.w",{ A_REG_M,A_REG_N},{HEX_6,RE
218 {"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,
219 {"trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}},
220 {"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8
221 {"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N
222 {"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C
223 {"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8
224 {"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N
225 {"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E
226 {"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG
227 {"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG
228 {"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX
229 {"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,R
230 {"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,R
231 {"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_
232 {"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,H
233 {"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,H
234 {"fabs",{FD_REG_N},{HEX_F,REG_N,HEX_5,
235 {"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N
236 {"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N
237 {"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,RE
238 {"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,RE
239 {"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,RE
240 {"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,RE
241 {"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_
242 {"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_
243 {"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N
244 {"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N
245 {"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_N
246 {"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,
247 {"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,
248 {"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,
249 {"float",{FPUL_M,FD_REG_N},{HEX_F,REG_
250 {"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F
251 {"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N
252 {"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG
253 {"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N
254 {"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_
255 {"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N
256 {"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_
257 {"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N
258 {"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_
259 {"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N
260 {"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_
261 {"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_
262 {"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX
263 {"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_
264 {"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX
265 {"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,RE
266 {"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,RE
267 {"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,RE
268 {"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,RE
269 {"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{H
270 {"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{H
271 {"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG
272 {"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG
273 {"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG
274 {"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG
275 {"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HE
276 {"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HE
277 {"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N
278 {"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N
279 {"fneg",{FD_REG_N},{HEX_F,REG_N,HEX_4,
280 {"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}
281 {"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}
282 {"fsqrt",{FD_REG_N},{HEX_F,REG_N,HEX_6
283 {"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,
284 {"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N
285 {"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N
286 {"ftrc",{FD_REG_N,FPUL_M},{HEX_F,REG_N
287 {"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_
288 { 0 },
289 };
290
291 static void print_sh_insn(u32 memaddr, u16 ins
292 {
293 int relmask = ~0;
294 int nibs[4] = { (insn >> 12) & 0xf, (i
295 int lastsp;
296 struct sh_opcode_info *op = sh_table;
297
298 for (; op->name; op++) {
299 int n;
300 int imm = 0;
301 int rn = 0;
302 int rm = 0;
303 int rb = 0;
304 int disp_pc;
305 int disp_pc_addr = 0;
306
307 for (n = 0; n < 4; n++) {
308 int i = op->nibbles[n]
309
310 if (i < 16) {
311 if (nibs[n] ==
312 contin
313 goto fail;
314 }
315 switch (i) {
316 case BRANCH_8:
317 imm = (nibs[2]
318 if (imm & 0x80
319 imm |=
320 imm = ((char)i
321 goto ok;
322 case BRANCH_12:
323 imm = ((nibs[1
324 if (imm & 0x80
325 imm |=
326 imm = imm * 2
327 goto ok;
328 case IMM_4:
329 imm = nibs[3];
330 goto ok;
331 case IMM_4BY2:
332 imm = nibs[3]
333 goto ok;
334 case IMM_4BY4:
335 imm = nibs[3]
336 goto ok;
337 case IMM_8:
338 imm = (nibs[2]
339 goto ok;
340 case PCRELIMM_8BY2:
341 imm = ((nibs[2
342 relmask = ~1;
343 goto ok;
344 case PCRELIMM_8BY4:
345 imm = ((nibs[2
346 relmask = ~3;
347 goto ok;
348 case IMM_8BY2:
349 imm = ((nibs[2
350 goto ok;
351 case IMM_8BY4:
352 imm = ((nibs[2
353 goto ok;
354 case DISP_8:
355 imm = (nibs[2]
356 goto ok;
357 case DISP_4:
358 imm = nibs[3];
359 goto ok;
360 case REG_N:
361 rn = nibs[n];
362 break;
363 case REG_M:
364 rm = nibs[n];
365 break;
366 case REG_NM:
367 rn = (nibs[n]
368 rm = (nibs[n]
369 break;
370 case REG_B:
371 rb = nibs[n] &
372 break;
373 default:
374 return;
375 }
376 }
377
378 ok:
379 pr_cont("%-8s ", op->name);
380 lastsp = (op->arg[0] == A_END)
381 disp_pc = 0;
382 for (n = 0; n < 6 && op->arg[n
383 if (n && op->arg[1] !=
384 pr_cont(", ");
385 switch (op->arg[n]) {
386 case A_IMM:
387 pr_cont("#%d",
388 break;
389 case A_R0:
390 pr_cont("r0");
391 break;
392 case A_REG_N:
393 pr_cont("r%d",
394 break;
395 case A_INC_N:
396 pr_cont("@r%d+
397 break;
398 case A_DEC_N:
399 pr_cont("@-r%d
400 break;
401 case A_IND_N:
402 pr_cont("@r%d"
403 break;
404 case A_DISP_REG_N:
405 pr_cont("@(%d,
406 break;
407 case A_REG_M:
408 pr_cont("r%d",
409 break;
410 case A_INC_M:
411 pr_cont("@r%d+
412 break;
413 case A_DEC_M:
414 pr_cont("@-r%d
415 break;
416 case A_IND_M:
417 pr_cont("@r%d"
418 break;
419 case A_DISP_REG_M:
420 pr_cont("@(%d,
421 break;
422 case A_REG_B:
423 pr_cont("r%d_b
424 break;
425 case A_DISP_PC:
426 disp_pc = 1;
427 disp_pc_addr =
428 pr_cont("%08x
429 (void
430 break;
431 case A_IND_R0_REG_N:
432 pr_cont("@(r0,
433 break;
434 case A_IND_R0_REG_M:
435 pr_cont("@(r0,
436 break;
437 case A_DISP_GBR:
438 pr_cont("@(%d,
439 break;
440 case A_R0_GBR:
441 pr_cont("@(r0,
442 break;
443 case A_BDISP12:
444 case A_BDISP8:
445 pr_cont("%08x"
446 break;
447 case A_SR:
448 pr_cont("sr");
449 break;
450 case A_GBR:
451 pr_cont("gbr")
452 break;
453 case A_VBR:
454 pr_cont("vbr")
455 break;
456 case A_SSR:
457 pr_cont("ssr")
458 break;
459 case A_SPC:
460 pr_cont("spc")
461 break;
462 case A_MACH:
463 pr_cont("mach"
464 break;
465 case A_MACL:
466 pr_cont("macl"
467 break;
468 case A_PR:
469 pr_cont("pr");
470 break;
471 case A_SGR:
472 pr_cont("sgr")
473 break;
474 case A_DBR:
475 pr_cont("dbr")
476 break;
477 case FD_REG_N:
478 case F_REG_N:
479 pr_cont("fr%d"
480 break;
481 case F_REG_M:
482 pr_cont("fr%d"
483 break;
484 case DX_REG_N:
485 if (rn & 1) {
486 pr_con
487 break;
488 }
489 fallthrough;
490 case D_REG_N:
491 pr_cont("dr%d"
492 break;
493 case DX_REG_M:
494 if (rm & 1) {
495 pr_con
496 break;
497 }
498 fallthrough;
499 case D_REG_M:
500 pr_cont("dr%d"
501 break;
502 case FPSCR_M:
503 case FPSCR_N:
504 pr_cont("fpscr
505 break;
506 case FPUL_M:
507 case FPUL_N:
508 pr_cont("fpul"
509 break;
510 case F_FR0:
511 pr_cont("fr0")
512 break;
513 case V_REG_N:
514 pr_cont("fv%d"
515 break;
516 case V_REG_M:
517 pr_cont("fv%d"
518 break;
519 case XMTRX_M4:
520 pr_cont("xmtrx
521 break;
522 default:
523 return;
524 }
525 }
526
527 if (disp_pc && strcmp(op->name
528 u32 val;
529
530 if (relmask == ~1)
531 __get_user(val
532 else
533 __get_user(val
534
535 pr_cont(" ! %08x <%pS
536 }
537
538 return;
539 fail:
540 ;
541
542 }
543
544 pr_info(".word 0x%x%x%x%x", nibs[0], n
545 }
546
547 void show_code(struct pt_regs *regs)
548 {
549 unsigned short *pc = (unsigned short *
550 long i;
551
552 if (regs->pc & 0x1)
553 return;
554
555 pr_info("Code:\n");
556
557 for (i = -3 ; i < 6 ; i++) {
558 unsigned short insn;
559
560 if (__get_user(insn, pc + i))
561 pr_err(" (Bad address
562 break;
563 }
564
565 pr_info("%s%08lx: ", (i ? "
566 (unsigned long)(pc + i
567 print_sh_insn((unsigned long)(
568 pr_cont("\n");
569 }
570
571 pr_info("\n");
572 }
573
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