1 # SPDX-License-Identifier: GPL-2.0
2 menu "Memory management options"
3
4 config MMU
5 bool "Support for memory management ha
6 depends on !CPU_SH2
7 select HAVE_PAGE_SIZE_4KB
8 select HAVE_PAGE_SIZE_8KB if X2TLB
9 select HAVE_PAGE_SIZE_64KB if CPU_SH4
10 default y
11 help
12 Some SH processors (such as SH-2/SH-
13 boot on these systems, this option m
14
15 On other systems (such as the SH-3 a
16 turning this off will boot the kerne
17 MMU implicitly switched off.
18
19 config NOMMU
20 def_bool !MMU
21 select HAVE_PAGE_SIZE_4KB
22 select HAVE_PAGE_SIZE_8KB
23 select HAVE_PAGE_SIZE_16KB
24 select HAVE_PAGE_SIZE_64KB
25 help
26 On MMU-less systems, any of these pa
27
28 config PAGE_OFFSET
29 hex
30 default "0x80000000" if MMU
31 default "0x00000000"
32
33 config ARCH_FORCE_MAX_ORDER
34 int "Order of maximal physically conti
35 default "8" if PAGE_SIZE_16KB
36 default "6" if PAGE_SIZE_64KB
37 default "13" if !MMU
38 default "10"
39 help
40 The kernel page allocator limits the
41 contiguous allocations. The limit is
42 defines the maximal power of two of
43 allocated as a single contiguous blo
44 overriding the default setting when
45 large blocks of physically contiguou
46
47 The page size is not necessarily 4KB
48 choosing a value for this option.
49
50 Don't change if unsure.
51
52 config MEMORY_START
53 hex "Physical memory start address"
54 default "0x08000000"
55 help
56 Computers built with Hitachi SuperH
57 map the ROM starting at address zero
58 does not specify the range that RAM
59
60 The physical memory (RAM) start addr
61 set to 08000000. Other platforms, su
62 boards typically map RAM at 0C000000
63
64 Tweak this only when porting to a ne
65 already have a defconfig. Changing i
66 value on any of the known systems wi
67
68 config MEMORY_SIZE
69 hex "Physical memory size"
70 default "0x04000000"
71 help
72 This sets the default memory size as
73 be overridden as normal by the 'mem=
74 line. If unsure, consult your board
75 as 0x04000000 which was the default
76 configurable.
77
78 # Physical addressing modes
79
80 config 29BIT
81 def_bool !32BIT
82 select UNCACHED_MAPPING
83
84 config 32BIT
85 bool
86 default !MMU
87
88 config PMB
89 bool "Support 32-bit physical addressi
90 depends on MMU && CPU_SH4A && !CPU_SH4
91 select 32BIT
92 select UNCACHED_MAPPING
93 help
94 If you say Y here, physical addressi
95 32-bits through the SH-4A PMB. If th
96 29-bit physical addressing will be u
97
98 config X2TLB
99 def_bool y
100 depends on (CPU_SHX2 || CPU_SHX3) && M
101
102 config VSYSCALL
103 bool "Support vsyscall page"
104 depends on MMU && (CPU_SH3 || CPU_SH4)
105 default y
106 help
107 This will enable support for the ker
108 in process space, and subsequently h
109 to the libc through the ELF auxiliar
110
111 From the kernel side this is used fo
112 For systems with an MMU that can aff
113 (the default value) say Y.
114
115 config NUMA
116 bool "Non-Uniform Memory Access (NUMA)
117 depends on MMU && SYS_SUPPORTS_NUMA
118 select ARCH_WANT_NUMA_VARIABLE_LOCALIT
119 default n
120 help
121 Some SH systems have many various me
122 the address space, each with varying
123 support for these blocks by binding
124 memory policies to be used for prior
125 allocation behaviour.
126
127 config NODES_SHIFT
128 int
129 default "3" if CPU_SUBTYPE_SHX3
130 default "1"
131 depends on NUMA
132
133 config ARCH_FLATMEM_ENABLE
134 def_bool y
135 depends on !NUMA
136
137 config ARCH_SPARSEMEM_ENABLE
138 def_bool y
139 select SPARSEMEM_STATIC
140
141 config ARCH_SPARSEMEM_DEFAULT
142 def_bool y
143
144 config ARCH_SELECT_MEMORY_MODEL
145 def_bool y
146
147 config IOREMAP_FIXED
148 def_bool y
149 depends on X2TLB
150
151 config UNCACHED_MAPPING
152 bool
153
154 config HAVE_SRAM_POOL
155 bool
156 select GENERIC_ALLOCATOR
157
158 choice
159 prompt "HugeTLB page size"
160 depends on HUGETLB_PAGE
161 default HUGETLB_PAGE_SIZE_1MB if PAGE_
162 default HUGETLB_PAGE_SIZE_64K
163
164 config HUGETLB_PAGE_SIZE_64K
165 bool "64kB"
166 depends on !PAGE_SIZE_64KB
167
168 config HUGETLB_PAGE_SIZE_256K
169 bool "256kB"
170 depends on X2TLB
171
172 config HUGETLB_PAGE_SIZE_1MB
173 bool "1MB"
174
175 config HUGETLB_PAGE_SIZE_4MB
176 bool "4MB"
177 depends on X2TLB
178
179 config HUGETLB_PAGE_SIZE_64MB
180 bool "64MB"
181 depends on X2TLB
182
183 endchoice
184
185 config SCHED_MC
186 bool "Multi-core scheduler support"
187 depends on SMP
188 default y
189 help
190 Multi-core scheduler support improve
191 making when dealing with multi-core
192 increased overhead in some places. I
193
194 endmenu
195
196 menu "Cache configuration"
197
198 config SH7705_CACHE_32KB
199 bool "Enable 32KB cache size for SH770
200 depends on CPU_SUBTYPE_SH7705
201 default y
202
203 choice
204 prompt "Cache mode"
205 default CACHE_WRITEBACK if CPU_SH2A ||
206 default CACHE_WRITETHROUGH if (CPU_SH2
207
208 config CACHE_WRITEBACK
209 bool "Write-back"
210
211 config CACHE_WRITETHROUGH
212 bool "Write-through"
213 help
214 Selecting this option will configure
215 mode, as opposed to the default writ
216
217 Since there's sill some aliasing iss
218 unfortunately still require the majo
219 be implemented to deal with aliasing
220
221 If unsure, say N.
222
223 config CACHE_OFF
224 bool "Off"
225
226 endchoice
227
228 endmenu
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