1 // SPDX-License-Identifier: GPL-2.0-only 1
2 /*
3 * arch/sh/mm/tlb-sh4.c
4 *
5 * SH-4 specific TLB operations
6 *
7 * Copyright (C) 1999 Niibe Yutaka
8 * Copyright (C) 2002 - 2007 Paul Mundt
9 */
10 #include <linux/kernel.h>
11 #include <linux/mm.h>
12 #include <linux/io.h>
13 #include <asm/mmu_context.h>
14 #include <asm/cacheflush.h>
15
16 void __update_tlb(struct vm_area_struct *vma,
17 {
18 unsigned long flags, pteval, vpn;
19
20 /*
21 * Handle debugger faulting in for deb
22 */
23 if (vma && current->active_mm != vma->
24 return;
25
26 local_irq_save(flags);
27
28 /* Set PTEH register */
29 vpn = (address & MMU_VPN_MASK) | get_a
30 __raw_writel(vpn, MMU_PTEH);
31
32 pteval = pte.pte_low;
33
34 /* Set PTEA register */
35 #ifdef CONFIG_X2TLB
36 /*
37 * For the extended mode TLB this is t
38 * EPR bits need to be written out to
39 * the protection bits (with the excep
40 * and PR bits, which are cleared) bei
41 */
42 __raw_writel(pte.pte_high, MMU_PTEA);
43 #else
44 if (cpu_data->flags & CPU_HAS_PTEA) {
45 /* The last 3 bits and the fir
46 * the PTEA timing control and
47 */
48 __raw_writel(copy_ptea_attribu
49 }
50 #endif
51
52 /* Set PTEL register */
53 pteval &= _PAGE_FLAGS_HARDWARE_MASK; /
54 #ifdef CONFIG_CACHE_WRITETHROUGH
55 pteval |= _PAGE_WT;
56 #endif
57 /* conveniently, we want all the softw
58 __raw_writel(pteval, MMU_PTEL);
59
60 /* Load the TLB */
61 asm volatile("ldtlb": /* no output */
62 local_irq_restore(flags);
63 }
64
65 void local_flush_tlb_one(unsigned long asid, u
66 {
67 unsigned long addr, data;
68
69 /*
70 * NOTE: PTEH.ASID should be set to th
71 * _AND_ we need to write ASID t
72 *
73 * It would be simple if we didn't nee
74 */
75 addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PA
76 data = page | asid; /* VALID bit is of
77 jump_to_uncached();
78 __raw_writel(data, addr);
79 back_to_cached();
80 }
81
82 void local_flush_tlb_all(void)
83 {
84 unsigned long flags, status;
85 int i;
86
87 /*
88 * Flush all the TLB.
89 */
90 local_irq_save(flags);
91 jump_to_uncached();
92
93 status = __raw_readl(MMUCR);
94 status = ((status & MMUCR_URB) >> MMUC
95
96 if (status == 0)
97 status = MMUCR_URB_NENTRIES;
98
99 for (i = 0; i < status; i++)
100 __raw_writel(0x0, MMU_UTLB_ADD
101
102 for (i = 0; i < 4; i++)
103 __raw_writel(0x0, MMU_ITLB_ADD
104
105 back_to_cached();
106 ctrl_barrier();
107 local_irq_restore(flags);
108 }
109
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