1 /* 1
2 * TLB miss handler for SH with an MMU.
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 - 2012 Paul Mundt
6 *
7 * This file is subject to the terms and condi
8 * License. See the file "COPYING" in the mai
9 * for more details.
10 */
11 #include <linux/kernel.h>
12 #include <linux/mm.h>
13 #include <linux/kprobes.h>
14 #include <linux/kdebug.h>
15 #include <asm/mmu_context.h>
16 #include <asm/thread_info.h>
17 #include <asm/tlb.h>
18
19 /*
20 * Called with interrupts disabled.
21 */
22 asmlinkage int __kprobes
23 handle_tlbmiss(struct pt_regs *regs, unsigned
24 unsigned long address)
25 {
26 pgd_t *pgd;
27 p4d_t *p4d;
28 pud_t *pud;
29 pmd_t *pmd;
30 pte_t *pte;
31 pte_t entry;
32
33 /*
34 * We don't take page faults for P1, P
35 * are always mapped, whether it be du
36 * 29-bit mode, or due to PMB configur
37 */
38 if (address >= P3SEG && address < P3_A
39 pgd = pgd_offset_k(address);
40 } else {
41 if (unlikely(address >= TASK_S
42 return 1;
43
44 pgd = pgd_offset(current->mm,
45 }
46
47 p4d = p4d_offset(pgd, address);
48 if (p4d_none_or_clear_bad(p4d))
49 return 1;
50 pud = pud_offset(p4d, address);
51 if (pud_none_or_clear_bad(pud))
52 return 1;
53 pmd = pmd_offset(pud, address);
54 if (pmd_none_or_clear_bad(pmd))
55 return 1;
56 pte = pte_offset_kernel(pmd, address);
57 entry = *pte;
58 if (unlikely(pte_none(entry) || pte_no
59 return 1;
60 if (unlikely(error_code && !pte_write(
61 return 1;
62
63 if (error_code)
64 entry = pte_mkdirty(entry);
65 entry = pte_mkyoung(entry);
66
67 set_pte(pte, entry);
68
69 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG
70 /*
71 * SH-4 does not set MMUCR.RC to the c
72 * the case of an initial page write e
73 * flush it in order to avoid potentia
74 */
75 if (error_code == FAULT_CODE_INITIAL)
76 local_flush_tlb_one(get_asid()
77 #endif
78
79 set_thread_fault_code(error_code);
80 update_mmu_cache(NULL, address, pte);
81
82 return 0;
83 }
84
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