1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 #ifndef _SPARC64_CHAFSR_H 3 #define _SPARC64_CHAFSR_H 4 5 /* Cheetah Asynchronous Fault Status register, 6 7 /* Comments indicate which processor variants 8 * is valid. Codes are: 9 * ch --> cheetah 10 * ch+ --> cheetah plus 11 * jp --> jalapeno 12 */ 13 14 /* All bits of this register except M_SYNDROME 15 * read, write 1 to clear. M_SYNDROME and E_S 16 */ 17 18 /* Software bit set by linux trap handlers to 19 * signalled at %tl >= 1. 20 */ 21 #define CHAFSR_TL1 (1UL << 63UL) 22 23 /* Unmapped error from system bus for prefetch 24 * store queue read operation 25 */ 26 #define CHPAFSR_DTO (1UL << 59UL) 27 28 /* Bus error from system bus for prefetch queu 29 * read operation 30 */ 31 #define CHPAFSR_DBERR (1UL << 58UL) 32 33 /* Hardware corrected E-cache Tag ECC error */ 34 #define CHPAFSR_THCE (1UL << 57UL) 35 /* System interface protocol error, hw timeout 36 #define JPAFSR_JETO (1UL << 57UL) 37 38 /* SW handled correctable E-cache Tag ECC erro 39 #define CHPAFSR_TSCE (1UL << 56UL) 40 /* Parity error on system snoop results */ 41 #define JPAFSR_SCE (1UL << 56UL) 42 43 /* Uncorrectable E-cache Tag ECC error */ 44 #define CHPAFSR_TUE (1UL << 55UL) 45 /* System interface protocol error, illegal co 46 #define JPAFSR_JEIC (1UL << 55UL) 47 48 /* Uncorrectable system bus data ECC error due 49 * or store fill request 50 */ 51 #define CHPAFSR_DUE (1UL << 54UL) 52 /* System interface protocol error, illegal AD 53 #define JPAFSR_JEIT (1UL << 54UL) 54 55 /* Multiple errors of the same type have occur 56 * an uncorrectable error or a SW correctable 57 * bit to report that error is already set. W 58 * different types are indicated by setting mu 59 * 60 * This bit is not set if multiple HW correcte 61 * status bit occur, only uncorrectable and SW 62 * this behavior. 63 * 64 * This bit is not set when multiple ECC error 65 * 64-byte system bus transaction. Only the f 66 * subunit will be logged. All errors in subs 67 * from the same 64-byte transaction are ignor 68 */ 69 #define CHAFSR_ME (1UL << 53UL) 70 71 /* Privileged state error has occurred. This 72 * at the time the error is detected. 73 */ 74 #define CHAFSR_PRIV (1UL << 52UL) 75 76 /* The following bits 51 (CHAFSR_PERR) to 33 ( 77 * bits and record the most recently detected 78 * errors that have been detected since the la 79 */ 80 81 /* System interface protocol error. The proce 82 * pin when this event occurs and it also logs 83 * into a JTAG scannable flop. 84 */ 85 #define CHAFSR_PERR (1UL << 51UL) 86 87 /* Internal processor error. The processor as 88 * pin when this event occurs and it also logs 89 * into a JTAG scannable flop. 90 */ 91 #define CHAFSR_IERR (1UL << 50UL) 92 93 /* System request parity error on incoming add 94 #define CHAFSR_ISAP (1UL << 49UL) 95 96 /* HW Corrected system bus MTAG ECC error */ 97 #define CHAFSR_EMC (1UL << 48UL) 98 /* Parity error on L2 cache tag SRAM */ 99 #define JPAFSR_ETP (1UL << 48UL) 100 101 /* Uncorrectable system bus MTAG ECC error */ 102 #define CHAFSR_EMU (1UL << 47UL) 103 /* Out of range memory error has occurred */ 104 #define JPAFSR_OM (1UL << 47UL) 105 106 /* HW Corrected system bus data ECC error for 107 #define CHAFSR_IVC (1UL << 46UL) 108 /* Error due to unsupported store */ 109 #define JPAFSR_UMS (1UL << 46UL) 110 111 /* Uncorrectable system bus data ECC error for 112 #define CHAFSR_IVU (1UL << 45UL) 113 114 /* Unmapped error from system bus */ 115 #define CHAFSR_TO (1UL << 44UL) 116 117 /* Bus error response from system bus */ 118 #define CHAFSR_BERR (1UL << 43UL) 119 120 /* SW Correctable E-cache ECC error for instru 121 * other than block load. 122 */ 123 #define CHAFSR_UCC (1UL << 42UL) 124 125 /* Uncorrectable E-cache ECC error for instruc 126 * other than block load. 127 */ 128 #define CHAFSR_UCU (1UL << 41UL) 129 130 /* Copyout HW Corrected ECC error */ 131 #define CHAFSR_CPC (1UL << 40UL) 132 133 /* Copyout Uncorrectable ECC error */ 134 #define CHAFSR_CPU (1UL << 39UL) 135 136 /* HW Corrected ECC error from E-cache for wri 137 #define CHAFSR_WDC (1UL << 38UL) 138 139 /* Uncorrectable ECC error from E-cache for wr 140 #define CHAFSR_WDU (1UL << 37UL) 141 142 /* HW Corrected ECC error from E-cache for sto 143 #define CHAFSR_EDC (1UL << 36UL) 144 145 /* Uncorrectable ECC error from E-cache for st 146 #define CHAFSR_EDU (1UL << 35UL) 147 148 /* Uncorrectable system bus data ECC error for 149 #define CHAFSR_UE (1UL << 34UL) 150 151 /* HW Corrected system bus data ECC error for 152 #define CHAFSR_CE (1UL << 33UL) 153 154 /* Uncorrectable ECC error from remote cache/m 155 #define JPAFSR_RUE (1UL << 32UL) 156 157 /* Correctable ECC error from remote cache/mem 158 #define JPAFSR_RCE (1UL << 31UL) 159 160 /* JBUS parity error on returned read data */ 161 #define JPAFSR_BP (1UL << 30UL) 162 163 /* JBUS parity error on data for writeback or 164 #define JPAFSR_WBP (1UL << 29UL) 165 166 /* Foreign read to DRAM incurring correctable 167 #define JPAFSR_FRC (1UL << 28UL) 168 169 /* Foreign read to DRAM incurring uncorrectabl 170 #define JPAFSR_FRU (1UL << 27UL) 171 172 #define CHAFSR_ERRORS (CHAFSR_PERR | 173 CHAFSR_EMU | 174 CHAFSR_BERR | 175 CHAFSR_CPU | 176 CHAFSR_EDU | 177 #define CHPAFSR_ERRORS (CHPAFSR_DTO | 178 CHPAFSR_TSCE 179 CHAFSR_PERR | 180 CHAFSR_EMU | 181 CHAFSR_BERR | 182 CHAFSR_CPU | 183 CHAFSR_EDU | 184 #define JPAFSR_ERRORS (JPAFSR_JETO | 185 JPAFSR_JEIT | 186 CHAFSR_ISAP | 187 JPAFSR_UMS | 188 CHAFSR_BERR | 189 CHAFSR_CPC | 190 CHAFSR_WDU | 191 CHAFSR_UE | C 192 JPAFSR_RCE | 193 JPAFSR_FRC | 194 195 /* Active JBUS request signal when error occur 196 #define JPAFSR_JBREQ (0x7UL << 24UL 197 #define JPAFSR_JBREQ_SHIFT 24UL 198 199 /* L2 cache way information */ 200 #define JPAFSR_ETW (0x3UL << 22UL 201 #define JPAFSR_ETW_SHIFT 22UL 202 203 /* System bus MTAG ECC syndrome. This field c 204 * first occurrence of the highest-priority er 205 * overwrite policy. After the AFSR sticky bi 206 * for which the M_SYND is reported, is cleare 207 * field will be unchanged by will be unfrozen 208 */ 209 #define CHAFSR_M_SYNDROME (0xfUL << 16UL 210 #define CHAFSR_M_SYNDROME_SHIFT 16UL 211 212 /* Agenid Id of the foreign device causing the 213 #define JPAFSR_AID (0x1fUL << 9UL 214 #define JPAFSR_AID_SHIFT 9UL 215 216 /* System bus or E-cache data ECC syndrome. T 217 * of the first occurrence of the highest-prio 218 * E_SYND overwrite policy. After the AFSR st 219 * error for which the E_SYND is reported, is 220 * field will be unchanged but will be unfroze 221 */ 222 #define CHAFSR_E_SYNDROME (0x1ffUL << 0U 223 #define CHAFSR_E_SYNDROME_SHIFT 0UL 224 225 /* The AFSR must be explicitly cleared by soft 226 * by a read. Writes to bits <51:33> with bit 227 * bits in the AFSR. Bits associated with dis 228 * interrupts are re-enabled to prevent multip 229 * PSTATE.IE and AFSR bits control delivery of 230 * 231 * Since there is only one AFAR, when multiple 232 * bits in the AFSR, at most one of these even 233 * in the AFAR. The highest priority of those 234 * The AFAR will be unlocked and available to 235 * as soon as the one bit in AFSR that corresp 236 * cleared. For example, if AFSR.CE is detect 237 * the AFAR), and AFSR.UE is cleared by not AF 238 * and ready for another event, even though AF 239 * also apply to the M_SYNDROME and E_SYNDROME 240 */ 241 242 #endif /* _SPARC64_CHAFSR_H */ 243
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