1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 #ifndef _ASM_SPARC_DMA_H 3 #define _ASM_SPARC_DMA_H 4 5 /* These are irrelevant for Sparc DMA, but we 6 * things can compile. 7 */ 8 #define MAX_DMA_CHANNELS 8 9 #define DMA_MODE_READ 1 10 #define DMA_MODE_WRITE 2 11 #define MAX_DMA_ADDRESS (~0UL) 12 13 /* Useful constants */ 14 #define SIZE_16MB (16*1024*1024) 15 #define SIZE_64K (64*1024) 16 17 /* SBUS DMA controller reg offsets */ 18 #define DMA_CSR 0x00UL /* rw 19 #define DMA_ADDR 0x04UL /* rw 20 #define DMA_COUNT 0x08UL /* rw 21 #define DMA_TEST 0x0cUL /* rw 22 23 /* Fields in the cond_reg register */ 24 /* First, the version identification bits */ 25 #define DMA_DEVICE_ID 0xf0000000 /* 26 #define DMA_VERS0 0x00000000 /* 27 #define DMA_ESCV1 0x40000000 /* 28 #define DMA_VERS1 0x80000000 /* 29 #define DMA_VERS2 0xa0000000 /* 30 #define DMA_VERHME 0xb0000000 /* 31 #define DMA_VERSPLUS 0x90000000 /* 32 33 #define DMA_HNDL_INTR 0x00000001 /* 34 #define DMA_HNDL_ERROR 0x00000002 /* 35 #define DMA_FIFO_ISDRAIN 0x0000000c /* 36 #define DMA_INT_ENAB 0x00000010 /* 37 #define DMA_FIFO_INV 0x00000020 /* 38 #define DMA_ACC_SZ_ERR 0x00000040 /* 39 #define DMA_FIFO_STDRAIN 0x00000040 /* 40 #define DMA_RST_SCSI 0x00000080 /* 41 #define DMA_RST_ENET DMA_RST_SCSI /* 42 #define DMA_ST_WRITE 0x00000100 /* 43 #define DMA_ENABLE 0x00000200 /* 44 #define DMA_PEND_READ 0x00000400 /* 45 #define DMA_ESC_BURST 0x00000800 /* 46 #define DMA_READ_AHEAD 0x00001800 /* 47 #define DMA_DSBL_RD_DRN 0x00001000 /* 48 #define DMA_BCNT_ENAB 0x00002000 /* 49 #define DMA_TERM_CNTR 0x00004000 /* 50 #define DMA_SCSI_SBUS64 0x00008000 /* 51 #define DMA_CSR_DISAB 0x00010000 /* 52 #define DMA_SCSI_DISAB 0x00020000 /* 53 #define DMA_DSBL_WR_INV 0x00020000 /* 54 #define DMA_ADD_ENABLE 0x00040000 /* 55 #define DMA_E_BURSTS 0x000c0000 /* 56 #define DMA_E_BURST32 0x00040000 /* 57 #define DMA_E_BURST16 0x00000000 /* 58 #define DMA_BRST_SZ 0x000c0000 /* 59 #define DMA_BRST64 0x000c0000 /* 60 #define DMA_BRST32 0x00040000 /* 61 #define DMA_BRST16 0x00000000 /* 62 #define DMA_BRST0 0x00080000 /* 63 #define DMA_ADDR_DISAB 0x00100000 /* 64 #define DMA_2CLKS 0x00200000 /* 65 #define DMA_3CLKS 0x00400000 /* 66 #define DMA_EN_ENETAUI DMA_3CLKS /* 67 #define DMA_CNTR_DISAB 0x00800000 /* 68 #define DMA_AUTO_NADDR 0x01000000 /* 69 #define DMA_SCSI_ON 0x02000000 /* 70 #define DMA_PARITY_OFF 0x02000000 /* 71 #define DMA_LOADED_ADDR 0x04000000 /* 72 #define DMA_LOADED_NADDR 0x08000000 /* 73 #define DMA_RESET_FAS366 0x08000000 /* 74 75 /* Values describing the burst-size property f 76 #define DMA_BURST1 0x01 77 #define DMA_BURST2 0x02 78 #define DMA_BURST4 0x04 79 #define DMA_BURST8 0x08 80 #define DMA_BURST16 0x10 81 #define DMA_BURST32 0x20 82 #define DMA_BURST64 0x40 83 #define DMA_BURSTBITS 0x7f 84 85 #ifdef CONFIG_SPARC32 86 struct device; 87 88 unsigned long sparc_dma_alloc_resource(struct 89 bool sparc_dma_free_resource(void *cpu_addr, s 90 #endif 91 92 #endif /* !(_ASM_SPARC_DMA_H) */ 93
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