1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 #ifndef _SPARC64_ESTATE_H 3 #define _SPARC64_ESTATE_H 4 5 /* UltraSPARC-III E-cache Error Enable */ 6 #define ESTATE_ERROR_FMT 0x000000000004 7 #define ESTATE_ERROR_FMESS 0x000000000003 8 #define ESTATE_ERROR_FMD 0x000000000000 9 #define ESTATE_ERROR_FDECC 0x000000000000 10 #define ESTATE_ERROR_UCEEN 0x000000000000 11 #define ESTATE_ERROR_NCEEN 0x000000000000 12 #define ESTATE_ERROR_CEEN 0x000000000000 13 14 /* UCEEN enables the fast_ECC_error trap for: 15 * errors 2) uncorrectable E-cache errors. Su 16 * of the E-cache by the local processor for: 17 * fetches 3) atomic operations. Such events 18 * 2) writeback 2) copyout. The AFSR bits ass 19 * UCC and UCU. 20 */ 21 22 /* NCEEN enables instruction_access_error, dat 23 * for uncorrectable ECC errors and system err 24 * 25 * Uncorrectable system bus data error or MTAG 26 * or system bus BusERR: 27 * 1) As the result of an instruction fetch, w 28 * 2) As the result of a load etc. will genera 29 * 3) As the result of store merge completion, 30 * generate a disrupting ECC_error trap. 31 * 4) As the result of such errors on instruct 32 * of the 3 trap types. 33 * 34 * The AFSR bits associated with these traps a 35 * BERR, and TO. 36 */ 37 38 /* CEEN enables the ECC_error trap for hardwar 39 * reads resulting in a hardware corrected dat 40 * ECC_error disrupting trap with this bit ena 41 * 42 * This same trap will also be generated when 43 * during store merge, writeback, and copyout 44 */ 45 46 /* In general, if the trap enable bits above a 47 * log the events even though the trap will no 48 */ 49 50 #endif /* _SPARC64_ESTATE_H */ 51
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