1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 /* pci_impl.h: Helper definitions for PCI cont
3 *
4 * Copyright (C) 1999, 2007 David S. Miller (d
5 */
6
7 #ifndef PCI_IMPL_H
8 #define PCI_IMPL_H
9
10 #include <linux/types.h>
11 #include <linux/spinlock.h>
12 #include <linux/pci.h>
13 #include <linux/msi.h>
14 #include <asm/io.h>
15 #include <asm/prom.h>
16 #include <asm/iommu.h>
17
18 /* The abstraction used here is that there are
19 * each with one (Sabre) or two (PSYCHO/SCHIZO
20 * underneath. Each PCI bus module uses an IO
21 * PBMs of a controller, or per-PBM), and if a
22 * is present, each PCI bus module has its own
23 * might be shared between PBMs, the STC is ne
24 * Furthermore, each PCI bus module controls i
25 * PCI bus.
26 */
27
28 #define PCI_STC_FLUSHFLAG_INIT(STC) \
29 (*((STC)->strbuf_flushflag) = 0UL)
30 #define PCI_STC_FLUSHFLAG_SET(STC) \
31 (*((STC)->strbuf_flushflag) != 0UL)
32
33 #ifdef CONFIG_PCI_MSI
34 struct pci_pbm_info;
35 struct sparc64_msiq_ops {
36 int (*get_head)(struct pci_pbm_info *p
37 unsigned long *head);
38 int (*dequeue_msi)(struct pci_pbm_info
39 unsigned long *head
40 int (*set_head)(struct pci_pbm_info *p
41 unsigned long head);
42 int (*msi_setup)(struct pci_pbm_info *
43 unsigned long msi, in
44 int (*msi_teardown)(struct pci_pbm_inf
45 int (*msiq_alloc)(struct pci_pbm_info
46 void (*msiq_free)(struct pci_pbm_info
47 int (*msiq_build_irq)(struct pci_pbm_i
48 unsigned long de
49 };
50
51 void sparc64_pbm_msi_init(struct pci_pbm_info
52 const struct sparc64
53
54 struct sparc64_msiq_cookie {
55 struct pci_pbm_info *pbm;
56 unsigned long msiqid;
57 };
58 #endif
59
60 struct pci_pbm_info {
61 struct pci_pbm_info *next;
62 struct pci_pbm_info *sibli
63 int index;
64
65 /* Physical address base of controller
66 unsigned long contro
67
68 /* Physical address base of PBM regist
69 unsigned long pbm_re
70
71 /* Physical address of DMA sync regist
72 unsigned long sync_r
73
74 /* Opaque 32-bit system bus Port ID. *
75 u32 portid
76
77 /* Opaque 32-bit handle used for hyper
78 u32 devhan
79
80 /* Chipset version information. */
81 int chip_t
82 #define PBM_CHIP_TYPE_SABRE 1
83 #define PBM_CHIP_TYPE_PSYCHO 2
84 #define PBM_CHIP_TYPE_SCHIZO 3
85 #define PBM_CHIP_TYPE_SCHIZO_PLUS 4
86 #define PBM_CHIP_TYPE_TOMATILLO 5
87 int chip_v
88 int chip_r
89
90 /* Name used for top-level resources.
91 const char *name;
92
93 /* OBP specific information. */
94 struct platform_device *op;
95 u64 ino_bi
96
97 /* PBM I/O and Memory space resources.
98 struct resource io_spa
99 struct resource mem_sp
100 struct resource mem64_
101 struct resource busn;
102 /* offset */
103 resource_size_t io_off
104 resource_size_t mem_of
105 resource_size_t mem64_
106
107 /* Base of PCI Config space, can be pe
108 unsigned long config
109
110 /* This will be 12 on PCI-E controller
111 unsigned long config
112
113 unsigned long pci_af
114 unsigned long pci_af
115 unsigned long pci_cs
116
117 /* State of 66MHz capabilities on this
118 int is_66m
119 int all_de
120
121 #ifdef CONFIG_PCI_MSI
122 /* MSI info. */
123 u32 msiq_n
124 u32 msiq_e
125 u32 msiq_f
126 u32 msiq_f
127 u32 msiq_r
128 struct sparc64_msiq_cookie *msiq_
129 u32 msi_nu
130 u32 msi_fi
131 u32 msi_da
132 u32 msix_d
133 u64 msi32_
134 u64 msi64_
135 u32 msi32_
136 u32 msi64_
137 void *msi_q
138 unsigned long *msi_b
139 unsigned int *msi_i
140 int (*setup_msi_irq)(unsigned int *irq
141 struct msi_desc *
142 void (*teardown_msi_irq)(unsigned int
143 const struct sparc64_msiq_ops *msi_o
144 #endif /* !(CONFIG_PCI_MSI) */
145
146 /* This PBM's streaming buffer. */
147 struct strbuf stc;
148
149 /* IOMMU state, potentially shared by
150 struct iommu *iommu
151
152 /* Now things for the actual PCI bus p
153 unsigned int pci_fi
154 unsigned int pci_la
155 struct pci_bus *pci_b
156 struct pci_ops *pci_o
157
158 int numa_n
159 };
160
161 extern struct pci_pbm_info *pci_pbm_root;
162
163 extern int pci_num_pbms;
164
165 /* PCI bus scanning and fixup support. */
166 void pci_get_pbm_props(struct pci_pbm_info *pb
167 struct pci_bus *pci_scan_one_pbm(struct pci_pb
168 struct device
169 void pci_determine_mem_io_space(struct pci_pbm
170
171 /* Error reporting support. */
172 void pci_scan_for_target_abort(struct pci_pbm_
173 void pci_scan_for_master_abort(struct pci_pbm_
174 void pci_scan_for_parity_error(struct pci_pbm_
175
176 /* Configuration space access. */
177 void pci_config_read8(u8 *addr, u8 *ret);
178 void pci_config_read16(u16 *addr, u16 *ret);
179 void pci_config_read32(u32 *addr, u32 *ret);
180 void pci_config_write8(u8 *addr, u8 val);
181 void pci_config_write16(u16 *addr, u16 val);
182 void pci_config_write32(u32 *addr, u32 val);
183
184 extern struct pci_ops sun4u_pci_ops;
185 extern struct pci_ops sun4v_pci_ops;
186
187 extern volatile int pci_poke_in_progress;
188 extern volatile int pci_poke_cpu;
189 extern volatile int pci_poke_faulted;
190
191 #endif /* !(PCI_IMPL_H) */
192
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