1 // SPDX-License-Identifier: GPL-2.0 1
2 /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI
3 *
4 * Copyright (C) 2001, 2002, 2003, 2007, 2008
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 #include <linux/pci.h>
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/export.h>
13 #include <linux/interrupt.h>
14 #include <linux/of.h>
15 #include <linux/of_platform.h>
16 #include <linux/platform_device.h>
17 #include <linux/property.h>
18 #include <linux/numa.h>
19
20 #include <asm/iommu.h>
21 #include <asm/irq.h>
22 #include <asm/pstate.h>
23 #include <asm/prom.h>
24 #include <asm/upa.h>
25
26 #include "pci_impl.h"
27 #include "iommu_common.h"
28
29 #define DRIVER_NAME "schizo"
30 #define PFX DRIVER_NAME ": "
31
32 /* This is a convention that at least Excalibu
33 * follow. I suppose the SCHIZO used in Starc
34 * will do similar.
35 *
36 * The only way I could see this changing is i
37 * block requires more space in Schizo's addre
38 * they predicted, thus requiring an address s
39 * the newer Schizo is taped out.
40 */
41
42 /* Streaming buffer control register. */
43 #define SCHIZO_STRBUF_CTRL_LPTR 0x000000000
44 #define SCHIZO_STRBUF_CTRL_LENAB 0x000000000
45 #define SCHIZO_STRBUF_CTRL_RRDIS 0x000000000
46 #define SCHIZO_STRBUF_CTRL_DENAB 0x000000000
47 #define SCHIZO_STRBUF_CTRL_ENAB 0x000000000
48
49 /* IOMMU control register. */
50 #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff
51 #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x000000000
52 #define SCHIZO_IOMMU_CTRL_XLTEERR 0x000000000
53 #define SCHIZO_IOMMU_CTRL_LCKEN 0x000000000
54 #define SCHIZO_IOMMU_CTRL_LCKPTR 0x000000000
55 #define SCHIZO_IOMMU_CTRL_TSBSZ 0x000000000
56 #define SCHIZO_IOMMU_TSBSZ_1K 0x000000000
57 #define SCHIZO_IOMMU_TSBSZ_2K 0x000000000
58 #define SCHIZO_IOMMU_TSBSZ_4K 0x000000000
59 #define SCHIZO_IOMMU_TSBSZ_8K 0x000000000
60 #define SCHIZO_IOMMU_TSBSZ_16K 0x000000000
61 #define SCHIZO_IOMMU_TSBSZ_32K 0x000000000
62 #define SCHIZO_IOMMU_TSBSZ_64K 0x000000000
63 #define SCHIZO_IOMMU_TSBSZ_128K 0x000000000
64 #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000
65 #define SCHIZO_IOMMU_CTRL_TBWSZ 0x000000000
66 #define SCHIZO_IOMMU_CTRL_DENAB 0x000000000
67 #define SCHIZO_IOMMU_CTRL_ENAB 0x000000000
68
69 /* Schizo config space address format is nearl
70 * that of PSYCHO:
71 *
72 * 32 24 23 16 15 11 10
73 * -------------------------------------------
74 * |0 0 0 0 0 0 0 0 0| bus | device | function
75 * -------------------------------------------
76 */
77 #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config
78 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG)
79 (((unsigned long)(BUS) << 16) |
80 ((unsigned long)(DEVFN) << 8) |
81 ((unsigned long)(REG)))
82
83 static void *schizo_pci_config_mkaddr(struct p
84 unsigned
85 unsigned
86 int wher
87 {
88 if (!pbm)
89 return NULL;
90 bus -= pbm->pci_first_busno;
91 return (void *)
92 (SCHIZO_CONFIG_BASE(pbm) |
93 SCHIZO_CONFIG_ENCODE(bus, dev
94 }
95
96 /* SCHIZO error handling support. */
97 enum schizo_error_type {
98 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
99 };
100
101 static DEFINE_SPINLOCK(stc_buf_lock);
102 static unsigned long stc_error_buf[128];
103 static unsigned long stc_tag_buf[16];
104 static unsigned long stc_line_buf[16];
105
106 #define SCHIZO_UE_INO 0x30 /* Uncorr
107 #define SCHIZO_CE_INO 0x31 /* Correc
108 #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A
109 #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B
110 #define SCHIZO_SERR_INO 0x34 /* Safari
111
112 #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00
113 #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80
114 #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80
115
116 #define SCHIZO_STCERR_WRITE 0x2UL
117 #define SCHIZO_STCERR_READ 0x1UL
118
119 #define SCHIZO_STCTAG_PPN 0x3fffffff0000
120 #define SCHIZO_STCTAG_VPN 0x00000000ffff
121 #define SCHIZO_STCTAG_VALID 0x800000000000
122 #define SCHIZO_STCTAG_READ 0x400000000000
123
124 #define SCHIZO_STCLINE_LINDX 0x000000000780
125 #define SCHIZO_STCLINE_SPTR 0x000000000007
126 #define SCHIZO_STCLINE_LADDR 0x000000000000
127 #define SCHIZO_STCLINE_EPTR 0x000000000000
128 #define SCHIZO_STCLINE_VALID 0x000000000060
129 #define SCHIZO_STCLINE_FOFN 0x000000000018
130
131 static void __schizo_check_stc_error_pbm(struc
132 enum
133 {
134 struct strbuf *strbuf = &pbm->stc;
135 unsigned long regbase = pbm->pbm_regs;
136 unsigned long err_base, tag_base, line
137 u64 control;
138 int i;
139
140 err_base = regbase + SCHIZO_STC_ERR;
141 tag_base = regbase + SCHIZO_STC_TAG;
142 line_base = regbase + SCHIZO_STC_LINE;
143
144 spin_lock(&stc_buf_lock);
145
146 /* This is __REALLY__ dangerous. When
147 * streaming buffer into diagnostic mo
148 * its tags and error status, we _must
149 * of the line tag valid bits before r
150 * the streaming buffer. If any dirty
151 * in the STC when we do this, we will
152 * invalidating it before it has a cha
153 * main memory.
154 */
155 control = upa_readq(strbuf->strbuf_con
156 upa_writeq((control | SCHIZO_STRBUF_CT
157 strbuf->strbuf_control);
158 for (i = 0; i < 128; i++) {
159 unsigned long val;
160
161 val = upa_readq(err_base + (i
162 upa_writeq(0UL, err_base + (i
163 stc_error_buf[i] = val;
164 }
165 for (i = 0; i < 16; i++) {
166 stc_tag_buf[i] = upa_readq(tag
167 stc_line_buf[i] = upa_readq(li
168 upa_writeq(0UL, tag_base + (i
169 upa_writeq(0UL, line_base + (i
170 }
171
172 /* OK, state is logged, exit diagnosti
173 upa_writeq(control, strbuf->strbuf_con
174
175 for (i = 0; i < 16; i++) {
176 int j, saw_error, first, last;
177
178 saw_error = 0;
179 first = i * 8;
180 last = first + 8;
181 for (j = first; j < last; j++)
182 unsigned long errval =
183 if (errval != 0) {
184 saw_error++;
185 printk("%s: ST
186 pbm->na
187 j,
188 (errval
189 (errval
190 }
191 }
192 if (saw_error != 0) {
193 unsigned long tagval =
194 unsigned long lineval
195 printk("%s: STC_TAG(%d
196 pbm->name,
197 i,
198 ((tagval & SCHI
199 (tagval & SCHIZ
200 ((tagval & SCHI
201 ((tagval & SCHI
202
203 /* XXX Should spit out
204 printk("%s: STC_LINE(%
205 "V(%d)FOFN(%d)]
206 pbm->name,
207 i,
208 ((lineval & SCH
209 ((lineval & SCH
210 ((lineval & SCH
211 ((lineval & SCH
212 ((lineval & SCH
213 ((lineval & SCH
214 }
215 }
216
217 spin_unlock(&stc_buf_lock);
218 }
219
220 /* IOMMU is per-PBM in Schizo, so interrogate
221 * controller level errors.
222 */
223
224 #define SCHIZO_IOMMU_TAG 0xa580UL
225 #define SCHIZO_IOMMU_DATA 0xa600UL
226
227 #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe00
228 #define SCHIZO_IOMMU_TAG_ERRSTS 0x000000000180
229 #define SCHIZO_IOMMU_TAG_ERR 0x000000000040
230 #define SCHIZO_IOMMU_TAG_WRITE 0x000000000020
231 #define SCHIZO_IOMMU_TAG_STREAM 0x000000000010
232 #define SCHIZO_IOMMU_TAG_SIZE 0x000000000008
233 #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007
234
235 #define SCHIZO_IOMMU_DATA_VALID 0x000000010000
236 #define SCHIZO_IOMMU_DATA_CACHE 0x000000004000
237 #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fff
238
239 static void schizo_check_iommu_error_pbm(struc
240 enum
241 {
242 struct iommu *iommu = pbm->iommu;
243 unsigned long iommu_tag[16];
244 unsigned long iommu_data[16];
245 unsigned long flags;
246 u64 control;
247 int i;
248
249 spin_lock_irqsave(&iommu->lock, flags)
250 control = upa_readq(iommu->iommu_contr
251 if (control & SCHIZO_IOMMU_CTRL_XLTEER
252 unsigned long base;
253 char *type_string;
254
255 /* Clear the error encountered
256 control &= ~SCHIZO_IOMMU_CTRL_
257 upa_writeq(control, iommu->iom
258
259 switch((control & SCHIZO_IOMMU
260 case 0:
261 type_string = "Protect
262 break;
263 case 1:
264 type_string = "Invalid
265 break;
266 case 2:
267 type_string = "TimeOut
268 break;
269 case 3:
270 default:
271 type_string = "ECC Err
272 break;
273 }
274 printk("%s: IOMMU Error, type[
275 pbm->name, type_string)
276
277 /* Put the IOMMU into diagnost
278 * its TLB for entries with er
279 *
280 * It is very possible for ano
281 * while we do this probe, and
282 * further. But we are so scr
283 * that we are likely to crash
284 * get as much diagnostic info
285 * console as we can.
286 */
287 upa_writeq(control | SCHIZO_IO
288 iommu->iommu_contro
289
290 base = pbm->pbm_regs;
291
292 for (i = 0; i < 16; i++) {
293 iommu_tag[i] =
294 upa_readq(base
295 iommu_data[i] =
296 upa_readq(base
297
298 /* Now clear out the e
299 upa_writeq(0, base + S
300 upa_writeq(0, base + S
301 }
302
303 /* Leave diagnostic mode. */
304 upa_writeq(control, iommu->iom
305
306 for (i = 0; i < 16; i++) {
307 unsigned long tag, dat
308
309 tag = iommu_tag[i];
310 if (!(tag & SCHIZO_IOM
311 continue;
312
313 data = iommu_data[i];
314 switch((tag & SCHIZO_I
315 case 0:
316 type_string =
317 break;
318 case 1:
319 type_string =
320 break;
321 case 2:
322 type_string =
323 break;
324 case 3:
325 default:
326 type_string =
327 break;
328 }
329 printk("%s: IOMMU TAG(
330 "sz(%dK) vpg(%0
331 pbm->name, i, t
332 (int)((tag & SC
333 ((tag & SCHIZO_
334 ((tag & SCHIZO_
335 ((tag & SCHIZO_
336 (tag & SCHIZO_I
337 printk("%s: IOMMU DATA
338 pbm->name, i,
339 ((data & SCHIZO
340 ((data & SCHIZO
341 (data & SCHIZO_
342 }
343 }
344 if (pbm->stc.strbuf_enabled)
345 __schizo_check_stc_error_pbm(p
346 spin_unlock_irqrestore(&iommu->lock, f
347 }
348
349 static void schizo_check_iommu_error(struct pc
350 enum schi
351 {
352 schizo_check_iommu_error_pbm(pbm, type
353 if (pbm->sibling)
354 schizo_check_iommu_error_pbm(p
355 }
356
357 /* Uncorrectable ECC error status gathering. *
358 #define SCHIZO_UE_AFSR 0x10030UL
359 #define SCHIZO_UE_AFAR 0x10038UL
360
361 #define SCHIZO_UEAFSR_PPIO 0x800000000000
362 #define SCHIZO_UEAFSR_PDRD 0x400000000000
363 #define SCHIZO_UEAFSR_PDWR 0x200000000000
364 #define SCHIZO_UEAFSR_SPIO 0x100000000000
365 #define SCHIZO_UEAFSR_SDMA 0x080000000000
366 #define SCHIZO_UEAFSR_ERRPNDG 0x030000000000
367 #define SCHIZO_UEAFSR_BMSK 0x000003ff0000
368 #define SCHIZO_UEAFSR_QOFF 0x00000000c000
369 #define SCHIZO_UEAFSR_AID 0x000000001f00
370 #define SCHIZO_UEAFSR_PARTIAL 0x000000000080
371 #define SCHIZO_UEAFSR_OWNEDIN 0x000000000040
372 #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f
373 #define SCHIZO_UEAFSR_MTAG 0x000000000000
374 #define SCHIZO_UEAFSR_ECCSYND 0x000000000000
375
376 static irqreturn_t schizo_ue_intr(int irq, voi
377 {
378 struct pci_pbm_info *pbm = dev_id;
379 unsigned long afsr_reg = pbm->controll
380 unsigned long afar_reg = pbm->controll
381 unsigned long afsr, afar, error_bits;
382 int reported, limit;
383
384 /* Latch uncorrectable error status. *
385 afar = upa_readq(afar_reg);
386
387 /* If either of the error pending bits
388 * AFSR, the error status is being act
389 * the hardware and we must re-read to
390 */
391 limit = 1000;
392 do {
393 afsr = upa_readq(afsr_reg);
394 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG
395
396 /* Clear the primary/secondary error s
397 error_bits = afsr &
398 (SCHIZO_UEAFSR_PPIO | SCHIZO_U
399 SCHIZO_UEAFSR_SPIO | SCHIZO_U
400 if (!error_bits)
401 return IRQ_NONE;
402 upa_writeq(error_bits, afsr_reg);
403
404 /* Log the error. */
405 printk("%s: Uncorrectable Error, prima
406 pbm->name,
407 (((error_bits & SCHIZO_UEAFSR_P
408 "PIO" :
409 ((error_bits & SCHIZO_UEAFSR_
410 "DMA Read" :
411 ((error_bits & SCHIZO_UEAFSR
412 "DMA Write" : "???")))));
413 printk("%s: bytemask[%04lx] qword_offs
414 pbm->name,
415 (afsr & SCHIZO_UEAFSR_BMSK) >>
416 (afsr & SCHIZO_UEAFSR_QOFF) >>
417 (afsr & SCHIZO_UEAFSR_AID) >> 2
418 printk("%s: partial[%d] owned_in[%d] m
419 pbm->name,
420 (afsr & SCHIZO_UEAFSR_PARTIAL)
421 (afsr & SCHIZO_UEAFSR_OWNEDIN)
422 (afsr & SCHIZO_UEAFSR_MTAG) >>
423 (afsr & SCHIZO_UEAFSR_MTAGSYND)
424 (afsr & SCHIZO_UEAFSR_ECCSYND)
425 printk("%s: UE AFAR [%016lx]\n", pbm->
426 printk("%s: UE Secondary errors [", pb
427 reported = 0;
428 if (afsr & SCHIZO_UEAFSR_SPIO) {
429 reported++;
430 printk("(PIO)");
431 }
432 if (afsr & SCHIZO_UEAFSR_SDMA) {
433 reported++;
434 printk("(DMA)");
435 }
436 if (!reported)
437 printk("(none)");
438 printk("]\n");
439
440 /* Interrogate IOMMU for error status.
441 schizo_check_iommu_error(pbm, UE_ERR);
442
443 return IRQ_HANDLED;
444 }
445
446 #define SCHIZO_CE_AFSR 0x10040UL
447 #define SCHIZO_CE_AFAR 0x10048UL
448
449 #define SCHIZO_CEAFSR_PPIO 0x800000000000
450 #define SCHIZO_CEAFSR_PDRD 0x400000000000
451 #define SCHIZO_CEAFSR_PDWR 0x200000000000
452 #define SCHIZO_CEAFSR_SPIO 0x100000000000
453 #define SCHIZO_CEAFSR_SDMA 0x080000000000
454 #define SCHIZO_CEAFSR_ERRPNDG 0x030000000000
455 #define SCHIZO_CEAFSR_BMSK 0x000003ff0000
456 #define SCHIZO_CEAFSR_QOFF 0x00000000c000
457 #define SCHIZO_CEAFSR_AID 0x000000001f00
458 #define SCHIZO_CEAFSR_PARTIAL 0x000000000080
459 #define SCHIZO_CEAFSR_OWNEDIN 0x000000000040
460 #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f
461 #define SCHIZO_CEAFSR_MTAG 0x000000000000
462 #define SCHIZO_CEAFSR_ECCSYND 0x000000000000
463
464 static irqreturn_t schizo_ce_intr(int irq, voi
465 {
466 struct pci_pbm_info *pbm = dev_id;
467 unsigned long afsr_reg = pbm->controll
468 unsigned long afar_reg = pbm->controll
469 unsigned long afsr, afar, error_bits;
470 int reported, limit;
471
472 /* Latch error status. */
473 afar = upa_readq(afar_reg);
474
475 /* If either of the error pending bits
476 * AFSR, the error status is being act
477 * the hardware and we must re-read to
478 */
479 limit = 1000;
480 do {
481 afsr = upa_readq(afsr_reg);
482 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG
483
484 /* Clear primary/secondary error statu
485 error_bits = afsr &
486 (SCHIZO_CEAFSR_PPIO | SCHIZO_C
487 SCHIZO_CEAFSR_SPIO | SCHIZO_C
488 if (!error_bits)
489 return IRQ_NONE;
490 upa_writeq(error_bits, afsr_reg);
491
492 /* Log the error. */
493 printk("%s: Correctable Error, primary
494 pbm->name,
495 (((error_bits & SCHIZO_CEAFSR_P
496 "PIO" :
497 ((error_bits & SCHIZO_CEAFSR_
498 "DMA Read" :
499 ((error_bits & SCHIZO_CEAFSR
500 "DMA Write" : "???")))));
501
502 /* XXX Use syndrome and afar to print
503 * XXX UDB CE trap handler does... -Da
504 */
505 printk("%s: bytemask[%04lx] qword_offs
506 pbm->name,
507 (afsr & SCHIZO_UEAFSR_BMSK) >>
508 (afsr & SCHIZO_UEAFSR_QOFF) >>
509 (afsr & SCHIZO_UEAFSR_AID) >> 2
510 printk("%s: partial[%d] owned_in[%d] m
511 pbm->name,
512 (afsr & SCHIZO_UEAFSR_PARTIAL)
513 (afsr & SCHIZO_UEAFSR_OWNEDIN)
514 (afsr & SCHIZO_UEAFSR_MTAG) >>
515 (afsr & SCHIZO_UEAFSR_MTAGSYND)
516 (afsr & SCHIZO_UEAFSR_ECCSYND)
517 printk("%s: CE AFAR [%016lx]\n", pbm->
518 printk("%s: CE Secondary errors [", pb
519 reported = 0;
520 if (afsr & SCHIZO_CEAFSR_SPIO) {
521 reported++;
522 printk("(PIO)");
523 }
524 if (afsr & SCHIZO_CEAFSR_SDMA) {
525 reported++;
526 printk("(DMA)");
527 }
528 if (!reported)
529 printk("(none)");
530 printk("]\n");
531
532 return IRQ_HANDLED;
533 }
534
535 #define SCHIZO_PCI_AFSR 0x2010UL
536 #define SCHIZO_PCI_AFAR 0x2018UL
537
538 #define SCHIZO_PCIAFSR_PMA 0x800000000000
539 #define SCHIZO_PCIAFSR_PTA 0x400000000000
540 #define SCHIZO_PCIAFSR_PRTRY 0x200000000000
541 #define SCHIZO_PCIAFSR_PPERR 0x100000000000
542 #define SCHIZO_PCIAFSR_PTTO 0x080000000000
543 #define SCHIZO_PCIAFSR_PUNUS 0x040000000000
544 #define SCHIZO_PCIAFSR_SMA 0x020000000000
545 #define SCHIZO_PCIAFSR_STA 0x010000000000
546 #define SCHIZO_PCIAFSR_SRTRY 0x008000000000
547 #define SCHIZO_PCIAFSR_SPERR 0x004000000000
548 #define SCHIZO_PCIAFSR_STTO 0x002000000000
549 #define SCHIZO_PCIAFSR_SUNUS 0x001000000000
550 #define SCHIZO_PCIAFSR_BMSK 0x000003ff0000
551 #define SCHIZO_PCIAFSR_BLK 0x000000008000
552 #define SCHIZO_PCIAFSR_CFG 0x000000004000
553 #define SCHIZO_PCIAFSR_MEM 0x000000002000
554 #define SCHIZO_PCIAFSR_IO 0x000000001000
555
556 #define SCHIZO_PCI_CTRL (0x2000UL)
557 #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL)
558 #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL)
559 #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL
560 #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL)
561 #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL)
562 #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL)
563 #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL)
564 #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL)
565 #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL)
566 #define SCHIZO_PCICTRL_SERR (1UL << 34UL)
567 #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL)
568 #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL)
569 #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL)
570 #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL)
571 #define SCHIZO_PCICTRL_PTO (3UL << 24UL)
572 #define SCHIZO_PCICTRL_PTO_SHIFT 24UL
573 #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL)
574 #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL)
575 #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL)
576 #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL)
577 #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL)
578 #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL)
579 #define SCHIZO_PCICTRL_EEN (1UL << 17UL)
580 #define SCHIZO_PCICTRL_PARK (1UL << 16UL)
581 #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL)
582 #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL
583 #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL
584
585 static irqreturn_t schizo_pcierr_intr_other(st
586 {
587 unsigned long csr_reg, csr, csr_error_
588 irqreturn_t ret = IRQ_NONE;
589 u32 stat;
590
591 csr_reg = pbm->pbm_regs + SCHIZO_PCI_C
592 csr = upa_readq(csr_reg);
593 csr_error_bits =
594 csr & (SCHIZO_PCICTRL_BUS_UNUS
595 SCHIZO_PCICTRL_TTO_ERR
596 SCHIZO_PCICTRL_RTRY_ERR
597 SCHIZO_PCICTRL_DTO_ERR
598 SCHIZO_PCICTRL_SBH_ERR
599 SCHIZO_PCICTRL_SERR);
600 if (csr_error_bits) {
601 /* Clear the errors. */
602 upa_writeq(csr, csr_reg);
603
604 /* Log 'em. */
605 if (csr_error_bits & SCHIZO_PC
606 printk("%s: Bus unusab
607 pbm->name);
608 if (csr_error_bits & SCHIZO_PC
609 printk("%s: PCI TRDY#
610 pbm->name);
611 if (csr_error_bits & SCHIZO_PC
612 printk("%s: PCI excess
613 pbm->name);
614 if (csr_error_bits & SCHIZO_PC
615 printk("%s: PCI discar
616 pbm->name);
617 if (csr_error_bits & SCHIZO_PC
618 printk("%s: PCI stream
619 pbm->name);
620 if (csr_error_bits & SCHIZO_PC
621 printk("%s: PCI SERR s
622 pbm->name);
623 ret = IRQ_HANDLED;
624 }
625 pbm->pci_ops->read(pbm->pci_bus, 0, PC
626 if (stat & (PCI_STATUS_PARITY |
627 PCI_STATUS_SIG_TARGET_ABOR
628 PCI_STATUS_REC_TARGET_ABOR
629 PCI_STATUS_REC_MASTER_ABOR
630 PCI_STATUS_SIG_SYSTEM_ERRO
631 printk("%s: PCI bus error, PCI
632 pbm->name, stat);
633 pbm->pci_ops->write(pbm->pci_b
634 ret = IRQ_HANDLED;
635 }
636 return ret;
637 }
638
639 static irqreturn_t schizo_pcierr_intr(int irq,
640 {
641 struct pci_pbm_info *pbm = dev_id;
642 unsigned long afsr_reg, afar_reg, base
643 unsigned long afsr, afar, error_bits;
644 int reported;
645
646 base = pbm->pbm_regs;
647
648 afsr_reg = base + SCHIZO_PCI_AFSR;
649 afar_reg = base + SCHIZO_PCI_AFAR;
650
651 /* Latch error status. */
652 afar = upa_readq(afar_reg);
653 afsr = upa_readq(afsr_reg);
654
655 /* Clear primary/secondary error statu
656 error_bits = afsr &
657 (SCHIZO_PCIAFSR_PMA | SCHIZO_P
658 SCHIZO_PCIAFSR_PRTRY | SCHIZO
659 SCHIZO_PCIAFSR_PTTO | SCHIZO_
660 SCHIZO_PCIAFSR_SMA | SCHIZO_P
661 SCHIZO_PCIAFSR_SRTRY | SCHIZO
662 SCHIZO_PCIAFSR_STTO | SCHIZO_
663 if (!error_bits)
664 return schizo_pcierr_intr_othe
665 upa_writeq(error_bits, afsr_reg);
666
667 /* Log the error. */
668 printk("%s: PCI Error, primary error t
669 pbm->name,
670 (((error_bits & SCHIZO_PCIAFSR_
671 "Master Abort" :
672 ((error_bits & SCHIZO_PCIAFSR
673 "Target Abort" :
674 ((error_bits & SCHIZO_PCIAFS
675 "Excessive Retries" :
676 ((error_bits & SCHIZO_PCIAF
677 "Parity Error" :
678 ((error_bits & SCHIZO_PCIA
679 "Timeout" :
680 ((error_bits & SCHIZO_PCI
681 "Bus Unusable" : "???"))
682 printk("%s: bytemask[%04lx] was_block(
683 pbm->name,
684 (afsr & SCHIZO_PCIAFSR_BMSK) >>
685 (afsr & SCHIZO_PCIAFSR_BLK) ? 1
686 ((afsr & SCHIZO_PCIAFSR_CFG) ?
687 "Config" :
688 ((afsr & SCHIZO_PCIAFSR_MEM) ?
689 "Memory" :
690 ((afsr & SCHIZO_PCIAFSR_IO) ?
691 "I/O" : "???"))));
692 printk("%s: PCI AFAR [%016lx]\n",
693 pbm->name, afar);
694 printk("%s: PCI Secondary errors [",
695 pbm->name);
696 reported = 0;
697 if (afsr & SCHIZO_PCIAFSR_SMA) {
698 reported++;
699 printk("(Master Abort)");
700 }
701 if (afsr & SCHIZO_PCIAFSR_STA) {
702 reported++;
703 printk("(Target Abort)");
704 }
705 if (afsr & SCHIZO_PCIAFSR_SRTRY) {
706 reported++;
707 printk("(Excessive Retries)");
708 }
709 if (afsr & SCHIZO_PCIAFSR_SPERR) {
710 reported++;
711 printk("(Parity Error)");
712 }
713 if (afsr & SCHIZO_PCIAFSR_STTO) {
714 reported++;
715 printk("(Timeout)");
716 }
717 if (afsr & SCHIZO_PCIAFSR_SUNUS) {
718 reported++;
719 printk("(Bus Unusable)");
720 }
721 if (!reported)
722 printk("(none)");
723 printk("]\n");
724
725 /* For the error types shown, scan PBM
726 * which have logged that error type.
727 */
728
729 /* If we see a Target Abort, this coul
730 * IOMMU translation error of some sor
731 * useful to log this information as u
732 * a bug in the IOMMU support code or
733 */
734 if (error_bits & (SCHIZO_PCIAFSR_PTA |
735 schizo_check_iommu_error(pbm,
736 pci_scan_for_target_abort(pbm,
737 }
738 if (error_bits & (SCHIZO_PCIAFSR_PMA |
739 pci_scan_for_master_abort(pbm,
740
741 /* For excessive retries, PSYCHO/PBM w
742 * and there is no way to specifically
743 * retries in the config space status
744 * we hope is that we'll catch it via
745 * abort events.
746 */
747
748 if (error_bits & (SCHIZO_PCIAFSR_PPERR
749 pci_scan_for_parity_error(pbm,
750
751 return IRQ_HANDLED;
752 }
753
754 #define SCHIZO_SAFARI_ERRLOG 0x10018UL
755
756 #define SAFARI_ERRLOG_ERROUT 0x800000000000
757
758 #define BUS_ERROR_BADCMD 0x400000000000
759 #define BUS_ERROR_SSMDIS 0x200000000000
760 #define BUS_ERROR_BADMA 0x100000000000
761 #define BUS_ERROR_BADMB 0x080000000000
762 #define BUS_ERROR_BADMC 0x040000000000
763 #define BUS_ERROR_SNOOP_GR 0x000000000020
764 #define BUS_ERROR_SNOOP_PCI 0x000000000010
765 #define BUS_ERROR_SNOOP_RD 0x000000000008
766 #define BUS_ERROR_SNOOP_RDS 0x000000000002
767 #define BUS_ERROR_SNOOP_RDSA 0x000000000001
768 #define BUS_ERROR_SNOOP_OWN 0x000000000000
769 #define BUS_ERROR_SNOOP_RDO 0x000000000000
770 #define BUS_ERROR_CPU1PS 0x000000000000
771 #define BUS_ERROR_WDATA_PERR 0x000000000000
772 #define BUS_ERROR_CPU1PB 0x000000000000
773 #define BUS_ERROR_CTRL_PERR 0x000000000000
774 #define BUS_ERROR_CPU0PS 0x000000000000
775 #define BUS_ERROR_SNOOP_ERR 0x000000000000
776 #define BUS_ERROR_CPU0PB 0x000000000000
777 #define BUS_ERROR_JBUS_ILL_B 0x000000000000
778 #define BUS_ERROR_CIQTO 0x000000000000
779 #define BUS_ERROR_LPQTO 0x000000000000
780 #define BUS_ERROR_JBUS_ILL_C 0x000000000000
781 #define BUS_ERROR_SFPQTO 0x000000000000
782 #define BUS_ERROR_UFPQTO 0x000000000000
783 #define BUS_ERROR_RD_PERR 0x000000000000
784 #define BUS_ERROR_APERR 0x000000000000
785 #define BUS_ERROR_UNMAP 0x000000000000
786 #define BUS_ERROR_BUSERR 0x000000000000
787 #define BUS_ERROR_TIMEOUT 0x000000000000
788 #define BUS_ERROR_ILL 0x000000000000
789
790 /* We only expect UNMAP errors here. The rest
791 * are marked fatal and thus cause a system re
792 */
793 static irqreturn_t schizo_safarierr_intr(int i
794 {
795 struct pci_pbm_info *pbm = dev_id;
796 u64 errlog;
797
798 errlog = upa_readq(pbm->controller_reg
799 upa_writeq(errlog & ~(SAFARI_ERRLOG_ER
800 pbm->controller_regs + SCHI
801
802 if (!(errlog & BUS_ERROR_UNMAP)) {
803 printk("%s: Unexpected Safari/
804 pbm->name, errlog);
805
806 return IRQ_HANDLED;
807 }
808
809 printk("%s: Safari/JBUS interrupt, UNM
810 pbm->name);
811 schizo_check_iommu_error(pbm, SAFARI_E
812
813 return IRQ_HANDLED;
814 }
815
816 /* Nearly identical to PSYCHO equivalents... *
817 #define SCHIZO_ECC_CTRL 0x10020UL
818 #define SCHIZO_ECCCTRL_EE 0x80000000000
819 #define SCHIZO_ECCCTRL_UE 0x40000000000
820 #define SCHIZO_ECCCTRL_CE 0x20000000000
821
822 #define SCHIZO_SAFARI_ERRCTRL 0x10008UL
823 #define SCHIZO_SAFERRCTRL_EN 0x80000000000
824 #define SCHIZO_SAFARI_IRQCTRL 0x10010UL
825 #define SCHIZO_SAFIRQCTRL_EN 0x80000000000
826
827 static int pbm_routes_this_ino(struct pci_pbm_
828 {
829 ino &= IMAP_INO;
830
831 if (pbm->ino_bitmap & (1UL << ino))
832 return 1;
833
834 return 0;
835 }
836
837 /* How the Tomatillo IRQs are routed around is
838 *
839 * All the Tomatillo devices I see in prtconf
840 * a single PCI bus unit attached to it. It w
841 * devices because their PortID (ie. JBUS ID)
842 * and thus the registers are mapped to totall
843 *
844 * However, two Tomatillo's look "similar" in
845 * in their PortID is the lowest bit.
846 *
847 * So if we were to ignore this lower bit, it
848 * PCI bus units of the same Tomatillo. I sti
849 * figured this out...
850 */
851 static void tomatillo_register_error_handlers(
852 {
853 struct platform_device *op = of_find_d
854 u64 tmp, err_mask, err_no_mask;
855 int err;
856
857 /* Tomatillo IRQ property layout is:
858 * 0: PCIERR
859 * 1: UE ERR
860 * 2: CE ERR
861 * 3: SERR
862 * 4: POWER FAIL?
863 */
864
865 if (pbm_routes_this_ino(pbm, SCHIZO_UE
866 err = request_irq(op->archdata
867 "TOMATILLO_U
868 if (err)
869 printk(KERN_WARNING "%
870 "err=%d\n", pbm
871 }
872 if (pbm_routes_this_ino(pbm, SCHIZO_CE
873 err = request_irq(op->archdata
874 "TOMATILLO_C
875 if (err)
876 printk(KERN_WARNING "%
877 "err=%d\n", pbm
878 }
879 err = 0;
880 if (pbm_routes_this_ino(pbm, SCHIZO_PC
881 err = request_irq(op->archdata
882 "TOMATILLO_P
883 } else if (pbm_routes_this_ino(pbm, SC
884 err = request_irq(op->archdata
885 "TOMATILLO_P
886 }
887 if (err)
888 printk(KERN_WARNING "%s: Could
889 "err=%d\n", pbm->name,
890
891 if (pbm_routes_this_ino(pbm, SCHIZO_SE
892 err = request_irq(op->archdata
893 "TOMATILLO_S
894 if (err)
895 printk(KERN_WARNING "%
896 "err=%d\n", pbm
897 }
898
899 /* Enable UE and CE interrupts for con
900 upa_writeq((SCHIZO_ECCCTRL_EE |
901 SCHIZO_ECCCTRL_UE |
902 SCHIZO_ECCCTRL_CE), pbm->c
903
904 /* Enable PCI Error interrupts and cle
905 * bits.
906 */
907 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
908 SCHIZO_PCICTRL_TTO_ERR |
909 SCHIZO_PCICTRL_RTRY_ERR |
910 SCHIZO_PCICTRL_SERR |
911 SCHIZO_PCICTRL_EEN);
912
913 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
914
915 tmp = upa_readq(pbm->pbm_regs + SCHIZO
916 tmp |= err_mask;
917 tmp &= ~err_no_mask;
918 upa_writeq(tmp, pbm->pbm_regs + SCHIZO
919
920 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZ
921 SCHIZO_PCIAFSR_PRTRY | SCH
922 SCHIZO_PCIAFSR_PTTO |
923 SCHIZO_PCIAFSR_SMA | SCHIZ
924 SCHIZO_PCIAFSR_SRTRY | SCH
925 SCHIZO_PCIAFSR_STTO);
926
927 upa_writeq(err_mask, pbm->pbm_regs + S
928
929 err_mask = (BUS_ERROR_BADCMD | BUS_ERR
930 BUS_ERROR_SNOOP_PCI | BUS_
931 BUS_ERROR_SNOOP_RDS | BUS_
932 BUS_ERROR_SNOOP_OWN | BUS_
933 BUS_ERROR_WDATA_PERR | BUS
934 BUS_ERROR_SNOOP_ERR | BUS_
935 BUS_ERROR_JBUS_ILL_C | BUS
936 BUS_ERROR_APERR | BUS_ERRO
937 BUS_ERROR_BUSERR | BUS_ERR
938
939 upa_writeq((SCHIZO_SAFERRCTRL_EN | err
940 pbm->controller_regs + SCHI
941
942 upa_writeq((SCHIZO_SAFIRQCTRL_EN | (BU
943 pbm->controller_regs + SCHI
944 }
945
946 static void schizo_register_error_handlers(str
947 {
948 struct platform_device *op = of_find_d
949 u64 tmp, err_mask, err_no_mask;
950 int err;
951
952 /* Schizo IRQ property layout is:
953 * 0: PCIERR
954 * 1: UE ERR
955 * 2: CE ERR
956 * 3: SERR
957 * 4: POWER FAIL?
958 */
959
960 if (pbm_routes_this_ino(pbm, SCHIZO_UE
961 err = request_irq(op->archdata
962 "SCHIZO_UE",
963 if (err)
964 printk(KERN_WARNING "%
965 "err=%d\n", pbm
966 }
967 if (pbm_routes_this_ino(pbm, SCHIZO_CE
968 err = request_irq(op->archdata
969 "SCHIZO_CE",
970 if (err)
971 printk(KERN_WARNING "%
972 "err=%d\n", pbm
973 }
974 err = 0;
975 if (pbm_routes_this_ino(pbm, SCHIZO_PC
976 err = request_irq(op->archdata
977 "SCHIZO_PCIE
978 } else if (pbm_routes_this_ino(pbm, SC
979 err = request_irq(op->archdata
980 "SCHIZO_PCIE
981 }
982 if (err)
983 printk(KERN_WARNING "%s: Could
984 "err=%d\n", pbm->name,
985
986 if (pbm_routes_this_ino(pbm, SCHIZO_SE
987 err = request_irq(op->archdata
988 "SCHIZO_SERR
989 if (err)
990 printk(KERN_WARNING "%
991 "err=%d\n", pbm
992 }
993
994 /* Enable UE and CE interrupts for con
995 upa_writeq((SCHIZO_ECCCTRL_EE |
996 SCHIZO_ECCCTRL_UE |
997 SCHIZO_ECCCTRL_CE), pbm->c
998
999 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1000 SCHIZO_PCICTRL_ESLCK |
1001 SCHIZO_PCICTRL_TTO_ERR |
1002 SCHIZO_PCICTRL_RTRY_ERR |
1003 SCHIZO_PCICTRL_SBH_ERR |
1004 SCHIZO_PCICTRL_SERR |
1005 SCHIZO_PCICTRL_EEN);
1006
1007 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR
1008 SCHIZO_PCICTRL_SBH_INT
1009
1010 /* Enable PCI Error interrupts and cl
1011 * bits for each PBM.
1012 */
1013 tmp = upa_readq(pbm->pbm_regs + SCHIZ
1014 tmp |= err_mask;
1015 tmp &= ~err_no_mask;
1016 upa_writeq(tmp, pbm->pbm_regs + SCHIZ
1017
1018 upa_writeq((SCHIZO_PCIAFSR_PMA | SCHI
1019 SCHIZO_PCIAFSR_PRTRY | SC
1020 SCHIZO_PCIAFSR_PTTO | SCH
1021 SCHIZO_PCIAFSR_SMA | SCHI
1022 SCHIZO_PCIAFSR_SRTRY | SC
1023 SCHIZO_PCIAFSR_STTO | SCH
1024 pbm->pbm_regs + SCHIZO_PCI
1025
1026 /* Make all Safari error conditions f
1027 * errors which we make generate inte
1028 */
1029 err_mask = (BUS_ERROR_BADCMD | BUS_ER
1030 BUS_ERROR_BADMA | BUS_ERR
1031 BUS_ERROR_BADMC |
1032 BUS_ERROR_CPU1PS | BUS_ER
1033 BUS_ERROR_CPU0PS | BUS_ER
1034 BUS_ERROR_CIQTO |
1035 BUS_ERROR_LPQTO | BUS_ERR
1036 BUS_ERROR_UFPQTO | BUS_ER
1037 BUS_ERROR_BUSERR | BUS_ER
1038 BUS_ERROR_ILL);
1039 #if 1
1040 /* XXX Something wrong with some Exca
1041 * XXX Sun is shipping. The behavior
1042 * XXX machine is that both CPU1 pari
1043 * XXX are set and are immediately se
1044 * XXX their error status bits are cl
1045 * XXX ignore them for now. -DaveM
1046 */
1047 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_
1048 BUS_ERROR_CPU0PS | BUS_
1049 #endif
1050
1051 upa_writeq((SCHIZO_SAFERRCTRL_EN | er
1052 pbm->controller_regs + SCH
1053 }
1054
1055 static void pbm_config_busmastering(struct pc
1056 {
1057 u8 *addr;
1058
1059 /* Set cache-line size to 64 bytes, t
1060 * a nop but I do it for completeness
1061 */
1062 addr = schizo_pci_config_mkaddr(pbm,
1063 0, PC
1064 pci_config_write8(addr, 64 / sizeof(u
1065
1066 /* Set PBM latency timer to 64 PCI cl
1067 addr = schizo_pci_config_mkaddr(pbm,
1068 0, PC
1069 pci_config_write8(addr, 64);
1070 }
1071
1072 static void schizo_scan_bus(struct pci_pbm_in
1073 {
1074 pbm_config_busmastering(pbm);
1075 pbm->is_66mhz_capable =
1076 (of_find_property(pbm->op->de
1077 != NULL);
1078
1079 pbm->pci_bus = pci_scan_one_pbm(pbm,
1080
1081 if (pbm->chip_type == PBM_CHIP_TYPE_T
1082 tomatillo_register_error_hand
1083 else
1084 schizo_register_error_handler
1085 }
1086
1087 #define SCHIZO_STRBUF_CONTROL (0x02
1088 #define SCHIZO_STRBUF_FLUSH (0x02
1089 #define SCHIZO_STRBUF_FSYNC (0x02
1090 #define SCHIZO_STRBUF_CTXFLUSH (0x02
1091 #define SCHIZO_STRBUF_CTXMATCH (0x10
1092
1093 static void schizo_pbm_strbuf_init(struct pci
1094 {
1095 unsigned long base = pbm->pbm_regs;
1096 u64 control;
1097
1098 if (pbm->chip_type == PBM_CHIP_TYPE_T
1099 /* TOMATILLO lacks streaming
1100 return;
1101 }
1102
1103 /* SCHIZO has context flushing. */
1104 pbm->stc.strbuf_control = bas
1105 pbm->stc.strbuf_pflush = bas
1106 pbm->stc.strbuf_fsync = bas
1107 pbm->stc.strbuf_ctxflush = bas
1108 pbm->stc.strbuf_ctxmatch_base = bas
1109
1110 pbm->stc.strbuf_flushflag = (volatile
1111 ((((unsigned long)&pbm->stc._
1112 + 63UL)
1113 & ~63UL);
1114 pbm->stc.strbuf_flushflag_pa = (unsig
1115 __pa(pbm->stc.strbuf_flushfla
1116
1117 /* Turn off LRU locking and diag mode
1118 * streaming buffer and leave the rer
1119 * setting however OBP set it.
1120 */
1121 control = upa_readq(pbm->stc.strbuf_c
1122 control &= ~(SCHIZO_STRBUF_CTRL_LPTR
1123 SCHIZO_STRBUF_CTRL_LENAB
1124 SCHIZO_STRBUF_CTRL_DENAB
1125 control |= SCHIZO_STRBUF_CTRL_ENAB;
1126 upa_writeq(control, pbm->stc.strbuf_c
1127
1128 pbm->stc.strbuf_enabled = 1;
1129 }
1130
1131 #define SCHIZO_IOMMU_CONTROL (0x00
1132 #define SCHIZO_IOMMU_TSBBASE (0x00
1133 #define SCHIZO_IOMMU_FLUSH (0x00
1134 #define SCHIZO_IOMMU_CTXFLUSH (0x00
1135
1136 static int schizo_pbm_iommu_init(struct pci_p
1137 {
1138 static const u32 vdma_default[] = { 0
1139 unsigned long i, tagbase, database;
1140 struct iommu *iommu = pbm->iommu;
1141 int tsbsize, err;
1142 const u32 *vdma;
1143 u32 dma_mask;
1144 u64 control;
1145
1146 vdma = of_get_property(pbm->op->dev.o
1147 if (!vdma)
1148 vdma = vdma_default;
1149
1150 dma_mask = vdma[0];
1151 switch (vdma[1]) {
1152 case 0x20000000:
1153 dma_mask |= 0x1ffffff
1154 tsbsize = 64;
1155 break;
1156
1157 case 0x40000000:
1158 dma_mask |= 0x3ffffff
1159 tsbsize = 128;
1160 break;
1161
1162 case 0x80000000:
1163 dma_mask |= 0x7ffffff
1164 tsbsize = 128;
1165 break;
1166
1167 default:
1168 printk(KERN_ERR PFX "
1169 return -EINVAL;
1170 }
1171
1172 /* Register addresses, SCHIZO has iom
1173 iommu->iommu_control = pbm->pbm_regs
1174 iommu->iommu_tsbbase = pbm->pbm_regs
1175 iommu->iommu_flush = pbm->pbm_regs
1176 iommu->iommu_tags = iommu->iommu_
1177 iommu->iommu_ctxflush = pbm->pbm_regs
1178
1179 /* We use the main control/status reg
1180 * completion register.
1181 */
1182 iommu->write_complete_reg = pbm->cont
1183
1184 /*
1185 * Invalidate TLB Entries.
1186 */
1187 control = upa_readq(iommu->iommu_cont
1188 control |= SCHIZO_IOMMU_CTRL_DENAB;
1189 upa_writeq(control, iommu->iommu_cont
1190
1191 tagbase = SCHIZO_IOMMU_TAG, database
1192
1193 for (i = 0; i < 16; i++) {
1194 upa_writeq(0, pbm->pbm_regs +
1195 upa_writeq(0, pbm->pbm_regs +
1196 }
1197
1198 /* Leave diag mode enabled for full-f
1199 * in pci_iommu.c
1200 */
1201 err = iommu_table_init(iommu, tsbsize
1202 pbm->numa_node
1203 if (err) {
1204 printk(KERN_ERR PFX "iommu_ta
1205 return err;
1206 }
1207
1208 upa_writeq(__pa(iommu->page_table), i
1209
1210 control = upa_readq(iommu->iommu_cont
1211 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ
1212 switch (tsbsize) {
1213 case 64:
1214 control |= SCHIZO_IOMMU_TSBSZ
1215 break;
1216 case 128:
1217 control |= SCHIZO_IOMMU_TSBSZ
1218 break;
1219 }
1220
1221 control |= SCHIZO_IOMMU_CTRL_ENAB;
1222 upa_writeq(control, iommu->iommu_cont
1223
1224 return 0;
1225 }
1226
1227 #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
1228 #define SCHIZO_IRQ_RETRY_INF 0xffUL
1229
1230 #define SCHIZO_PCI_DIAG (0x20
1231 #define SCHIZO_PCIDIAG_D_BADECC (1UL
1232 #define SCHIZO_PCIDIAG_D_BYPASS (1UL
1233 #define SCHIZO_PCIDIAG_D_TTO (1UL
1234 #define SCHIZO_PCIDIAG_D_RTRYARB (1UL
1235 #define SCHIZO_PCIDIAG_D_RETRY (1UL
1236 #define SCHIZO_PCIDIAG_D_INTSYNC (1UL
1237 #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL
1238 #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL
1239 #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL
1240
1241 #define TOMATILLO_PCI_IOC_CSR (0x22
1242 #define TOMATILLO_IOC_PART_WPENAB 0x000
1243 #define TOMATILLO_IOC_RDMULT_PENAB 0x000
1244 #define TOMATILLO_IOC_RDONE_PENAB 0x000
1245 #define TOMATILLO_IOC_RDLINE_PENAB 0x000
1246 #define TOMATILLO_IOC_RDMULT_PLEN 0x000
1247 #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1248 #define TOMATILLO_IOC_RDONE_PLEN 0x000
1249 #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1250 #define TOMATILLO_IOC_RDLINE_PLEN 0x000
1251 #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1252 #define TOMATILLO_IOC_PREF_OFF 0x000
1253 #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1254 #define TOMATILLO_IOC_RDMULT_CPENAB 0x000
1255 #define TOMATILLO_IOC_RDONE_CPENAB 0x000
1256 #define TOMATILLO_IOC_RDLINE_CPENAB 0x000
1257
1258 #define TOMATILLO_PCI_IOC_TDIAG (0x22
1259 #define TOMATILLO_PCI_IOC_DDIAG (0x22
1260
1261 static void schizo_pbm_hw_init(struct pci_pbm
1262 {
1263 u64 tmp;
1264
1265 upa_writeq(5, pbm->pbm_regs + SCHIZO_
1266
1267 tmp = upa_readq(pbm->pbm_regs + SCHIZ
1268
1269 /* Enable arbiter for all PCI slots.
1270 tmp |= 0xff;
1271
1272 if (pbm->chip_type == PBM_CHIP_TYPE_T
1273 pbm->chip_version >= 0x2)
1274 tmp |= 0x3UL << SCHIZO_PCICTR
1275
1276 if (!of_property_read_bool(pbm->op->d
1277 tmp |= SCHIZO_PCICTRL_PARK;
1278 else
1279 tmp &= ~SCHIZO_PCICTRL_PARK;
1280
1281 if (pbm->chip_type == PBM_CHIP_TYPE_T
1282 pbm->chip_version <= 0x1)
1283 tmp |= SCHIZO_PCICTRL_DTO_INT
1284 else
1285 tmp &= ~SCHIZO_PCICTRL_DTO_IN
1286
1287 if (pbm->chip_type == PBM_CHIP_TYPE_T
1288 tmp |= (SCHIZO_PCICTRL_MRM_PR
1289 SCHIZO_PCICTRL_RDO_PR
1290 SCHIZO_PCICTRL_RDL_PR
1291
1292 upa_writeq(tmp, pbm->pbm_regs + SCHIZ
1293
1294 tmp = upa_readq(pbm->pbm_regs + SCHIZ
1295 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1296 SCHIZO_PCIDIAG_D_RETRY |
1297 SCHIZO_PCIDIAG_D_INTSYNC);
1298 upa_writeq(tmp, pbm->pbm_regs + SCHIZ
1299
1300 if (pbm->chip_type == PBM_CHIP_TYPE_T
1301 /* Clear prefetch lengths to
1302 * Jalapeno...
1303 */
1304 tmp = (TOMATILLO_IOC_PART_WPE
1305 (1 << TOMATILLO_IOC_PR
1306 TOMATILLO_IOC_RDMULT_C
1307 TOMATILLO_IOC_RDONE_CP
1308 TOMATILLO_IOC_RDLINE_C
1309
1310 upa_writeq(tmp, pbm->pbm_regs
1311 }
1312 }
1313
1314 static int schizo_pbm_init(struct pci_pbm_inf
1315 struct platform_de
1316 int chip_type)
1317 {
1318 const struct linux_prom64_registers *
1319 struct device_node *dp = op->dev.of_n
1320 const char *chipset_name;
1321 int err;
1322
1323 switch (chip_type) {
1324 case PBM_CHIP_TYPE_TOMATILLO:
1325 chipset_name = "TOMATILLO";
1326 break;
1327
1328 case PBM_CHIP_TYPE_SCHIZO_PLUS:
1329 chipset_name = "SCHIZO+";
1330 break;
1331
1332 case PBM_CHIP_TYPE_SCHIZO:
1333 default:
1334 chipset_name = "SCHIZO";
1335 break;
1336 }
1337
1338 /* For SCHIZO, three OBP regs:
1339 * 1) PBM controller regs
1340 * 2) Schizo front-end controller reg
1341 * 3) PBM PCI config space
1342 *
1343 * For TOMATILLO, four OBP regs:
1344 * 1) PBM controller regs
1345 * 2) Tomatillo front-end controller
1346 * 3) PBM PCI config space
1347 * 4) Ichip regs
1348 */
1349 regs = of_get_property(dp, "reg", NUL
1350
1351 pbm->next = pci_pbm_root;
1352 pci_pbm_root = pbm;
1353
1354 pbm->numa_node = NUMA_NO_NODE;
1355
1356 pbm->pci_ops = &sun4u_pci_ops;
1357 pbm->config_space_reg_bits = 8;
1358
1359 pbm->index = pci_num_pbms++;
1360
1361 pbm->portid = portid;
1362 pbm->op = op;
1363
1364 pbm->chip_type = chip_type;
1365 pbm->chip_version = of_getintprop_def
1366 pbm->chip_revision = of_getintprop_de
1367
1368 pbm->pbm_regs = regs[0].phys_addr;
1369 pbm->controller_regs = regs[1].phys_a
1370
1371 if (chip_type == PBM_CHIP_TYPE_TOMATI
1372 pbm->sync_reg = regs[3].phys_
1373
1374 pbm->name = dp->full_name;
1375
1376 printk("%s: %s PCI Bus Module ver[%x:
1377 pbm->name, chipset_name,
1378 pbm->chip_version, pbm->chip_r
1379
1380 schizo_pbm_hw_init(pbm);
1381
1382 pci_determine_mem_io_space(pbm);
1383
1384 pci_get_pbm_props(pbm);
1385
1386 err = schizo_pbm_iommu_init(pbm);
1387 if (err)
1388 return err;
1389
1390 schizo_pbm_strbuf_init(pbm);
1391
1392 schizo_scan_bus(pbm, &op->dev);
1393
1394 return 0;
1395 }
1396
1397 static inline int portid_compare(u32 x, u32 y
1398 {
1399 if (chip_type == PBM_CHIP_TYPE_TOMATI
1400 if (x == (y ^ 1))
1401 return 1;
1402 return 0;
1403 }
1404 return (x == y);
1405 }
1406
1407 static struct pci_pbm_info *schizo_find_sibli
1408 {
1409 struct pci_pbm_info *pbm;
1410
1411 for (pbm = pci_pbm_root; pbm; pbm = p
1412 if (portid_compare(pbm->porti
1413 return pbm;
1414 }
1415 return NULL;
1416 }
1417
1418 static int __schizo_init(struct platform_devi
1419 {
1420 struct device_node *dp = op->dev.of_n
1421 struct pci_pbm_info *pbm;
1422 struct iommu *iommu;
1423 u32 portid;
1424 int err;
1425
1426 portid = of_getintprop_default(dp, "p
1427
1428 err = -ENOMEM;
1429 pbm = kzalloc(sizeof(*pbm), GFP_KERNE
1430 if (!pbm) {
1431 printk(KERN_ERR PFX "Cannot a
1432 goto out_err;
1433 }
1434
1435 pbm->sibling = schizo_find_sibling(po
1436
1437 iommu = kzalloc(sizeof(struct iommu),
1438 if (!iommu) {
1439 printk(KERN_ERR PFX "Cannot a
1440 goto out_free_pbm;
1441 }
1442
1443 pbm->iommu = iommu;
1444
1445 if (schizo_pbm_init(pbm, op, portid,
1446 goto out_free_iommu;
1447
1448 if (pbm->sibling)
1449 pbm->sibling->sibling = pbm;
1450
1451 dev_set_drvdata(&op->dev, pbm);
1452
1453 return 0;
1454
1455 out_free_iommu:
1456 kfree(pbm->iommu);
1457
1458 out_free_pbm:
1459 kfree(pbm);
1460
1461 out_err:
1462 return err;
1463 }
1464
1465 static int schizo_probe(struct platform_devic
1466 {
1467 unsigned long chip_type = (unsigned l
1468
1469 if (!chip_type)
1470 return -EINVAL;
1471 return __schizo_init(op, chip_type);
1472 }
1473
1474 /* The ordering of this table is very importa
1475 * nodes announce that they are compatible wi
1476 * and pci108e,8001. So list the chips in re
1477 * order.
1478 */
1479 static const struct of_device_id schizo_match
1480 {
1481 .name = "pci",
1482 .compatible = "pci108e,a801",
1483 .data = (void *) PBM_CHIP_TYP
1484 },
1485 {
1486 .name = "pci",
1487 .compatible = "pci108e,8002",
1488 .data = (void *) PBM_CHIP_TYP
1489 },
1490 {
1491 .name = "pci",
1492 .compatible = "pci108e,8001",
1493 .data = (void *) PBM_CHIP_TYP
1494 },
1495 {},
1496 };
1497
1498 static struct platform_driver schizo_driver =
1499 .driver = {
1500 .name = DRIVER_NAME,
1501 .of_match_table = schizo_matc
1502 },
1503 .probe = schizo_probe,
1504 };
1505
1506 static int __init schizo_init(void)
1507 {
1508 return platform_driver_register(&schi
1509 }
1510
1511 subsys_initcall(schizo_init);
1512
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