1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* ld script for sparc32/sparc64 kernel */ <<
3 <<
4 #include <asm-generic/vmlinux.lds.h> 2 #include <asm-generic/vmlinux.lds.h>
5 <<
6 #include <asm/page.h> <<
7 #include <asm/thread_info.h> 3 #include <asm/thread_info.h>
>> 4 #include <asm/cache.h>
>> 5 #include <asm/page.h>
>> 6 #include <asm/setup.h>
8 7
9 #ifdef CONFIG_SPARC32 !! 8 OUTPUT_FORMAT("elf64-alpha")
10 #define INITIAL_ADDRESS 0x10000 + SIZEOF_HEAD !! 9 OUTPUT_ARCH(alpha)
11 #define TEXTSTART 0xf0004000 !! 10 ENTRY(__start)
12 !! 11 PHDRS { kernel PT_LOAD; note PT_NOTE; }
13 #define SMP_CACHE_BYTES_SHIFT 5 <<
14 <<
15 #else <<
16 #define SMP_CACHE_BYTES_SHIFT 6 <<
17 #define INITIAL_ADDRESS 0x4000 <<
18 #define TEXTSTART 0x0000000000404000 <<
19 <<
20 #endif <<
21 <<
22 #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_ <<
23 <<
24 #ifdef CONFIG_SPARC32 <<
25 OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "e <<
26 OUTPUT_ARCH(sparc) <<
27 ENTRY(_start) <<
28 jiffies = jiffies_64 + 4; <<
29 #else <<
30 /* sparc64 */ <<
31 OUTPUT_FORMAT("elf64-sparc", "elf64-sparc", "e <<
32 OUTPUT_ARCH(sparc:v9a) <<
33 ENTRY(_start) <<
34 jiffies = jiffies_64; 12 jiffies = jiffies_64;
35 #endif <<
36 <<
37 #ifdef CONFIG_SPARC64 <<
38 ASSERT((swapper_tsb == 0x0000000000408000), "E <<
39 #endif <<
40 <<
41 SECTIONS 13 SECTIONS
42 { 14 {
43 #ifdef CONFIG_SPARC64 !! 15 #ifdef CONFIG_ALPHA_LEGACY_START_ADDRESS
44 swapper_pg_dir = 0x0000000000402000; !! 16 . = 0xfffffc0000310000;
>> 17 #else
>> 18 . = 0xfffffc0001010000;
45 #endif 19 #endif
46 . = INITIAL_ADDRESS; !! 20
47 .text TEXTSTART : !! 21 _text = .; /* Text and read-only data */
48 { !! 22 .text : {
49 _text = .; <<
50 HEAD_TEXT 23 HEAD_TEXT
51 TEXT_TEXT 24 TEXT_TEXT
52 SCHED_TEXT 25 SCHED_TEXT
>> 26 CPUIDLE_TEXT
53 LOCK_TEXT 27 LOCK_TEXT
54 KPROBES_TEXT !! 28 *(.fixup)
55 IRQENTRY_TEXT <<
56 SOFTIRQENTRY_TEXT <<
57 *(.gnu.warning) 29 *(.gnu.warning)
58 } = 0 !! 30 } :kernel
59 _etext = .; !! 31 swapper_pg_dir = SWAPPER_PGD;
60 !! 32 _etext = .; /* End of text section */
61 RO_DATA(PAGE_SIZE) !! 33
62 !! 34 NOTES :kernel :note
63 /* Start of data section */ !! 35 .dummy : {
64 _sdata = .; !! 36 *(.dummy)
65 !! 37 } :kernel
66 .data1 : { <<
67 *(.data1) <<
68 } <<
69 RW_DATA(SMP_CACHE_BYTES, 0, THREAD_SIZ <<
70 <<
71 /* End of data section */ <<
72 _edata = .; <<
73 38
74 .fixup : { !! 39 RODATA
75 __start___fixup = .; <<
76 *(.fixup) <<
77 __stop___fixup = .; <<
78 } <<
79 EXCEPTION_TABLE(16) 40 EXCEPTION_TABLE(16)
80 41
81 . = ALIGN(PAGE_SIZE); !! 42 /* Will be freed after init */
82 __init_begin = ALIGN(PAGE_SIZE); 43 __init_begin = ALIGN(PAGE_SIZE);
83 INIT_TEXT_SECTION(PAGE_SIZE) 44 INIT_TEXT_SECTION(PAGE_SIZE)
84 __init_text_end = .; <<
85 INIT_DATA_SECTION(16) 45 INIT_DATA_SECTION(16)
>> 46 PERCPU_SECTION(L1_CACHE_BYTES)
>> 47 /* Align to THREAD_SIZE rather than PAGE_SIZE here so any padding page
>> 48 needed for the THREAD_SIZE aligned init_task gets freed after init */
>> 49 . = ALIGN(THREAD_SIZE);
>> 50 __init_end = .;
>> 51 /* Freed after init ends here */
86 52
87 . = ALIGN(4); !! 53 _sdata = .; /* Start of rw data section */
88 .tsb_ldquad_phys_patch : { !! 54 _data = .;
89 __tsb_ldquad_phys_patch = .; !! 55 RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
90 *(.tsb_ldquad_phys_patch) <<
91 __tsb_ldquad_phys_patch_end = <<
92 } <<
93 56
94 .tsb_phys_patch : { !! 57 .got : {
95 __tsb_phys_patch = .; !! 58 *(.got)
96 *(.tsb_phys_patch) <<
97 __tsb_phys_patch_end = .; <<
98 } 59 }
99 !! 60 .sdata : {
100 .cpuid_patch : { !! 61 *(.sdata)
101 __cpuid_patch = .; <<
102 *(.cpuid_patch) <<
103 __cpuid_patch_end = .; <<
104 } 62 }
>> 63 _edata = .; /* End of data section */
105 64
106 .sun4v_1insn_patch : { !! 65 BSS_SECTION(0, 0, 0)
107 __sun4v_1insn_patch = .; !! 66 _end = .;
108 *(.sun4v_1insn_patch) <<
109 __sun4v_1insn_patch_end = .; <<
110 } <<
111 .sun4v_2insn_patch : { <<
112 __sun4v_2insn_patch = .; <<
113 *(.sun4v_2insn_patch) <<
114 __sun4v_2insn_patch_end = .; <<
115 } <<
116 .leon_1insn_patch : { <<
117 __leon_1insn_patch = .; <<
118 *(.leon_1insn_patch) <<
119 __leon_1insn_patch_end = .; <<
120 } <<
121 .swapper_tsb_phys_patch : { <<
122 __swapper_tsb_phys_patch = .; <<
123 *(.swapper_tsb_phys_patch) <<
124 __swapper_tsb_phys_patch_end = <<
125 } <<
126 .swapper_4m_tsb_phys_patch : { <<
127 __swapper_4m_tsb_phys_patch = <<
128 *(.swapper_4m_tsb_phys_patch) <<
129 __swapper_4m_tsb_phys_patch_en <<
130 } <<
131 .popc_3insn_patch : { <<
132 __popc_3insn_patch = .; <<
133 *(.popc_3insn_patch) <<
134 __popc_3insn_patch_end = .; <<
135 } <<
136 .popc_6insn_patch : { <<
137 __popc_6insn_patch = .; <<
138 *(.popc_6insn_patch) <<
139 __popc_6insn_patch_end = .; <<
140 } <<
141 .pause_3insn_patch : { <<
142 __pause_3insn_patch = .; <<
143 *(.pause_3insn_patch) <<
144 __pause_3insn_patch_end = .; <<
145 } <<
146 .sun_m7_1insn_patch : { <<
147 __sun_m7_1insn_patch = .; <<
148 *(.sun_m7_1insn_patch) <<
149 __sun_m7_1insn_patch_end = .; <<
150 } <<
151 .sun_m7_2insn_patch : { <<
152 __sun_m7_2insn_patch = .; <<
153 *(.sun_m7_2insn_patch) <<
154 __sun_m7_2insn_patch_end = .; <<
155 } <<
156 .get_tick_patch : { <<
157 __get_tick_patch = .; <<
158 *(.get_tick_patch) <<
159 __get_tick_patch_end = .; <<
160 } <<
161 .pud_huge_patch : { <<
162 __pud_huge_patch = .; <<
163 *(.pud_huge_patch) <<
164 __pud_huge_patch_end = .; <<
165 } <<
166 .fast_win_ctrl_1insn_patch : { <<
167 __fast_win_ctrl_1insn_patch = <<
168 *(.fast_win_ctrl_1insn_patch) <<
169 __fast_win_ctrl_1insn_patch_en <<
170 } <<
171 PERCPU_SECTION(SMP_CACHE_BYTES) <<
172 67
173 . = ALIGN(PAGE_SIZE); !! 68 .mdebug 0 : {
174 .exit.text : { !! 69 *(.mdebug)
175 EXIT_TEXT <<
176 } 70 }
177 !! 71 .note 0 : {
178 .exit.data : { !! 72 *(.note)
179 EXIT_DATA <<
180 } 73 }
181 74
182 . = ALIGN(PAGE_SIZE); <<
183 __init_end = .; <<
184 BSS_SECTION(0, 0, 0) <<
185 _end = . ; <<
186 <<
187 STABS_DEBUG 75 STABS_DEBUG
188 DWARF_DEBUG 76 DWARF_DEBUG
189 ELF_DETAILS <<
190 77
191 DISCARDS 78 DISCARDS
192 } 79 }
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