1 /* SPDX-License-Identifier: GPL-2.0 */ !! 1 #include <asm/asm-offsets.h>
2 /* ld script for sparc32/sparc64 kernel */ <<
3 <<
4 #include <asm-generic/vmlinux.lds.h> <<
5 <<
6 #include <asm/page.h> <<
7 #include <asm/thread_info.h> 2 #include <asm/thread_info.h>
8 3
9 #ifdef CONFIG_SPARC32 !! 4 #define PAGE_SIZE _PAGE_SIZE
10 #define INITIAL_ADDRESS 0x10000 + SIZEOF_HEAD <<
11 #define TEXTSTART 0xf0004000 <<
12 <<
13 #define SMP_CACHE_BYTES_SHIFT 5 <<
14 <<
15 #else <<
16 #define SMP_CACHE_BYTES_SHIFT 6 <<
17 #define INITIAL_ADDRESS 0x4000 <<
18 #define TEXTSTART 0x0000000000404000 <<
19 5
20 #endif !! 6 /*
>> 7 * Put .bss..swapper_pg_dir as the first thing in .bss. This will
>> 8 * ensure that it has .bss alignment (64K).
>> 9 */
>> 10 #define BSS_FIRST_SECTIONS *(.bss..swapper_pg_dir)
21 11
22 #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_ !! 12 #include <asm-generic/vmlinux.lds.h>
23 13
24 #ifdef CONFIG_SPARC32 !! 14 #undef mips
25 OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "e !! 15 #define mips mips
26 OUTPUT_ARCH(sparc) !! 16 OUTPUT_ARCH(mips)
27 ENTRY(_start) !! 17 ENTRY(kernel_entry)
28 jiffies = jiffies_64 + 4; !! 18 PHDRS {
>> 19 text PT_LOAD FLAGS(7); /* RWX */
>> 20 #ifndef CONFIG_CAVIUM_OCTEON_SOC
>> 21 note PT_NOTE FLAGS(4); /* R__ */
>> 22 #endif /* CAVIUM_OCTEON_SOC */
>> 23 }
>> 24
>> 25 #ifdef CONFIG_32BIT
>> 26 #ifdef CONFIG_CPU_LITTLE_ENDIAN
>> 27 jiffies = jiffies_64;
>> 28 #else
>> 29 jiffies = jiffies_64 + 4;
>> 30 #endif
29 #else 31 #else
30 /* sparc64 */ !! 32 jiffies = jiffies_64;
31 OUTPUT_FORMAT("elf64-sparc", "elf64-sparc", "e <<
32 OUTPUT_ARCH(sparc:v9a) <<
33 ENTRY(_start) <<
34 jiffies = jiffies_64; <<
35 #endif <<
36 <<
37 #ifdef CONFIG_SPARC64 <<
38 ASSERT((swapper_tsb == 0x0000000000408000), "E <<
39 #endif 33 #endif
40 34
41 SECTIONS 35 SECTIONS
42 { 36 {
43 #ifdef CONFIG_SPARC64 !! 37 #ifdef CONFIG_BOOT_ELF64
44 swapper_pg_dir = 0x0000000000402000; !! 38 /* Read-only sections, merged into text segment: */
>> 39 /* . = 0xc000000000000000; */
>> 40
>> 41 /* This is the value for an Origin kernel, taken from an IRIX kernel. */
>> 42 /* . = 0xc00000000001c000; */
>> 43
>> 44 /* Set the vaddr for the text segment to a value
>> 45 * >= 0xa800 0000 0001 9000 if no symmon is going to configured
>> 46 * >= 0xa800 0000 0030 0000 otherwise
>> 47 */
>> 48
>> 49 /* . = 0xa800000000300000; */
>> 50 . = 0xffffffff80300000;
45 #endif 51 #endif
46 . = INITIAL_ADDRESS; !! 52 . = VMLINUX_LOAD_ADDRESS;
47 .text TEXTSTART : !! 53 /* read-only */
48 { !! 54 _text = .; /* Text and read-only data */
49 _text = .; !! 55 .text : {
50 HEAD_TEXT <<
51 TEXT_TEXT 56 TEXT_TEXT
52 SCHED_TEXT 57 SCHED_TEXT
>> 58 CPUIDLE_TEXT
53 LOCK_TEXT 59 LOCK_TEXT
54 KPROBES_TEXT 60 KPROBES_TEXT
55 IRQENTRY_TEXT 61 IRQENTRY_TEXT
56 SOFTIRQENTRY_TEXT 62 SOFTIRQENTRY_TEXT
>> 63 *(.text.*)
>> 64 *(.fixup)
57 *(.gnu.warning) 65 *(.gnu.warning)
58 } = 0 !! 66 } :text = 0
59 _etext = .; !! 67 _etext = .; /* End of text section */
60 <<
61 RO_DATA(PAGE_SIZE) <<
62 <<
63 /* Start of data section */ <<
64 _sdata = .; <<
65 <<
66 .data1 : { <<
67 *(.data1) <<
68 } <<
69 RW_DATA(SMP_CACHE_BYTES, 0, THREAD_SIZ <<
70 <<
71 /* End of data section */ <<
72 _edata = .; <<
73 68
74 .fixup : { <<
75 __start___fixup = .; <<
76 *(.fixup) <<
77 __stop___fixup = .; <<
78 } <<
79 EXCEPTION_TABLE(16) 69 EXCEPTION_TABLE(16)
80 70
81 . = ALIGN(PAGE_SIZE); !! 71 /* Exception table for data bus errors */
82 __init_begin = ALIGN(PAGE_SIZE); !! 72 __dbe_table : {
>> 73 __start___dbe_table = .;
>> 74 *(__dbe_table)
>> 75 __stop___dbe_table = .;
>> 76 }
>> 77
>> 78 #ifdef CONFIG_CAVIUM_OCTEON_SOC
>> 79 #define NOTES_HEADER
>> 80 #else /* CONFIG_CAVIUM_OCTEON_SOC */
>> 81 #define NOTES_HEADER :note
>> 82 #endif /* CONFIG_CAVIUM_OCTEON_SOC */
>> 83 NOTES :text NOTES_HEADER
>> 84 .dummy : { *(.dummy) } :text
>> 85
>> 86 _sdata = .; /* Start of data section */
>> 87 RODATA
>> 88
>> 89 /* writeable */
>> 90 .data : { /* Data */
>> 91 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
>> 92
>> 93 INIT_TASK_DATA(THREAD_SIZE)
>> 94 NOSAVE_DATA
>> 95 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 96 READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 97 DATA_DATA
>> 98 CONSTRUCTORS
>> 99 }
>> 100 _gp = . + 0x8000;
>> 101 .lit8 : {
>> 102 *(.lit8)
>> 103 }
>> 104 .lit4 : {
>> 105 *(.lit4)
>> 106 }
>> 107 /* We want the small data sections together, so single-instruction offsets
>> 108 can access them all, and initialized data all before uninitialized, so
>> 109 we can shorten the on-disk segment size. */
>> 110 .sdata : {
>> 111 *(.sdata)
>> 112 }
>> 113 _edata = .; /* End of data section */
>> 114
>> 115 /* will be freed after init */
>> 116 . = ALIGN(PAGE_SIZE); /* Init code and data */
>> 117 __init_begin = .;
83 INIT_TEXT_SECTION(PAGE_SIZE) 118 INIT_TEXT_SECTION(PAGE_SIZE)
84 __init_text_end = .; <<
85 INIT_DATA_SECTION(16) 119 INIT_DATA_SECTION(16)
86 120
87 . = ALIGN(4); 121 . = ALIGN(4);
88 .tsb_ldquad_phys_patch : { !! 122 .mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) {
89 __tsb_ldquad_phys_patch = .; !! 123 __mips_machines_start = .;
90 *(.tsb_ldquad_phys_patch) !! 124 *(.mips.machines.init)
91 __tsb_ldquad_phys_patch_end = !! 125 __mips_machines_end = .;
92 } <<
93 <<
94 .tsb_phys_patch : { <<
95 __tsb_phys_patch = .; <<
96 *(.tsb_phys_patch) <<
97 __tsb_phys_patch_end = .; <<
98 } <<
99 <<
100 .cpuid_patch : { <<
101 __cpuid_patch = .; <<
102 *(.cpuid_patch) <<
103 __cpuid_patch_end = .; <<
104 } <<
105 <<
106 .sun4v_1insn_patch : { <<
107 __sun4v_1insn_patch = .; <<
108 *(.sun4v_1insn_patch) <<
109 __sun4v_1insn_patch_end = .; <<
110 } <<
111 .sun4v_2insn_patch : { <<
112 __sun4v_2insn_patch = .; <<
113 *(.sun4v_2insn_patch) <<
114 __sun4v_2insn_patch_end = .; <<
115 } <<
116 .leon_1insn_patch : { <<
117 __leon_1insn_patch = .; <<
118 *(.leon_1insn_patch) <<
119 __leon_1insn_patch_end = .; <<
120 } <<
121 .swapper_tsb_phys_patch : { <<
122 __swapper_tsb_phys_patch = .; <<
123 *(.swapper_tsb_phys_patch) <<
124 __swapper_tsb_phys_patch_end = <<
125 } <<
126 .swapper_4m_tsb_phys_patch : { <<
127 __swapper_4m_tsb_phys_patch = <<
128 *(.swapper_4m_tsb_phys_patch) <<
129 __swapper_4m_tsb_phys_patch_en <<
130 } <<
131 .popc_3insn_patch : { <<
132 __popc_3insn_patch = .; <<
133 *(.popc_3insn_patch) <<
134 __popc_3insn_patch_end = .; <<
135 } <<
136 .popc_6insn_patch : { <<
137 __popc_6insn_patch = .; <<
138 *(.popc_6insn_patch) <<
139 __popc_6insn_patch_end = .; <<
140 } <<
141 .pause_3insn_patch : { <<
142 __pause_3insn_patch = .; <<
143 *(.pause_3insn_patch) <<
144 __pause_3insn_patch_end = .; <<
145 } <<
146 .sun_m7_1insn_patch : { <<
147 __sun_m7_1insn_patch = .; <<
148 *(.sun_m7_1insn_patch) <<
149 __sun_m7_1insn_patch_end = .; <<
150 } <<
151 .sun_m7_2insn_patch : { <<
152 __sun_m7_2insn_patch = .; <<
153 *(.sun_m7_2insn_patch) <<
154 __sun_m7_2insn_patch_end = .; <<
155 } <<
156 .get_tick_patch : { <<
157 __get_tick_patch = .; <<
158 *(.get_tick_patch) <<
159 __get_tick_patch_end = .; <<
160 } <<
161 .pud_huge_patch : { <<
162 __pud_huge_patch = .; <<
163 *(.pud_huge_patch) <<
164 __pud_huge_patch_end = .; <<
165 } <<
166 .fast_win_ctrl_1insn_patch : { <<
167 __fast_win_ctrl_1insn_patch = <<
168 *(.fast_win_ctrl_1insn_patch) <<
169 __fast_win_ctrl_1insn_patch_en <<
170 } 126 }
171 PERCPU_SECTION(SMP_CACHE_BYTES) <<
172 127
173 . = ALIGN(PAGE_SIZE); !! 128 /* .exit.text is discarded at runtime, not link time, to deal with
>> 129 * references from .rodata
>> 130 */
174 .exit.text : { 131 .exit.text : {
175 EXIT_TEXT 132 EXIT_TEXT
176 } 133 }
177 <<
178 .exit.data : { 134 .exit.data : {
179 EXIT_DATA 135 EXIT_DATA
180 } 136 }
>> 137 #ifdef CONFIG_SMP
>> 138 PERCPU_SECTION(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 139 #endif
>> 140
>> 141 #ifdef CONFIG_RELOCATABLE
>> 142 . = ALIGN(4);
>> 143
>> 144 .data.reloc : {
>> 145 _relocation_start = .;
>> 146 /*
>> 147 * Space for relocation table
>> 148 * This needs to be filled so that the
>> 149 * relocs tool can overwrite the content.
>> 150 * An invalid value is left at the start of the
>> 151 * section to abort relocation if the table
>> 152 * has not been filled in.
>> 153 */
>> 154 LONG(0xFFFFFFFF);
>> 155 FILL(0);
>> 156 . += CONFIG_RELOCATION_TABLE_SIZE - 4;
>> 157 _relocation_end = .;
>> 158 }
>> 159 #endif
181 160
182 . = ALIGN(PAGE_SIZE); !! 161 #ifdef CONFIG_MIPS_RAW_APPENDED_DTB
>> 162 __appended_dtb = .;
>> 163 /* leave space for appended DTB */
>> 164 . += 0x100000;
>> 165 #elif defined(CONFIG_MIPS_ELF_APPENDED_DTB)
>> 166 .appended_dtb : AT(ADDR(.appended_dtb) - LOAD_OFFSET) {
>> 167 *(.appended_dtb)
>> 168 KEEP(*(.appended_dtb))
>> 169 }
>> 170 #endif
>> 171 /*
>> 172 * Align to 64K in attempt to eliminate holes before the
>> 173 * .bss..swapper_pg_dir section at the start of .bss. This
>> 174 * also satisfies PAGE_SIZE alignment as the largest page size
>> 175 * allowed is 64K.
>> 176 */
>> 177 . = ALIGN(0x10000);
183 __init_end = .; 178 __init_end = .;
184 BSS_SECTION(0, 0, 0) !! 179 /* freed after init ends here */
>> 180
>> 181 /*
>> 182 * Force .bss to 64K alignment so that .bss..swapper_pg_dir
>> 183 * gets that alignment. .sbss should be empty, so there will be
>> 184 * no holes after __init_end. */
>> 185 BSS_SECTION(0, 0x10000, 0)
>> 186
185 _end = . ; 187 _end = . ;
186 188
>> 189 /* These mark the ABI of the kernel for debuggers. */
>> 190 .mdebug.abi32 : {
>> 191 KEEP(*(.mdebug.abi32))
>> 192 }
>> 193 .mdebug.abi64 : {
>> 194 KEEP(*(.mdebug.abi64))
>> 195 }
>> 196
>> 197 /* This is the MIPS specific mdebug section. */
>> 198 .mdebug : {
>> 199 *(.mdebug)
>> 200 }
>> 201
187 STABS_DEBUG 202 STABS_DEBUG
188 DWARF_DEBUG 203 DWARF_DEBUG
189 ELF_DETAILS <<
190 204
>> 205 /* These must appear regardless of . */
>> 206 .gptab.sdata : {
>> 207 *(.gptab.data)
>> 208 *(.gptab.sdata)
>> 209 }
>> 210 .gptab.sbss : {
>> 211 *(.gptab.bss)
>> 212 *(.gptab.sbss)
>> 213 }
>> 214
>> 215 /* Sections to be discarded */
191 DISCARDS 216 DISCARDS
>> 217 /DISCARD/ : {
>> 218 /* ABI crap starts here */
>> 219 *(.MIPS.abiflags)
>> 220 *(.MIPS.options)
>> 221 *(.options)
>> 222 *(.pdr)
>> 223 *(.reginfo)
>> 224 *(.eh_frame)
>> 225 }
192 } 226 }
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