1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* ld script for sparc32/sparc64 kernel */ !! 2 #include <asm/asm-offsets.h>
3 <<
4 #include <asm-generic/vmlinux.lds.h> <<
5 <<
6 #include <asm/page.h> <<
7 #include <asm/thread_info.h> 3 #include <asm/thread_info.h>
8 4
9 #ifdef CONFIG_SPARC32 !! 5 #define PAGE_SIZE _PAGE_SIZE
10 #define INITIAL_ADDRESS 0x10000 + SIZEOF_HEAD <<
11 #define TEXTSTART 0xf0004000 <<
12 <<
13 #define SMP_CACHE_BYTES_SHIFT 5 <<
14 <<
15 #else <<
16 #define SMP_CACHE_BYTES_SHIFT 6 <<
17 #define INITIAL_ADDRESS 0x4000 <<
18 #define TEXTSTART 0x0000000000404000 <<
19 6
20 #endif !! 7 /*
>> 8 * Put .bss..swapper_pg_dir as the first thing in .bss. This will
>> 9 * ensure that it has .bss alignment (64K).
>> 10 */
>> 11 #define BSS_FIRST_SECTIONS *(.bss..swapper_pg_dir)
21 12
22 #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_ !! 13 #include <asm-generic/vmlinux.lds.h>
23 14
24 #ifdef CONFIG_SPARC32 !! 15 #undef mips
25 OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "e !! 16 #define mips mips
26 OUTPUT_ARCH(sparc) !! 17 OUTPUT_ARCH(mips)
27 ENTRY(_start) !! 18 ENTRY(kernel_entry)
28 jiffies = jiffies_64 + 4; !! 19 PHDRS {
>> 20 text PT_LOAD FLAGS(7); /* RWX */
>> 21 #ifndef CONFIG_CAVIUM_OCTEON_SOC
>> 22 note PT_NOTE FLAGS(4); /* R__ */
>> 23 #endif /* CAVIUM_OCTEON_SOC */
>> 24 }
>> 25
>> 26 #ifdef CONFIG_32BIT
>> 27 #ifdef CONFIG_CPU_LITTLE_ENDIAN
>> 28 jiffies = jiffies_64;
>> 29 #else
>> 30 jiffies = jiffies_64 + 4;
>> 31 #endif
29 #else 32 #else
30 /* sparc64 */ !! 33 jiffies = jiffies_64;
31 OUTPUT_FORMAT("elf64-sparc", "elf64-sparc", "e <<
32 OUTPUT_ARCH(sparc:v9a) <<
33 ENTRY(_start) <<
34 jiffies = jiffies_64; <<
35 #endif <<
36 <<
37 #ifdef CONFIG_SPARC64 <<
38 ASSERT((swapper_tsb == 0x0000000000408000), "E <<
39 #endif 34 #endif
40 35
41 SECTIONS 36 SECTIONS
42 { 37 {
43 #ifdef CONFIG_SPARC64 !! 38 #ifdef CONFIG_BOOT_ELF64
44 swapper_pg_dir = 0x0000000000402000; !! 39 /* Read-only sections, merged into text segment: */
>> 40 /* . = 0xc000000000000000; */
>> 41
>> 42 /* This is the value for an Origin kernel, taken from an IRIX kernel. */
>> 43 /* . = 0xc00000000001c000; */
>> 44
>> 45 /* Set the vaddr for the text segment to a value
>> 46 * >= 0xa800 0000 0001 9000 if no symmon is going to configured
>> 47 * >= 0xa800 0000 0030 0000 otherwise
>> 48 */
>> 49
>> 50 /* . = 0xa800000000300000; */
>> 51 . = 0xffffffff80300000;
45 #endif 52 #endif
46 . = INITIAL_ADDRESS; !! 53 . = VMLINUX_LOAD_ADDRESS;
47 .text TEXTSTART : !! 54 /* read-only */
48 { !! 55 _text = .; /* Text and read-only data */
49 _text = .; !! 56 .text : {
50 HEAD_TEXT <<
51 TEXT_TEXT 57 TEXT_TEXT
52 SCHED_TEXT 58 SCHED_TEXT
>> 59 CPUIDLE_TEXT
53 LOCK_TEXT 60 LOCK_TEXT
54 KPROBES_TEXT 61 KPROBES_TEXT
55 IRQENTRY_TEXT 62 IRQENTRY_TEXT
56 SOFTIRQENTRY_TEXT 63 SOFTIRQENTRY_TEXT
>> 64 *(.text.*)
>> 65 *(.fixup)
57 *(.gnu.warning) 66 *(.gnu.warning)
58 } = 0 !! 67 } :text = 0
59 _etext = .; !! 68 _etext = .; /* End of text section */
60 <<
61 RO_DATA(PAGE_SIZE) <<
62 <<
63 /* Start of data section */ <<
64 _sdata = .; <<
65 <<
66 .data1 : { <<
67 *(.data1) <<
68 } <<
69 RW_DATA(SMP_CACHE_BYTES, 0, THREAD_SIZ <<
70 <<
71 /* End of data section */ <<
72 _edata = .; <<
73 69
74 .fixup : { <<
75 __start___fixup = .; <<
76 *(.fixup) <<
77 __stop___fixup = .; <<
78 } <<
79 EXCEPTION_TABLE(16) 70 EXCEPTION_TABLE(16)
80 71
81 . = ALIGN(PAGE_SIZE); !! 72 /* Exception table for data bus errors */
82 __init_begin = ALIGN(PAGE_SIZE); !! 73 __dbe_table : {
>> 74 __start___dbe_table = .;
>> 75 *(__dbe_table)
>> 76 __stop___dbe_table = .;
>> 77 }
>> 78
>> 79 #ifdef CONFIG_CAVIUM_OCTEON_SOC
>> 80 #define NOTES_HEADER
>> 81 #else /* CONFIG_CAVIUM_OCTEON_SOC */
>> 82 #define NOTES_HEADER :note
>> 83 #endif /* CONFIG_CAVIUM_OCTEON_SOC */
>> 84 NOTES :text NOTES_HEADER
>> 85 .dummy : { *(.dummy) } :text
>> 86
>> 87 _sdata = .; /* Start of data section */
>> 88 RODATA
>> 89
>> 90 /* writeable */
>> 91 .data : { /* Data */
>> 92 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
>> 93
>> 94 INIT_TASK_DATA(THREAD_SIZE)
>> 95 NOSAVE_DATA
>> 96 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 97 READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 98 DATA_DATA
>> 99 CONSTRUCTORS
>> 100 }
>> 101 BUG_TABLE
>> 102 _gp = . + 0x8000;
>> 103 .lit8 : {
>> 104 *(.lit8)
>> 105 }
>> 106 .lit4 : {
>> 107 *(.lit4)
>> 108 }
>> 109 /* We want the small data sections together, so single-instruction offsets
>> 110 can access them all, and initialized data all before uninitialized, so
>> 111 we can shorten the on-disk segment size. */
>> 112 .sdata : {
>> 113 *(.sdata)
>> 114 }
>> 115 _edata = .; /* End of data section */
>> 116
>> 117 /* will be freed after init */
>> 118 . = ALIGN(PAGE_SIZE); /* Init code and data */
>> 119 __init_begin = .;
83 INIT_TEXT_SECTION(PAGE_SIZE) 120 INIT_TEXT_SECTION(PAGE_SIZE)
84 __init_text_end = .; <<
85 INIT_DATA_SECTION(16) 121 INIT_DATA_SECTION(16)
86 122
87 . = ALIGN(4); 123 . = ALIGN(4);
88 .tsb_ldquad_phys_patch : { !! 124 .mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) {
89 __tsb_ldquad_phys_patch = .; !! 125 __mips_machines_start = .;
90 *(.tsb_ldquad_phys_patch) !! 126 *(.mips.machines.init)
91 __tsb_ldquad_phys_patch_end = !! 127 __mips_machines_end = .;
92 } <<
93 <<
94 .tsb_phys_patch : { <<
95 __tsb_phys_patch = .; <<
96 *(.tsb_phys_patch) <<
97 __tsb_phys_patch_end = .; <<
98 } <<
99 <<
100 .cpuid_patch : { <<
101 __cpuid_patch = .; <<
102 *(.cpuid_patch) <<
103 __cpuid_patch_end = .; <<
104 } <<
105 <<
106 .sun4v_1insn_patch : { <<
107 __sun4v_1insn_patch = .; <<
108 *(.sun4v_1insn_patch) <<
109 __sun4v_1insn_patch_end = .; <<
110 } <<
111 .sun4v_2insn_patch : { <<
112 __sun4v_2insn_patch = .; <<
113 *(.sun4v_2insn_patch) <<
114 __sun4v_2insn_patch_end = .; <<
115 } <<
116 .leon_1insn_patch : { <<
117 __leon_1insn_patch = .; <<
118 *(.leon_1insn_patch) <<
119 __leon_1insn_patch_end = .; <<
120 } <<
121 .swapper_tsb_phys_patch : { <<
122 __swapper_tsb_phys_patch = .; <<
123 *(.swapper_tsb_phys_patch) <<
124 __swapper_tsb_phys_patch_end = <<
125 } <<
126 .swapper_4m_tsb_phys_patch : { <<
127 __swapper_4m_tsb_phys_patch = <<
128 *(.swapper_4m_tsb_phys_patch) <<
129 __swapper_4m_tsb_phys_patch_en <<
130 } <<
131 .popc_3insn_patch : { <<
132 __popc_3insn_patch = .; <<
133 *(.popc_3insn_patch) <<
134 __popc_3insn_patch_end = .; <<
135 } <<
136 .popc_6insn_patch : { <<
137 __popc_6insn_patch = .; <<
138 *(.popc_6insn_patch) <<
139 __popc_6insn_patch_end = .; <<
140 } <<
141 .pause_3insn_patch : { <<
142 __pause_3insn_patch = .; <<
143 *(.pause_3insn_patch) <<
144 __pause_3insn_patch_end = .; <<
145 } <<
146 .sun_m7_1insn_patch : { <<
147 __sun_m7_1insn_patch = .; <<
148 *(.sun_m7_1insn_patch) <<
149 __sun_m7_1insn_patch_end = .; <<
150 } <<
151 .sun_m7_2insn_patch : { <<
152 __sun_m7_2insn_patch = .; <<
153 *(.sun_m7_2insn_patch) <<
154 __sun_m7_2insn_patch_end = .; <<
155 } <<
156 .get_tick_patch : { <<
157 __get_tick_patch = .; <<
158 *(.get_tick_patch) <<
159 __get_tick_patch_end = .; <<
160 } <<
161 .pud_huge_patch : { <<
162 __pud_huge_patch = .; <<
163 *(.pud_huge_patch) <<
164 __pud_huge_patch_end = .; <<
165 } <<
166 .fast_win_ctrl_1insn_patch : { <<
167 __fast_win_ctrl_1insn_patch = <<
168 *(.fast_win_ctrl_1insn_patch) <<
169 __fast_win_ctrl_1insn_patch_en <<
170 } 128 }
171 PERCPU_SECTION(SMP_CACHE_BYTES) <<
172 129
173 . = ALIGN(PAGE_SIZE); !! 130 /* .exit.text is discarded at runtime, not link time, to deal with
>> 131 * references from .rodata
>> 132 */
174 .exit.text : { 133 .exit.text : {
175 EXIT_TEXT 134 EXIT_TEXT
176 } 135 }
177 <<
178 .exit.data : { 136 .exit.data : {
179 EXIT_DATA 137 EXIT_DATA
180 } 138 }
>> 139 #ifdef CONFIG_SMP
>> 140 PERCPU_SECTION(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 141 #endif
>> 142
>> 143 #ifdef CONFIG_RELOCATABLE
>> 144 . = ALIGN(4);
>> 145
>> 146 .data.reloc : {
>> 147 _relocation_start = .;
>> 148 /*
>> 149 * Space for relocation table
>> 150 * This needs to be filled so that the
>> 151 * relocs tool can overwrite the content.
>> 152 * An invalid value is left at the start of the
>> 153 * section to abort relocation if the table
>> 154 * has not been filled in.
>> 155 */
>> 156 LONG(0xFFFFFFFF);
>> 157 FILL(0);
>> 158 . += CONFIG_RELOCATION_TABLE_SIZE - 4;
>> 159 _relocation_end = .;
>> 160 }
>> 161 #endif
181 162
182 . = ALIGN(PAGE_SIZE); !! 163 #ifdef CONFIG_MIPS_RAW_APPENDED_DTB
>> 164 __appended_dtb = .;
>> 165 /* leave space for appended DTB */
>> 166 . += 0x100000;
>> 167 #elif defined(CONFIG_MIPS_ELF_APPENDED_DTB)
>> 168 .appended_dtb : AT(ADDR(.appended_dtb) - LOAD_OFFSET) {
>> 169 *(.appended_dtb)
>> 170 KEEP(*(.appended_dtb))
>> 171 }
>> 172 #endif
>> 173 /*
>> 174 * Align to 64K in attempt to eliminate holes before the
>> 175 * .bss..swapper_pg_dir section at the start of .bss. This
>> 176 * also satisfies PAGE_SIZE alignment as the largest page size
>> 177 * allowed is 64K.
>> 178 */
>> 179 . = ALIGN(0x10000);
183 __init_end = .; 180 __init_end = .;
184 BSS_SECTION(0, 0, 0) !! 181 /* freed after init ends here */
>> 182
>> 183 /*
>> 184 * Force .bss to 64K alignment so that .bss..swapper_pg_dir
>> 185 * gets that alignment. .sbss should be empty, so there will be
>> 186 * no holes after __init_end. */
>> 187 BSS_SECTION(0, 0x10000, 8)
>> 188
185 _end = . ; 189 _end = . ;
186 190
>> 191 /* These mark the ABI of the kernel for debuggers. */
>> 192 .mdebug.abi32 : {
>> 193 KEEP(*(.mdebug.abi32))
>> 194 }
>> 195 .mdebug.abi64 : {
>> 196 KEEP(*(.mdebug.abi64))
>> 197 }
>> 198
>> 199 /* This is the MIPS specific mdebug section. */
>> 200 .mdebug : {
>> 201 *(.mdebug)
>> 202 }
>> 203
187 STABS_DEBUG 204 STABS_DEBUG
188 DWARF_DEBUG 205 DWARF_DEBUG
189 ELF_DETAILS <<
190 206
>> 207 /* These must appear regardless of . */
>> 208 .gptab.sdata : {
>> 209 *(.gptab.data)
>> 210 *(.gptab.sdata)
>> 211 }
>> 212 .gptab.sbss : {
>> 213 *(.gptab.bss)
>> 214 *(.gptab.sbss)
>> 215 }
>> 216
>> 217 /* Sections to be discarded */
191 DISCARDS 218 DISCARDS
>> 219 /DISCARD/ : {
>> 220 /* ABI crap starts here */
>> 221 *(.MIPS.abiflags)
>> 222 *(.MIPS.options)
>> 223 *(.options)
>> 224 *(.pdr)
>> 225 *(.reginfo)
>> 226 *(.eh_frame)
>> 227 }
192 } 228 }
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.