1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* ld script for sparc32/sparc64 kernel */ !! 2 #include <asm/asm-offsets.h>
3 <<
4 #include <asm-generic/vmlinux.lds.h> <<
5 <<
6 #include <asm/page.h> <<
7 #include <asm/thread_info.h> 3 #include <asm/thread_info.h>
8 4
9 #ifdef CONFIG_SPARC32 !! 5 #define PAGE_SIZE _PAGE_SIZE
10 #define INITIAL_ADDRESS 0x10000 + SIZEOF_HEAD <<
11 #define TEXTSTART 0xf0004000 <<
12 <<
13 #define SMP_CACHE_BYTES_SHIFT 5 <<
14 <<
15 #else <<
16 #define SMP_CACHE_BYTES_SHIFT 6 <<
17 #define INITIAL_ADDRESS 0x4000 <<
18 #define TEXTSTART 0x0000000000404000 <<
19 6
>> 7 /*
>> 8 * Put .bss..swapper_pg_dir as the first thing in .bss. This will
>> 9 * ensure that it has .bss alignment (64K).
>> 10 */
>> 11 #define BSS_FIRST_SECTIONS *(.bss..swapper_pg_dir)
>> 12
>> 13 /* Cavium Octeon should not have a separate PT_NOTE Program Header. */
>> 14 #ifndef CONFIG_CAVIUM_OCTEON_SOC
>> 15 #define EMITS_PT_NOTE
20 #endif 16 #endif
21 17
22 #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_ !! 18 #include <asm-generic/vmlinux.lds.h>
23 19
24 #ifdef CONFIG_SPARC32 !! 20 #undef mips
25 OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "e !! 21 #define mips mips
26 OUTPUT_ARCH(sparc) !! 22 OUTPUT_ARCH(mips)
27 ENTRY(_start) !! 23 ENTRY(kernel_entry)
28 jiffies = jiffies_64 + 4; !! 24 PHDRS {
>> 25 text PT_LOAD FLAGS(7); /* RWX */
>> 26 #ifndef CONFIG_CAVIUM_OCTEON_SOC
>> 27 note PT_NOTE FLAGS(4); /* R__ */
>> 28 #endif /* CAVIUM_OCTEON_SOC */
>> 29 }
>> 30
>> 31 #ifdef CONFIG_32BIT
>> 32 #ifdef CONFIG_CPU_LITTLE_ENDIAN
>> 33 jiffies = jiffies_64;
>> 34 #else
>> 35 jiffies = jiffies_64 + 4;
>> 36 #endif
29 #else 37 #else
30 /* sparc64 */ !! 38 jiffies = jiffies_64;
31 OUTPUT_FORMAT("elf64-sparc", "elf64-sparc", "e <<
32 OUTPUT_ARCH(sparc:v9a) <<
33 ENTRY(_start) <<
34 jiffies = jiffies_64; <<
35 #endif <<
36 <<
37 #ifdef CONFIG_SPARC64 <<
38 ASSERT((swapper_tsb == 0x0000000000408000), "E <<
39 #endif 39 #endif
40 40
41 SECTIONS 41 SECTIONS
42 { 42 {
43 #ifdef CONFIG_SPARC64 !! 43 #ifdef CONFIG_BOOT_ELF64
44 swapper_pg_dir = 0x0000000000402000; !! 44 /* Read-only sections, merged into text segment: */
>> 45 /* . = 0xc000000000000000; */
>> 46
>> 47 /* This is the value for an Origin kernel, taken from an IRIX kernel. */
>> 48 /* . = 0xc00000000001c000; */
>> 49
>> 50 /* Set the vaddr for the text segment to a value
>> 51 * >= 0xa800 0000 0001 9000 if no symmon is going to configured
>> 52 * >= 0xa800 0000 0030 0000 otherwise
>> 53 */
>> 54
>> 55 /* . = 0xa800000000300000; */
>> 56 . = 0xffffffff80300000;
45 #endif 57 #endif
46 . = INITIAL_ADDRESS; !! 58 . = VMLINUX_LOAD_ADDRESS;
47 .text TEXTSTART : !! 59 /* read-only */
48 { !! 60 _text = .; /* Text and read-only data */
49 _text = .; !! 61 .text : {
50 HEAD_TEXT <<
51 TEXT_TEXT 62 TEXT_TEXT
52 SCHED_TEXT 63 SCHED_TEXT
>> 64 CPUIDLE_TEXT
53 LOCK_TEXT 65 LOCK_TEXT
54 KPROBES_TEXT 66 KPROBES_TEXT
55 IRQENTRY_TEXT 67 IRQENTRY_TEXT
56 SOFTIRQENTRY_TEXT 68 SOFTIRQENTRY_TEXT
>> 69 *(.text.*)
>> 70 *(.fixup)
57 *(.gnu.warning) 71 *(.gnu.warning)
58 } = 0 !! 72 } :text = 0
59 _etext = .; !! 73 _etext = .; /* End of text section */
60 <<
61 RO_DATA(PAGE_SIZE) <<
62 <<
63 /* Start of data section */ <<
64 _sdata = .; <<
65 <<
66 .data1 : { <<
67 *(.data1) <<
68 } <<
69 RW_DATA(SMP_CACHE_BYTES, 0, THREAD_SIZ <<
70 74
71 /* End of data section */ <<
72 _edata = .; <<
73 <<
74 .fixup : { <<
75 __start___fixup = .; <<
76 *(.fixup) <<
77 __stop___fixup = .; <<
78 } <<
79 EXCEPTION_TABLE(16) 75 EXCEPTION_TABLE(16)
80 76
81 . = ALIGN(PAGE_SIZE); !! 77 /* Exception table for data bus errors */
82 __init_begin = ALIGN(PAGE_SIZE); !! 78 __dbe_table : {
>> 79 __start___dbe_table = .;
>> 80 KEEP(*(__dbe_table))
>> 81 __stop___dbe_table = .;
>> 82 }
>> 83
>> 84 _sdata = .; /* Start of data section */
>> 85 RO_DATA(4096)
>> 86
>> 87 /* writeable */
>> 88 .data : { /* Data */
>> 89 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
>> 90
>> 91 INIT_TASK_DATA(THREAD_SIZE)
>> 92 NOSAVE_DATA
>> 93 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 94 READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 95 DATA_DATA
>> 96 CONSTRUCTORS
>> 97 }
>> 98 BUG_TABLE
>> 99 _gp = . + 0x8000;
>> 100 .lit8 : {
>> 101 *(.lit8)
>> 102 }
>> 103 .lit4 : {
>> 104 *(.lit4)
>> 105 }
>> 106 /* We want the small data sections together, so single-instruction offsets
>> 107 can access them all, and initialized data all before uninitialized, so
>> 108 we can shorten the on-disk segment size. */
>> 109 .sdata : {
>> 110 *(.sdata)
>> 111 }
>> 112 _edata = .; /* End of data section */
>> 113
>> 114 /* will be freed after init */
>> 115 . = ALIGN(PAGE_SIZE); /* Init code and data */
>> 116 __init_begin = .;
83 INIT_TEXT_SECTION(PAGE_SIZE) 117 INIT_TEXT_SECTION(PAGE_SIZE)
84 __init_text_end = .; <<
85 INIT_DATA_SECTION(16) 118 INIT_DATA_SECTION(16)
86 119
87 . = ALIGN(4); 120 . = ALIGN(4);
88 .tsb_ldquad_phys_patch : { !! 121 .mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) {
89 __tsb_ldquad_phys_patch = .; !! 122 __mips_machines_start = .;
90 *(.tsb_ldquad_phys_patch) !! 123 KEEP(*(.mips.machines.init))
91 __tsb_ldquad_phys_patch_end = !! 124 __mips_machines_end = .;
92 } <<
93 <<
94 .tsb_phys_patch : { <<
95 __tsb_phys_patch = .; <<
96 *(.tsb_phys_patch) <<
97 __tsb_phys_patch_end = .; <<
98 } <<
99 <<
100 .cpuid_patch : { <<
101 __cpuid_patch = .; <<
102 *(.cpuid_patch) <<
103 __cpuid_patch_end = .; <<
104 } <<
105 <<
106 .sun4v_1insn_patch : { <<
107 __sun4v_1insn_patch = .; <<
108 *(.sun4v_1insn_patch) <<
109 __sun4v_1insn_patch_end = .; <<
110 } <<
111 .sun4v_2insn_patch : { <<
112 __sun4v_2insn_patch = .; <<
113 *(.sun4v_2insn_patch) <<
114 __sun4v_2insn_patch_end = .; <<
115 } <<
116 .leon_1insn_patch : { <<
117 __leon_1insn_patch = .; <<
118 *(.leon_1insn_patch) <<
119 __leon_1insn_patch_end = .; <<
120 } <<
121 .swapper_tsb_phys_patch : { <<
122 __swapper_tsb_phys_patch = .; <<
123 *(.swapper_tsb_phys_patch) <<
124 __swapper_tsb_phys_patch_end = <<
125 } <<
126 .swapper_4m_tsb_phys_patch : { <<
127 __swapper_4m_tsb_phys_patch = <<
128 *(.swapper_4m_tsb_phys_patch) <<
129 __swapper_4m_tsb_phys_patch_en <<
130 } <<
131 .popc_3insn_patch : { <<
132 __popc_3insn_patch = .; <<
133 *(.popc_3insn_patch) <<
134 __popc_3insn_patch_end = .; <<
135 } <<
136 .popc_6insn_patch : { <<
137 __popc_6insn_patch = .; <<
138 *(.popc_6insn_patch) <<
139 __popc_6insn_patch_end = .; <<
140 } <<
141 .pause_3insn_patch : { <<
142 __pause_3insn_patch = .; <<
143 *(.pause_3insn_patch) <<
144 __pause_3insn_patch_end = .; <<
145 } <<
146 .sun_m7_1insn_patch : { <<
147 __sun_m7_1insn_patch = .; <<
148 *(.sun_m7_1insn_patch) <<
149 __sun_m7_1insn_patch_end = .; <<
150 } <<
151 .sun_m7_2insn_patch : { <<
152 __sun_m7_2insn_patch = .; <<
153 *(.sun_m7_2insn_patch) <<
154 __sun_m7_2insn_patch_end = .; <<
155 } <<
156 .get_tick_patch : { <<
157 __get_tick_patch = .; <<
158 *(.get_tick_patch) <<
159 __get_tick_patch_end = .; <<
160 } <<
161 .pud_huge_patch : { <<
162 __pud_huge_patch = .; <<
163 *(.pud_huge_patch) <<
164 __pud_huge_patch_end = .; <<
165 } <<
166 .fast_win_ctrl_1insn_patch : { <<
167 __fast_win_ctrl_1insn_patch = <<
168 *(.fast_win_ctrl_1insn_patch) <<
169 __fast_win_ctrl_1insn_patch_en <<
170 } 125 }
171 PERCPU_SECTION(SMP_CACHE_BYTES) <<
172 126
173 . = ALIGN(PAGE_SIZE); !! 127 /* .exit.text is discarded at runtime, not link time, to deal with
>> 128 * references from .rodata
>> 129 */
174 .exit.text : { 130 .exit.text : {
175 EXIT_TEXT 131 EXIT_TEXT
176 } 132 }
177 <<
178 .exit.data : { 133 .exit.data : {
179 EXIT_DATA 134 EXIT_DATA
180 } 135 }
>> 136 #ifdef CONFIG_SMP
>> 137 PERCPU_SECTION(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 138 #endif
>> 139
>> 140 #ifdef CONFIG_MIPS_ELF_APPENDED_DTB
>> 141 .appended_dtb : AT(ADDR(.appended_dtb) - LOAD_OFFSET) {
>> 142 *(.appended_dtb)
>> 143 KEEP(*(.appended_dtb))
>> 144 }
>> 145 #endif
>> 146
>> 147 #ifdef CONFIG_RELOCATABLE
>> 148 . = ALIGN(4);
>> 149
>> 150 .data.reloc : {
>> 151 _relocation_start = .;
>> 152 /*
>> 153 * Space for relocation table
>> 154 * This needs to be filled so that the
>> 155 * relocs tool can overwrite the content.
>> 156 * An invalid value is left at the start of the
>> 157 * section to abort relocation if the table
>> 158 * has not been filled in.
>> 159 */
>> 160 LONG(0xFFFFFFFF);
>> 161 FILL(0);
>> 162 . += CONFIG_RELOCATION_TABLE_SIZE - 4;
>> 163 _relocation_end = .;
>> 164 }
>> 165 #endif
181 166
182 . = ALIGN(PAGE_SIZE); !! 167 #ifdef CONFIG_MIPS_RAW_APPENDED_DTB
>> 168 __appended_dtb = .;
>> 169 /* leave space for appended DTB */
>> 170 . += 0x100000;
>> 171 #endif
>> 172 /*
>> 173 * Align to 64K in attempt to eliminate holes before the
>> 174 * .bss..swapper_pg_dir section at the start of .bss. This
>> 175 * also satisfies PAGE_SIZE alignment as the largest page size
>> 176 * allowed is 64K.
>> 177 */
>> 178 . = ALIGN(0x10000);
183 __init_end = .; 179 __init_end = .;
184 BSS_SECTION(0, 0, 0) !! 180 /* freed after init ends here */
>> 181
>> 182 /*
>> 183 * Force .bss to 64K alignment so that .bss..swapper_pg_dir
>> 184 * gets that alignment. .sbss should be empty, so there will be
>> 185 * no holes after __init_end. */
>> 186 BSS_SECTION(0, 0x10000, 8)
>> 187
185 _end = . ; 188 _end = . ;
186 189
>> 190 /* These mark the ABI of the kernel for debuggers. */
>> 191 .mdebug.abi32 : {
>> 192 KEEP(*(.mdebug.abi32))
>> 193 }
>> 194 .mdebug.abi64 : {
>> 195 KEEP(*(.mdebug.abi64))
>> 196 }
>> 197
>> 198 /* This is the MIPS specific mdebug section. */
>> 199 .mdebug : {
>> 200 *(.mdebug)
>> 201 }
>> 202
187 STABS_DEBUG 203 STABS_DEBUG
188 DWARF_DEBUG 204 DWARF_DEBUG
189 ELF_DETAILS <<
190 205
>> 206 /* These must appear regardless of . */
>> 207 .gptab.sdata : {
>> 208 *(.gptab.data)
>> 209 *(.gptab.sdata)
>> 210 }
>> 211 .gptab.sbss : {
>> 212 *(.gptab.bss)
>> 213 *(.gptab.sbss)
>> 214 }
>> 215
>> 216 /* Sections to be discarded */
191 DISCARDS 217 DISCARDS
>> 218 /DISCARD/ : {
>> 219 /* ABI crap starts here */
>> 220 *(.MIPS.abiflags)
>> 221 *(.MIPS.options)
>> 222 *(.options)
>> 223 *(.pdr)
>> 224 *(.reginfo)
>> 225 *(.eh_frame)
>> 226 }
192 } 227 }
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.