1 /* SPDX-License-Identifier: GPL-2.0 */ !! 1 /* ld script to make i386 Linux kernel
2 /* ld script for sparc32/sparc64 kernel */ !! 2 * Written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>;
>> 3 */
3 4
4 #include <asm-generic/vmlinux.lds.h> 5 #include <asm-generic/vmlinux.lds.h>
5 !! 6
6 #include <asm/page.h> !! 7 OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
7 #include <asm/thread_info.h> !! 8 OUTPUT_ARCH(i386)
8 !! 9 ENTRY(startup_32)
9 #ifdef CONFIG_SPARC32 <<
10 #define INITIAL_ADDRESS 0x10000 + SIZEOF_HEAD <<
11 #define TEXTSTART 0xf0004000 <<
12 <<
13 #define SMP_CACHE_BYTES_SHIFT 5 <<
14 <<
15 #else <<
16 #define SMP_CACHE_BYTES_SHIFT 6 <<
17 #define INITIAL_ADDRESS 0x4000 <<
18 #define TEXTSTART 0x0000000000404000 <<
19 <<
20 #endif <<
21 <<
22 #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_ <<
23 <<
24 #ifdef CONFIG_SPARC32 <<
25 OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "e <<
26 OUTPUT_ARCH(sparc) <<
27 ENTRY(_start) <<
28 jiffies = jiffies_64 + 4; <<
29 #else <<
30 /* sparc64 */ <<
31 OUTPUT_FORMAT("elf64-sparc", "elf64-sparc", "e <<
32 OUTPUT_ARCH(sparc:v9a) <<
33 ENTRY(_start) <<
34 jiffies = jiffies_64; 10 jiffies = jiffies_64;
35 #endif <<
36 <<
37 #ifdef CONFIG_SPARC64 <<
38 ASSERT((swapper_tsb == 0x0000000000408000), "E <<
39 #endif <<
40 <<
41 SECTIONS 11 SECTIONS
42 { 12 {
43 #ifdef CONFIG_SPARC64 !! 13 . = 0xC0000000 + 0x100000;
44 swapper_pg_dir = 0x0000000000402000; !! 14 /* read-only */
45 #endif !! 15 _text = .; /* Text and read-only data */
46 . = INITIAL_ADDRESS; !! 16 .text : {
47 .text TEXTSTART : !! 17 *(.text)
48 { !! 18 *(.fixup)
49 _text = .; !! 19 *(.gnu.warning)
50 HEAD_TEXT !! 20 } = 0x9090
51 TEXT_TEXT !! 21
52 SCHED_TEXT !! 22 _etext = .; /* End of text section */
53 LOCK_TEXT !! 23
54 KPROBES_TEXT !! 24 . = ALIGN(16); /* Exception table */
55 IRQENTRY_TEXT !! 25 __start___ex_table = .;
56 SOFTIRQENTRY_TEXT !! 26 __ex_table : { *(__ex_table) }
57 *(.gnu.warning) !! 27 __stop___ex_table = .;
58 } = 0 !! 28
59 _etext = .; !! 29 RODATA
60 !! 30
61 RO_DATA(PAGE_SIZE) !! 31 /* writeable */
62 !! 32 .data : { /* Data */
63 /* Start of data section */ !! 33 *(.data)
64 _sdata = .; !! 34 CONSTRUCTORS
65 !! 35 }
66 .data1 : { !! 36
67 *(.data1) !! 37 . = ALIGN(4096);
68 } !! 38 __nosave_begin = .;
69 RW_DATA(SMP_CACHE_BYTES, 0, THREAD_SIZ !! 39 .data_nosave : { *(.data.nosave) }
70 !! 40 . = ALIGN(4096);
71 /* End of data section */ !! 41 __nosave_end = .;
72 _edata = .; !! 42
73 !! 43 . = ALIGN(4096);
74 .fixup : { !! 44 .data.page_aligned : { *(.data.idt) }
75 __start___fixup = .; !! 45
76 *(.fixup) !! 46 . = ALIGN(32);
77 __stop___fixup = .; !! 47 .data.cacheline_aligned : { *(.data.cacheline_aligned) }
78 } !! 48
79 EXCEPTION_TABLE(16) !! 49 _edata = .; /* End of data section */
80 !! 50
81 . = ALIGN(PAGE_SIZE); !! 51 . = ALIGN(8192); /* init_task */
82 __init_begin = ALIGN(PAGE_SIZE); !! 52 .data.init_task : { *(.data.init_task) }
83 INIT_TEXT_SECTION(PAGE_SIZE) !! 53
84 __init_text_end = .; !! 54 /* will be freed after init */
85 INIT_DATA_SECTION(16) !! 55 . = ALIGN(4096); /* Init code and data */
86 !! 56 __init_begin = .;
87 . = ALIGN(4); !! 57 .init.text : {
88 .tsb_ldquad_phys_patch : { !! 58 _sinittext = .;
89 __tsb_ldquad_phys_patch = .; !! 59 *(.init.text)
90 *(.tsb_ldquad_phys_patch) !! 60 _einittext = .;
91 __tsb_ldquad_phys_patch_end = !! 61 }
92 } !! 62 .init.data : { *(.init.data) }
93 !! 63 . = ALIGN(16);
94 .tsb_phys_patch : { !! 64 __setup_start = .;
95 __tsb_phys_patch = .; !! 65 .init.setup : { *(.init.setup) }
96 *(.tsb_phys_patch) !! 66 __setup_end = .;
97 __tsb_phys_patch_end = .; !! 67 __start___param = .;
98 } !! 68 __param : { *(__param) }
99 !! 69 __stop___param = .;
100 .cpuid_patch : { !! 70 __initcall_start = .;
101 __cpuid_patch = .; !! 71 .initcall.init : {
102 *(.cpuid_patch) !! 72 *(.initcall1.init)
103 __cpuid_patch_end = .; !! 73 *(.initcall2.init)
104 } !! 74 *(.initcall3.init)
105 !! 75 *(.initcall4.init)
106 .sun4v_1insn_patch : { !! 76 *(.initcall5.init)
107 __sun4v_1insn_patch = .; !! 77 *(.initcall6.init)
108 *(.sun4v_1insn_patch) !! 78 *(.initcall7.init)
109 __sun4v_1insn_patch_end = .; !! 79 }
110 } !! 80 __initcall_end = .;
111 .sun4v_2insn_patch : { !! 81 __con_initcall_start = .;
112 __sun4v_2insn_patch = .; !! 82 .con_initcall.init : { *(.con_initcall.init) }
113 *(.sun4v_2insn_patch) !! 83 __con_initcall_end = .;
114 __sun4v_2insn_patch_end = .; !! 84 SECURITY_INIT
115 } !! 85 . = ALIGN(4);
116 .leon_1insn_patch : { !! 86 __alt_instructions = .;
117 __leon_1insn_patch = .; !! 87 .altinstructions : { *(.altinstructions) }
118 *(.leon_1insn_patch) !! 88 __alt_instructions_end = .;
119 __leon_1insn_patch_end = .; !! 89 .altinstr_replacement : { *(.altinstr_replacement) }
120 } !! 90 /* .exit.text is discard at runtime, not link time, to deal with references
121 .swapper_tsb_phys_patch : { !! 91 from .altinstructions and .eh_frame */
122 __swapper_tsb_phys_patch = .; !! 92 .exit.text : { *(.exit.text) }
123 *(.swapper_tsb_phys_patch) !! 93 .exit.data : { *(.exit.data) }
124 __swapper_tsb_phys_patch_end = !! 94 . = ALIGN(4096);
125 } !! 95 __initramfs_start = .;
126 .swapper_4m_tsb_phys_patch : { !! 96 .init.ramfs : { *(.init.ramfs) }
127 __swapper_4m_tsb_phys_patch = !! 97 __initramfs_end = .;
128 *(.swapper_4m_tsb_phys_patch) !! 98 . = ALIGN(32);
129 __swapper_4m_tsb_phys_patch_en !! 99 __per_cpu_start = .;
130 } !! 100 .data.percpu : { *(.data.percpu) }
131 .popc_3insn_patch : { !! 101 __per_cpu_end = .;
132 __popc_3insn_patch = .; !! 102 . = ALIGN(4096);
133 *(.popc_3insn_patch) !! 103 __init_end = .;
134 __popc_3insn_patch_end = .; !! 104 /* freed after init ends here */
135 } !! 105
136 .popc_6insn_patch : { !! 106 __bss_start = .; /* BSS */
137 __popc_6insn_patch = .; !! 107 .bss : { *(.bss) }
138 *(.popc_6insn_patch) !! 108 __bss_stop = .;
139 __popc_6insn_patch_end = .; !! 109
140 } !! 110 _end = . ;
141 .pause_3insn_patch : { !! 111
142 __pause_3insn_patch = .; !! 112 /* Sections to be discarded */
143 *(.pause_3insn_patch) !! 113 /DISCARD/ : {
144 __pause_3insn_patch_end = .; !! 114 *(.exitcall.exit)
145 } !! 115 }
146 .sun_m7_1insn_patch : { !! 116
147 __sun_m7_1insn_patch = .; !! 117 /* Stabs debugging sections. */
148 *(.sun_m7_1insn_patch) !! 118 .stab 0 : { *(.stab) }
149 __sun_m7_1insn_patch_end = .; !! 119 .stabstr 0 : { *(.stabstr) }
150 } !! 120 .stab.excl 0 : { *(.stab.excl) }
151 .sun_m7_2insn_patch : { !! 121 .stab.exclstr 0 : { *(.stab.exclstr) }
152 __sun_m7_2insn_patch = .; !! 122 .stab.index 0 : { *(.stab.index) }
153 *(.sun_m7_2insn_patch) !! 123 .stab.indexstr 0 : { *(.stab.indexstr) }
154 __sun_m7_2insn_patch_end = .; !! 124 .comment 0 : { *(.comment) }
155 } <<
156 .get_tick_patch : { <<
157 __get_tick_patch = .; <<
158 *(.get_tick_patch) <<
159 __get_tick_patch_end = .; <<
160 } <<
161 .pud_huge_patch : { <<
162 __pud_huge_patch = .; <<
163 *(.pud_huge_patch) <<
164 __pud_huge_patch_end = .; <<
165 } <<
166 .fast_win_ctrl_1insn_patch : { <<
167 __fast_win_ctrl_1insn_patch = <<
168 *(.fast_win_ctrl_1insn_patch) <<
169 __fast_win_ctrl_1insn_patch_en <<
170 } <<
171 PERCPU_SECTION(SMP_CACHE_BYTES) <<
172 <<
173 . = ALIGN(PAGE_SIZE); <<
174 .exit.text : { <<
175 EXIT_TEXT <<
176 } <<
177 <<
178 .exit.data : { <<
179 EXIT_DATA <<
180 } <<
181 <<
182 . = ALIGN(PAGE_SIZE); <<
183 __init_end = .; <<
184 BSS_SECTION(0, 0, 0) <<
185 _end = . ; <<
186 <<
187 STABS_DEBUG <<
188 DWARF_DEBUG <<
189 ELF_DETAILS <<
190 <<
191 DISCARDS <<
192 } 125 }
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