1 /* SPDX-License-Identifier: GPL-2.0 */ <<
2 /* 1 /*
3 * VISsave.S: Code for saving FPU register sta 2 * VISsave.S: Code for saving FPU register state for
4 * VIS routines. One should not cal 3 * VIS routines. One should not call this directly,
5 * but use macros provided in <asm/ 4 * but use macros provided in <asm/visasm.h>.
6 * 5 *
7 * Copyright (C) 1998 Jakub Jelinek (jj@ultra. 6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
8 */ 7 */
9 8
10 #include <linux/export.h> <<
11 #include <linux/linkage.h> <<
12 <<
13 #include <asm/asi.h> 9 #include <asm/asi.h>
14 #include <asm/page.h> 10 #include <asm/page.h>
15 #include <asm/ptrace.h> 11 #include <asm/ptrace.h>
16 #include <asm/visasm.h> 12 #include <asm/visasm.h>
17 #include <asm/thread_info.h> 13 #include <asm/thread_info.h>
18 14
>> 15 .text
>> 16 .globl VISenter, VISenterhalf
>> 17
19 /* On entry: %o5=current FPRS value, % 18 /* On entry: %o5=current FPRS value, %g7 is callers address */
20 /* May clobber %o5, %g1, %g2, %g3, %g7 19 /* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
21 20
22 /* Nothing special need be done here t 21 /* Nothing special need be done here to handle pre-emption, this
23 * FPU save/restore mechanism is alrea 22 * FPU save/restore mechanism is already preemption safe.
24 */ 23 */
25 .text !! 24
26 .align 32 25 .align 32
27 ENTRY(VISenter) !! 26 VISenter:
28 ldub [%g6 + TI_FPDEPTH], %g 27 ldub [%g6 + TI_FPDEPTH], %g1
29 brnz,a,pn %g1, 1f 28 brnz,a,pn %g1, 1f
30 cmp %g1, 1 29 cmp %g1, 1
31 stb %g0, [%g6 + TI_FPSAVED 30 stb %g0, [%g6 + TI_FPSAVED]
32 stx %fsr, [%g6 + TI_XFSR] 31 stx %fsr, [%g6 + TI_XFSR]
33 9: jmpl %g7 + %g0, %g0 32 9: jmpl %g7 + %g0, %g0
34 nop 33 nop
35 1: bne,pn %icc, 2f 34 1: bne,pn %icc, 2f
36 35
37 srl %g1, 1, %g1 36 srl %g1, 1, %g1
38 vis1: ldub [%g6 + TI_FPSAVED], %g 37 vis1: ldub [%g6 + TI_FPSAVED], %g3
39 stx %fsr, [%g6 + TI_XFSR] 38 stx %fsr, [%g6 + TI_XFSR]
40 or %g3, %o5, %g3 39 or %g3, %o5, %g3
41 stb %g3, [%g6 + TI_FPSAVED 40 stb %g3, [%g6 + TI_FPSAVED]
42 rd %gsr, %g3 41 rd %gsr, %g3
43 clr %g1 42 clr %g1
44 ba,pt %xcc, 3f 43 ba,pt %xcc, 3f
45 44
46 stx %g3, [%g6 + TI_GSR] 45 stx %g3, [%g6 + TI_GSR]
47 2: add %g6, %g1, %g3 46 2: add %g6, %g1, %g3
48 mov FPRS_DU | FPRS_DL | FP !! 47 cmp %o5, FPRS_DU
49 sll %g1, 3, %g1 !! 48 be,pn %icc, 6f
>> 49 sll %g1, 3, %g1
50 stb %o5, [%g3 + TI_FPSAVED 50 stb %o5, [%g3 + TI_FPSAVED]
51 rd %gsr, %g2 51 rd %gsr, %g2
52 add %g6, %g1, %g3 52 add %g6, %g1, %g3
53 stx %g2, [%g3 + TI_GSR] 53 stx %g2, [%g3 + TI_GSR]
54 54
55 add %g6, %g1, %g2 55 add %g6, %g1, %g2
56 stx %fsr, [%g2 + TI_XFSR] 56 stx %fsr, [%g2 + TI_XFSR]
57 sll %g1, 5, %g1 57 sll %g1, 5, %g1
58 3: andcc %o5, FPRS_DL|FPRS_DU, 58 3: andcc %o5, FPRS_DL|FPRS_DU, %g0
59 be,pn %icc, 9b 59 be,pn %icc, 9b
60 add %g6, TI_FPREGS, %g2 60 add %g6, TI_FPREGS, %g2
61 andcc %o5, FPRS_DL, %g0 61 andcc %o5, FPRS_DL, %g0
62 62
63 be,pn %icc, 4f 63 be,pn %icc, 4f
64 add %g6, TI_FPREGS+0x40, % 64 add %g6, TI_FPREGS+0x40, %g3
65 membar #Sync 65 membar #Sync
66 stda %f0, [%g2 + %g1] ASI_B 66 stda %f0, [%g2 + %g1] ASI_BLK_P
67 stda %f16, [%g3 + %g1] ASI_ 67 stda %f16, [%g3 + %g1] ASI_BLK_P
68 membar #Sync 68 membar #Sync
69 andcc %o5, FPRS_DU, %g0 69 andcc %o5, FPRS_DU, %g0
70 be,pn %icc, 5f 70 be,pn %icc, 5f
71 4: add %g1, 128, %g1 71 4: add %g1, 128, %g1
72 membar #Sync 72 membar #Sync
73 stda %f32, [%g2 + %g1] ASI_ 73 stda %f32, [%g2 + %g1] ASI_BLK_P
74 74
75 stda %f48, [%g3 + %g1] ASI_ 75 stda %f48, [%g3 + %g1] ASI_BLK_P
76 5: membar #Sync 76 5: membar #Sync
77 ba,pt %xcc, 80f 77 ba,pt %xcc, 80f
78 nop 78 nop
79 79
80 .align 32 80 .align 32
81 80: jmpl %g7 + %g0, %g0 81 80: jmpl %g7 + %g0, %g0
82 nop 82 nop
83 ENDPROC(VISenter) !! 83
84 EXPORT_SYMBOL(VISenter) !! 84 6: ldub [%g3 + TI_FPSAVED], %o5
>> 85 or %o5, FPRS_DU, %o5
>> 86 add %g6, TI_FPREGS+0x80, %g2
>> 87 stb %o5, [%g3 + TI_FPSAVED]
>> 88
>> 89 sll %g1, 5, %g1
>> 90 add %g6, TI_FPREGS+0xc0, %g3
>> 91 wr %g0, FPRS_FEF, %fprs
>> 92 membar #Sync
>> 93 stda %f32, [%g2 + %g1] ASI_BLK_P
>> 94 stda %f48, [%g3 + %g1] ASI_BLK_P
>> 95 membar #Sync
>> 96 ba,pt %xcc, 80f
>> 97 nop
>> 98
>> 99 .align 32
>> 100 80: jmpl %g7 + %g0, %g0
>> 101 nop
>> 102
>> 103 .align 32
>> 104 VISenterhalf:
>> 105 ldub [%g6 + TI_FPDEPTH], %g1
>> 106 brnz,a,pn %g1, 1f
>> 107 cmp %g1, 1
>> 108 stb %g0, [%g6 + TI_FPSAVED]
>> 109 stx %fsr, [%g6 + TI_XFSR]
>> 110 clr %o5
>> 111 jmpl %g7 + %g0, %g0
>> 112 wr %g0, FPRS_FEF, %fprs
>> 113
>> 114 1: bne,pn %icc, 2f
>> 115 srl %g1, 1, %g1
>> 116 ba,pt %xcc, vis1
>> 117 sub %g7, 8, %g7
>> 118 2: addcc %g6, %g1, %g3
>> 119 sll %g1, 3, %g1
>> 120 andn %o5, FPRS_DU, %g2
>> 121 stb %g2, [%g3 + TI_FPSAVED]
>> 122
>> 123 rd %gsr, %g2
>> 124 add %g6, %g1, %g3
>> 125 stx %g2, [%g3 + TI_GSR]
>> 126 add %g6, %g1, %g2
>> 127 stx %fsr, [%g2 + TI_XFSR]
>> 128 sll %g1, 5, %g1
>> 129 3: andcc %o5, FPRS_DL, %g0
>> 130 be,pn %icc, 4f
>> 131 add %g6, TI_FPREGS, %g2
>> 132
>> 133 add %g6, TI_FPREGS+0x40, %g3
>> 134 membar #Sync
>> 135 stda %f0, [%g2 + %g1] ASI_BLK_P
>> 136 stda %f16, [%g3 + %g1] ASI_BLK_P
>> 137 membar #Sync
>> 138 ba,pt %xcc, 4f
>> 139 nop
>> 140
>> 141 .align 32
>> 142 4: and %o5, FPRS_DU, %o5
>> 143 jmpl %g7 + %g0, %g0
>> 144 wr %o5, FPRS_FEF, %fprs
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