1 /* SPDX-License-Identifier: GPL-2.0 */ <<
2 /* 1 /*
3 * VISsave.S: Code for saving FPU register sta 2 * VISsave.S: Code for saving FPU register state for
4 * VIS routines. One should not cal 3 * VIS routines. One should not call this directly,
5 * but use macros provided in <asm/ 4 * but use macros provided in <asm/visasm.h>.
6 * 5 *
7 * Copyright (C) 1998 Jakub Jelinek (jj@ultra. 6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
8 */ 7 */
9 8
10 #include <linux/export.h> <<
11 #include <linux/linkage.h> 9 #include <linux/linkage.h>
12 10
13 #include <asm/asi.h> 11 #include <asm/asi.h>
14 #include <asm/page.h> 12 #include <asm/page.h>
15 #include <asm/ptrace.h> 13 #include <asm/ptrace.h>
16 #include <asm/visasm.h> 14 #include <asm/visasm.h>
17 #include <asm/thread_info.h> 15 #include <asm/thread_info.h>
>> 16 #include <asm/export.h>
18 17
19 /* On entry: %o5=current FPRS value, % 18 /* On entry: %o5=current FPRS value, %g7 is callers address */
20 /* May clobber %o5, %g1, %g2, %g3, %g7 19 /* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
21 20
22 /* Nothing special need be done here t 21 /* Nothing special need be done here to handle pre-emption, this
23 * FPU save/restore mechanism is alrea 22 * FPU save/restore mechanism is already preemption safe.
24 */ 23 */
25 .text 24 .text
26 .align 32 25 .align 32
27 ENTRY(VISenter) 26 ENTRY(VISenter)
28 ldub [%g6 + TI_FPDEPTH], %g 27 ldub [%g6 + TI_FPDEPTH], %g1
29 brnz,a,pn %g1, 1f 28 brnz,a,pn %g1, 1f
30 cmp %g1, 1 29 cmp %g1, 1
31 stb %g0, [%g6 + TI_FPSAVED 30 stb %g0, [%g6 + TI_FPSAVED]
32 stx %fsr, [%g6 + TI_XFSR] 31 stx %fsr, [%g6 + TI_XFSR]
33 9: jmpl %g7 + %g0, %g0 32 9: jmpl %g7 + %g0, %g0
34 nop 33 nop
35 1: bne,pn %icc, 2f 34 1: bne,pn %icc, 2f
36 35
37 srl %g1, 1, %g1 36 srl %g1, 1, %g1
38 vis1: ldub [%g6 + TI_FPSAVED], %g 37 vis1: ldub [%g6 + TI_FPSAVED], %g3
39 stx %fsr, [%g6 + TI_XFSR] 38 stx %fsr, [%g6 + TI_XFSR]
40 or %g3, %o5, %g3 39 or %g3, %o5, %g3
41 stb %g3, [%g6 + TI_FPSAVED 40 stb %g3, [%g6 + TI_FPSAVED]
42 rd %gsr, %g3 41 rd %gsr, %g3
43 clr %g1 42 clr %g1
44 ba,pt %xcc, 3f 43 ba,pt %xcc, 3f
45 44
46 stx %g3, [%g6 + TI_GSR] 45 stx %g3, [%g6 + TI_GSR]
47 2: add %g6, %g1, %g3 46 2: add %g6, %g1, %g3
48 mov FPRS_DU | FPRS_DL | FP 47 mov FPRS_DU | FPRS_DL | FPRS_FEF, %o5
49 sll %g1, 3, %g1 48 sll %g1, 3, %g1
50 stb %o5, [%g3 + TI_FPSAVED 49 stb %o5, [%g3 + TI_FPSAVED]
51 rd %gsr, %g2 50 rd %gsr, %g2
52 add %g6, %g1, %g3 51 add %g6, %g1, %g3
53 stx %g2, [%g3 + TI_GSR] 52 stx %g2, [%g3 + TI_GSR]
54 53
55 add %g6, %g1, %g2 54 add %g6, %g1, %g2
56 stx %fsr, [%g2 + TI_XFSR] 55 stx %fsr, [%g2 + TI_XFSR]
57 sll %g1, 5, %g1 56 sll %g1, 5, %g1
58 3: andcc %o5, FPRS_DL|FPRS_DU, 57 3: andcc %o5, FPRS_DL|FPRS_DU, %g0
59 be,pn %icc, 9b 58 be,pn %icc, 9b
60 add %g6, TI_FPREGS, %g2 59 add %g6, TI_FPREGS, %g2
61 andcc %o5, FPRS_DL, %g0 60 andcc %o5, FPRS_DL, %g0
62 61
63 be,pn %icc, 4f 62 be,pn %icc, 4f
64 add %g6, TI_FPREGS+0x40, % 63 add %g6, TI_FPREGS+0x40, %g3
65 membar #Sync 64 membar #Sync
66 stda %f0, [%g2 + %g1] ASI_B 65 stda %f0, [%g2 + %g1] ASI_BLK_P
67 stda %f16, [%g3 + %g1] ASI_ 66 stda %f16, [%g3 + %g1] ASI_BLK_P
68 membar #Sync 67 membar #Sync
69 andcc %o5, FPRS_DU, %g0 68 andcc %o5, FPRS_DU, %g0
70 be,pn %icc, 5f 69 be,pn %icc, 5f
71 4: add %g1, 128, %g1 70 4: add %g1, 128, %g1
72 membar #Sync 71 membar #Sync
73 stda %f32, [%g2 + %g1] ASI_ 72 stda %f32, [%g2 + %g1] ASI_BLK_P
74 73
75 stda %f48, [%g3 + %g1] ASI_ 74 stda %f48, [%g3 + %g1] ASI_BLK_P
76 5: membar #Sync 75 5: membar #Sync
77 ba,pt %xcc, 80f 76 ba,pt %xcc, 80f
78 nop 77 nop
79 78
80 .align 32 79 .align 32
81 80: jmpl %g7 + %g0, %g0 80 80: jmpl %g7 + %g0, %g0
82 nop 81 nop
83 ENDPROC(VISenter) 82 ENDPROC(VISenter)
84 EXPORT_SYMBOL(VISenter) 83 EXPORT_SYMBOL(VISenter)
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