1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* clear_page.S: UltraSparc optimized clear pa !! 2 /*
>> 3 * arch/alpha/lib/clear_page.S
3 * 4 *
4 * Copyright (C) 1996, 1998, 1999, 2000, 2004 !! 5 * Zero an entire page.
5 * Copyright (C) 1997 Jakub Jelinek (jakub@red <<
6 */ 6 */
7 <<
8 #include <linux/export.h> 7 #include <linux/export.h>
9 #include <linux/pgtable.h> <<
10 #include <asm/visasm.h> <<
11 #include <asm/thread_info.h> <<
12 #include <asm/page.h> <<
13 #include <asm/spitfire.h> <<
14 #include <asm/head.h> <<
15 <<
16 /* What we used to do was lock a TLB e <<
17 * TLB slot, clear the page with inter <<
18 * restore the original TLB entry. Th <<
19 * disturbing the TLB as little as pos <<
20 * we had to keep interrupts disabled <<
21 * <<
22 * Now, we simply use the normal TLB l <<
23 * and this makes the cpu choose a slo <<
24 * Then we do a normal TLB flush on ex <<
25 * disable preemption during the clear <<
26 */ <<
27 <<
28 .text 8 .text
>> 9 .align 4
>> 10 .global clear_page
>> 11 .ent clear_page
>> 12 clear_page:
>> 13 .prologue 0
>> 14
>> 15 lda $0,128
>> 16 nop
>> 17 unop
>> 18 nop
>> 19
>> 20 1: stq $31,0($16)
>> 21 stq $31,8($16)
>> 22 stq $31,16($16)
>> 23 stq $31,24($16)
>> 24
>> 25 stq $31,32($16)
>> 26 stq $31,40($16)
>> 27 stq $31,48($16)
>> 28 subq $0,1,$0
>> 29
>> 30 stq $31,56($16)
>> 31 addq $16,64,$16
>> 32 unop
>> 33 bne $0,1b
>> 34
>> 35 ret
>> 36 nop
>> 37 unop
>> 38 nop
29 39
30 .globl _clear_page !! 40 .end clear_page
31 EXPORT_SYMBOL(_clear_page) !! 41 EXPORT_SYMBOL(clear_page)
32 _clear_page: /* %o0=dest */ <<
33 ba,pt %xcc, clear_page_commo <<
34 clr %o4 <<
35 <<
36 /* This thing is pretty important, it <<
37 * on the profiles via do_anonymous_pa <<
38 */ <<
39 .align 32 <<
40 .globl clear_user_page <<
41 EXPORT_SYMBOL(clear_user_page) <<
42 clear_user_page: /* %o0=dest, %o1=vaddr <<
43 lduw [%g6 + TI_PRE_COUNT], <<
44 sethi %hi(PAGE_OFFSET), %g2 <<
45 sethi %hi(PAGE_SIZE), %o4 <<
46 <<
47 ldx [%g2 + %lo(PAGE_OFFSET <<
48 sethi %hi(PAGE_KERNEL_LOCKED <<
49 <<
50 ldx [%g3 + %lo(PAGE_KERNEL <<
51 sub %o0, %g2, %g1 <<
52 <<
53 and %o1, %o4, %o0 <<
54 <<
55 or %g1, %g3, %g1 <<
56 sethi %hi(TLBTEMP_BASE), %o3 <<
57 <<
58 add %o2, 1, %o4 <<
59 add %o0, %o3, %o0 <<
60 <<
61 /* Disable preemption. */ <<
62 mov TLB_TAG_ACCESS, %g3 <<
63 stw %o4, [%g6 + TI_PRE_COU <<
64 <<
65 /* Load TLB entry. */ <<
66 rdpr %pstate, %o4 <<
67 wrpr %o4, PSTATE_IE, %pstat <<
68 stxa %o0, [%g3] ASI_DMMU <<
69 stxa %g1, [%g0] ASI_DTLB_DA <<
70 sethi %hi(KERNBASE), %g1 <<
71 flush %g1 <<
72 wrpr %o4, 0x0, %pstate <<
73 <<
74 mov 1, %o4 <<
75 <<
76 clear_page_common: <<
77 VISEntryHalf <<
78 membar #StoreLoad | #StoreSto <<
79 fzero %f0 <<
80 sethi %hi(PAGE_SIZE/64), %o1 <<
81 mov %o0, %g1 <<
82 fzero %f2 <<
83 or %o1, %lo(PAGE_SIZE/64) <<
84 faddd %f0, %f2, %f4 <<
85 fmuld %f0, %f2, %f6 <<
86 faddd %f0, %f2, %f8 <<
87 fmuld %f0, %f2, %f10 <<
88 <<
89 faddd %f0, %f2, %f12 <<
90 fmuld %f0, %f2, %f14 <<
91 1: stda %f0, [%o0 + %g0] ASI_B <<
92 subcc %o1, 1, %o1 <<
93 bne,pt %icc, 1b <<
94 add %o0, 0x40, %o0 <<
95 membar #Sync <<
96 VISExitHalf <<
97 <<
98 brz,pn %o4, out <<
99 nop <<
100 <<
101 stxa %g0, [%g1] ASI_DMMU_DE <<
102 membar #Sync <<
103 stw %o2, [%g6 + TI_PRE_COU <<
104 <<
105 out: retl <<
106 nop <<
107 <<
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