1 /* SPDX-License-Identifier: GPL-2.0 */ <<
2 /* 1 /*
3 * swift.S: MicroSparc-II mmu/cache operations 2 * swift.S: MicroSparc-II mmu/cache operations.
4 * 3 *
5 * Copyright (C) 1999 David S. Miller (davem@r 4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
6 */ 5 */
7 6
8 #include <asm/psr.h> 7 #include <asm/psr.h>
9 #include <asm/asi.h> 8 #include <asm/asi.h>
10 #include <asm/page.h> 9 #include <asm/page.h>
11 #include <asm/pgtsrmmu.h> 10 #include <asm/pgtsrmmu.h>
12 #include <asm/asm-offsets.h> 11 #include <asm/asm-offsets.h>
13 12
14 .text 13 .text
15 .align 4 14 .align 4
16 15
17 #if 1 /* XXX screw this, I can't get the VAC 16 #if 1 /* XXX screw this, I can't get the VAC flushes working
18 * XXX reliably... -DaveM 17 * XXX reliably... -DaveM
19 */ 18 */
20 .globl swift_flush_cache_all, swift_f 19 .globl swift_flush_cache_all, swift_flush_cache_mm
21 .globl swift_flush_cache_range, swift 20 .globl swift_flush_cache_range, swift_flush_cache_page
22 .globl swift_flush_page_for_dma 21 .globl swift_flush_page_for_dma
23 .globl swift_flush_page_to_ram 22 .globl swift_flush_page_to_ram
24 23
25 swift_flush_cache_all: 24 swift_flush_cache_all:
26 swift_flush_cache_mm: 25 swift_flush_cache_mm:
27 swift_flush_cache_range: 26 swift_flush_cache_range:
28 swift_flush_cache_page: 27 swift_flush_cache_page:
29 swift_flush_page_for_dma: 28 swift_flush_page_for_dma:
30 swift_flush_page_to_ram: 29 swift_flush_page_to_ram:
31 sethi %hi(0x2000), %o0 30 sethi %hi(0x2000), %o0
32 1: subcc %o0, 0x10, %o0 31 1: subcc %o0, 0x10, %o0
33 add %o0, %o0, %o1 32 add %o0, %o0, %o1
34 sta %g0, [%o0] ASI_M_DATAC_TAG 33 sta %g0, [%o0] ASI_M_DATAC_TAG
35 bne 1b 34 bne 1b
36 sta %g0, [%o1] ASI_M_TXTC_TAG 35 sta %g0, [%o1] ASI_M_TXTC_TAG
37 retl 36 retl
38 nop 37 nop
39 #else 38 #else
40 39
41 .globl swift_flush_cache_all 40 .globl swift_flush_cache_all
42 swift_flush_cache_all: 41 swift_flush_cache_all:
43 WINDOW_FLUSH(%g4, %g5) 42 WINDOW_FLUSH(%g4, %g5)
44 43
45 /* Just clear out all the tags. */ 44 /* Just clear out all the tags. */
46 sethi %hi(16 * 1024), %o0 45 sethi %hi(16 * 1024), %o0
47 1: subcc %o0, 16, %o0 46 1: subcc %o0, 16, %o0
48 sta %g0, [%o0] ASI_M_TXTC_TAG 47 sta %g0, [%o0] ASI_M_TXTC_TAG
49 bne 1b 48 bne 1b
50 sta %g0, [%o0] ASI_M_DATAC_TAG 49 sta %g0, [%o0] ASI_M_DATAC_TAG
51 retl 50 retl
52 nop 51 nop
53 52
54 .globl swift_flush_cache_mm 53 .globl swift_flush_cache_mm
55 swift_flush_cache_mm: 54 swift_flush_cache_mm:
56 ld [%o0 + AOFF_mm_context], %g2 55 ld [%o0 + AOFF_mm_context], %g2
57 cmp %g2, -1 56 cmp %g2, -1
58 be swift_flush_cache_mm_out 57 be swift_flush_cache_mm_out
59 WINDOW_FLUSH(%g4, %g5) 58 WINDOW_FLUSH(%g4, %g5)
60 rd %psr, %g1 59 rd %psr, %g1
61 andn %g1, PSR_ET, %g3 60 andn %g1, PSR_ET, %g3
62 wr %g3, 0x0, %psr 61 wr %g3, 0x0, %psr
63 nop 62 nop
64 nop 63 nop
65 mov SRMMU_CTX_REG, %g7 64 mov SRMMU_CTX_REG, %g7
66 lda [%g7] ASI_M_MMUREGS, %g5 65 lda [%g7] ASI_M_MMUREGS, %g5
67 sta %g2, [%g7] ASI_M_MMUREGS 66 sta %g2, [%g7] ASI_M_MMUREGS
68 67
69 #if 1 68 #if 1
70 sethi %hi(0x2000), %o0 69 sethi %hi(0x2000), %o0
71 1: subcc %o0, 0x10, %o0 70 1: subcc %o0, 0x10, %o0
72 sta %g0, [%o0] ASI_M_FLUSH_CTX 71 sta %g0, [%o0] ASI_M_FLUSH_CTX
73 bne 1b 72 bne 1b
74 nop 73 nop
75 #else 74 #else
76 clr %o0 75 clr %o0
77 or %g0, 2048, %g7 76 or %g0, 2048, %g7
78 or %g0, 2048, %o1 77 or %g0, 2048, %o1
79 add %o1, 2048, %o2 78 add %o1, 2048, %o2
80 add %o2, 2048, %o3 79 add %o2, 2048, %o3
81 mov 16, %o4 80 mov 16, %o4
82 add %o4, 2048, %o5 81 add %o4, 2048, %o5
83 add %o5, 2048, %g2 82 add %o5, 2048, %g2
84 add %g2, 2048, %g3 83 add %g2, 2048, %g3
85 1: sta %g0, [%o0 ] ASI_M_FLUSH_C 84 1: sta %g0, [%o0 ] ASI_M_FLUSH_CTX
86 sta %g0, [%o0 + %o1] ASI_M_FLUSH_C 85 sta %g0, [%o0 + %o1] ASI_M_FLUSH_CTX
87 sta %g0, [%o0 + %o2] ASI_M_FLUSH_C 86 sta %g0, [%o0 + %o2] ASI_M_FLUSH_CTX
88 sta %g0, [%o0 + %o3] ASI_M_FLUSH_C 87 sta %g0, [%o0 + %o3] ASI_M_FLUSH_CTX
89 sta %g0, [%o0 + %o4] ASI_M_FLUSH_C 88 sta %g0, [%o0 + %o4] ASI_M_FLUSH_CTX
90 sta %g0, [%o0 + %o5] ASI_M_FLUSH_C 89 sta %g0, [%o0 + %o5] ASI_M_FLUSH_CTX
91 sta %g0, [%o0 + %g2] ASI_M_FLUSH_C 90 sta %g0, [%o0 + %g2] ASI_M_FLUSH_CTX
92 sta %g0, [%o0 + %g3] ASI_M_FLUSH_C 91 sta %g0, [%o0 + %g3] ASI_M_FLUSH_CTX
93 subcc %g7, 32, %g7 92 subcc %g7, 32, %g7
94 bne 1b 93 bne 1b
95 add %o0, 32, %o0 94 add %o0, 32, %o0
96 #endif 95 #endif
97 96
98 mov SRMMU_CTX_REG, %g7 97 mov SRMMU_CTX_REG, %g7
99 sta %g5, [%g7] ASI_M_MMUREGS 98 sta %g5, [%g7] ASI_M_MMUREGS
100 wr %g1, 0x0, %psr 99 wr %g1, 0x0, %psr
101 nop 100 nop
102 nop 101 nop
103 swift_flush_cache_mm_out: 102 swift_flush_cache_mm_out:
104 retl 103 retl
105 nop 104 nop
106 105
107 .globl swift_flush_cache_range 106 .globl swift_flush_cache_range
108 swift_flush_cache_range: 107 swift_flush_cache_range:
109 ld [%o0 + VMA_VM_MM], %o0 108 ld [%o0 + VMA_VM_MM], %o0
110 sub %o2, %o1, %o2 109 sub %o2, %o1, %o2
111 sethi %hi(4096), %o3 110 sethi %hi(4096), %o3
112 cmp %o2, %o3 111 cmp %o2, %o3
113 bgu swift_flush_cache_mm 112 bgu swift_flush_cache_mm
114 nop 113 nop
115 b 70f 114 b 70f
116 nop 115 nop
117 116
118 .globl swift_flush_cache_page 117 .globl swift_flush_cache_page
119 swift_flush_cache_page: 118 swift_flush_cache_page:
120 ld [%o0 + VMA_VM_MM], %o0 119 ld [%o0 + VMA_VM_MM], %o0
121 70: 120 70:
122 ld [%o0 + AOFF_mm_context], %g2 121 ld [%o0 + AOFF_mm_context], %g2
123 cmp %g2, -1 122 cmp %g2, -1
124 be swift_flush_cache_page_out 123 be swift_flush_cache_page_out
125 WINDOW_FLUSH(%g4, %g5) 124 WINDOW_FLUSH(%g4, %g5)
126 rd %psr, %g1 125 rd %psr, %g1
127 andn %g1, PSR_ET, %g3 126 andn %g1, PSR_ET, %g3
128 wr %g3, 0x0, %psr 127 wr %g3, 0x0, %psr
129 nop 128 nop
130 nop 129 nop
131 mov SRMMU_CTX_REG, %g7 130 mov SRMMU_CTX_REG, %g7
132 lda [%g7] ASI_M_MMUREGS, %g5 131 lda [%g7] ASI_M_MMUREGS, %g5
133 sta %g2, [%g7] ASI_M_MMUREGS 132 sta %g2, [%g7] ASI_M_MMUREGS
134 133
135 andn %o1, (PAGE_SIZE - 1), %o1 134 andn %o1, (PAGE_SIZE - 1), %o1
136 #if 1 135 #if 1
137 sethi %hi(0x1000), %o0 136 sethi %hi(0x1000), %o0
138 1: subcc %o0, 0x10, %o0 137 1: subcc %o0, 0x10, %o0
139 sta %g0, [%o1 + %o0] ASI_M_FLUSH_P 138 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
140 bne 1b 139 bne 1b
141 nop 140 nop
142 #else 141 #else
143 or %g0, 512, %g7 142 or %g0, 512, %g7
144 or %g0, 512, %o0 143 or %g0, 512, %o0
145 add %o0, 512, %o2 144 add %o0, 512, %o2
146 add %o2, 512, %o3 145 add %o2, 512, %o3
147 add %o3, 512, %o4 146 add %o3, 512, %o4
148 add %o4, 512, %o5 147 add %o4, 512, %o5
149 add %o5, 512, %g3 148 add %o5, 512, %g3
150 add %g3, 512, %g4 149 add %g3, 512, %g4
151 1: sta %g0, [%o1 ] ASI_M_FLUSH_P 150 1: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE
152 sta %g0, [%o1 + %o0] ASI_M_FLUSH_P 151 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
153 sta %g0, [%o1 + %o2] ASI_M_FLUSH_P 152 sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
154 sta %g0, [%o1 + %o3] ASI_M_FLUSH_P 153 sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
155 sta %g0, [%o1 + %o4] ASI_M_FLUSH_P 154 sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
156 sta %g0, [%o1 + %o5] ASI_M_FLUSH_P 155 sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
157 sta %g0, [%o1 + %g3] ASI_M_FLUSH_P 156 sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
158 sta %g0, [%o1 + %g4] ASI_M_FLUSH_P 157 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
159 subcc %g7, 16, %g7 158 subcc %g7, 16, %g7
160 bne 1b 159 bne 1b
161 add %o1, 16, %o1 160 add %o1, 16, %o1
162 #endif 161 #endif
163 162
164 mov SRMMU_CTX_REG, %g7 163 mov SRMMU_CTX_REG, %g7
165 sta %g5, [%g7] ASI_M_MMUREGS 164 sta %g5, [%g7] ASI_M_MMUREGS
166 wr %g1, 0x0, %psr 165 wr %g1, 0x0, %psr
167 nop 166 nop
168 nop 167 nop
169 swift_flush_cache_page_out: 168 swift_flush_cache_page_out:
170 retl 169 retl
171 nop 170 nop
172 171
173 /* Swift is write-thru, however it is 172 /* Swift is write-thru, however it is not
174 * I/O nor TLB-walk coherent. Also it 173 * I/O nor TLB-walk coherent. Also it has
175 * caches which are virtually indexed 174 * caches which are virtually indexed and tagged.
176 */ 175 */
177 .globl swift_flush_page_for_dma 176 .globl swift_flush_page_for_dma
178 .globl swift_flush_page_to_ram 177 .globl swift_flush_page_to_ram
179 swift_flush_page_for_dma: 178 swift_flush_page_for_dma:
180 swift_flush_page_to_ram: 179 swift_flush_page_to_ram:
181 andn %o0, (PAGE_SIZE - 1), %o1 180 andn %o0, (PAGE_SIZE - 1), %o1
182 #if 1 181 #if 1
183 sethi %hi(0x1000), %o0 182 sethi %hi(0x1000), %o0
184 1: subcc %o0, 0x10, %o0 183 1: subcc %o0, 0x10, %o0
185 sta %g0, [%o1 + %o0] ASI_M_FLUSH_P 184 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
186 bne 1b 185 bne 1b
187 nop 186 nop
188 #else 187 #else
189 or %g0, 512, %g7 188 or %g0, 512, %g7
190 or %g0, 512, %o0 189 or %g0, 512, %o0
191 add %o0, 512, %o2 190 add %o0, 512, %o2
192 add %o2, 512, %o3 191 add %o2, 512, %o3
193 add %o3, 512, %o4 192 add %o3, 512, %o4
194 add %o4, 512, %o5 193 add %o4, 512, %o5
195 add %o5, 512, %g3 194 add %o5, 512, %g3
196 add %g3, 512, %g4 195 add %g3, 512, %g4
197 1: sta %g0, [%o1 ] ASI_M_FLUSH_P 196 1: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE
198 sta %g0, [%o1 + %o0] ASI_M_FLUSH_P 197 sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
199 sta %g0, [%o1 + %o2] ASI_M_FLUSH_P 198 sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
200 sta %g0, [%o1 + %o3] ASI_M_FLUSH_P 199 sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
201 sta %g0, [%o1 + %o4] ASI_M_FLUSH_P 200 sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
202 sta %g0, [%o1 + %o5] ASI_M_FLUSH_P 201 sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
203 sta %g0, [%o1 + %g3] ASI_M_FLUSH_P 202 sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
204 sta %g0, [%o1 + %g4] ASI_M_FLUSH_P 203 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
205 subcc %g7, 16, %g7 204 subcc %g7, 16, %g7
206 bne 1b 205 bne 1b
207 add %o1, 16, %o1 206 add %o1, 16, %o1
208 #endif 207 #endif
209 retl 208 retl
210 nop 209 nop
211 #endif 210 #endif
212 211
213 .globl swift_flush_sig_insns 212 .globl swift_flush_sig_insns
214 swift_flush_sig_insns: 213 swift_flush_sig_insns:
215 flush %o1 214 flush %o1
216 retl 215 retl
217 flush %o1 + 4 216 flush %o1 + 4
218 217
219 .globl swift_flush_tlb_mm 218 .globl swift_flush_tlb_mm
220 .globl swift_flush_tlb_range 219 .globl swift_flush_tlb_range
221 .globl swift_flush_tlb_all 220 .globl swift_flush_tlb_all
222 swift_flush_tlb_range: 221 swift_flush_tlb_range:
223 ld [%o0 + VMA_VM_MM], %o0 222 ld [%o0 + VMA_VM_MM], %o0
224 swift_flush_tlb_mm: 223 swift_flush_tlb_mm:
225 ld [%o0 + AOFF_mm_context], %g2 224 ld [%o0 + AOFF_mm_context], %g2
226 cmp %g2, -1 225 cmp %g2, -1
227 be swift_flush_tlb_all_out 226 be swift_flush_tlb_all_out
228 swift_flush_tlb_all: 227 swift_flush_tlb_all:
229 mov 0x400, %o1 228 mov 0x400, %o1
230 sta %g0, [%o1] ASI_M_FLUSH_PROBE 229 sta %g0, [%o1] ASI_M_FLUSH_PROBE
231 swift_flush_tlb_all_out: 230 swift_flush_tlb_all_out:
232 retl 231 retl
233 nop 232 nop
234 233
235 .globl swift_flush_tlb_page 234 .globl swift_flush_tlb_page
236 swift_flush_tlb_page: 235 swift_flush_tlb_page:
237 ld [%o0 + VMA_VM_MM], %o0 236 ld [%o0 + VMA_VM_MM], %o0
238 mov SRMMU_CTX_REG, %g1 237 mov SRMMU_CTX_REG, %g1
239 ld [%o0 + AOFF_mm_context], %o3 238 ld [%o0 + AOFF_mm_context], %o3
240 andn %o1, (PAGE_SIZE - 1), %o1 239 andn %o1, (PAGE_SIZE - 1), %o1
241 cmp %o3, -1 240 cmp %o3, -1
242 be swift_flush_tlb_page_out 241 be swift_flush_tlb_page_out
243 nop 242 nop
244 #if 1 243 #if 1
245 mov 0x400, %o1 244 mov 0x400, %o1
246 sta %g0, [%o1] ASI_M_FLUSH_PROBE 245 sta %g0, [%o1] ASI_M_FLUSH_PROBE
247 #else 246 #else
248 lda [%g1] ASI_M_MMUREGS, %g5 247 lda [%g1] ASI_M_MMUREGS, %g5
249 sta %o3, [%g1] ASI_M_MMUREGS 248 sta %o3, [%g1] ASI_M_MMUREGS
250 sta %g0, [%o1] ASI_M_FLUSH_PAGE 249 sta %g0, [%o1] ASI_M_FLUSH_PAGE /* rem. virt. cache. prot. */
251 sta %g0, [%o1] ASI_M_FLUSH_PROBE 250 sta %g0, [%o1] ASI_M_FLUSH_PROBE
252 sta %g5, [%g1] ASI_M_MMUREGS 251 sta %g5, [%g1] ASI_M_MMUREGS
253 #endif 252 #endif
254 swift_flush_tlb_page_out: 253 swift_flush_tlb_page_out:
255 retl 254 retl
256 nop 255 nop
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.