1 # SPDX-License-Identifier: GPL-2.0 !! 1 comment "Processor Type"
2 # Put here option for CPU selection and depend !! 2
3 choice 3 choice
4 prompt "Processor family" !! 4 prompt "CPU family support"
5 default M686 if X86_32 !! 5 default M68KCLASSIC if MMU
6 default GENERIC_CPU if X86_64 !! 6 default COLDFIRE if !MMU
7 help !! 7 help
8 This is the processor type of your C !! 8 The Freescale (was Motorola) M68K family of processors implements
9 used for optimizing purposes. In ord !! 9 the full 68000 processor instruction set.
10 that can run on all supported x86 CP !! 10 The Freescale ColdFire family of processors is a modern derivative
11 optimally fast), you can specify "48 !! 11 of the 68000 processor family. They are mainly targeted at embedded
12 !! 12 applications, and are all System-On-Chip (SOC) devices, as opposed
13 Note that the 386 is no longer suppo !! 13 to stand alone CPUs. They implement a subset of the original 68000
14 AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, !! 14 processor instruction set.
15 UMC 486SX-S and the NexGen Nx586. !! 15 If you anticipate running this kernel on a computer with a classic
16 !! 16 MC68xxx processor, select M68KCLASSIC.
17 The kernel will not necessarily run !! 17 If you anticipate running this kernel on a computer with a ColdFire
18 the one you have chosen, e.g. a Pent !! 18 processor, select COLDFIRE.
19 a PPro, but not necessarily on a i48 !! 19
20 !! 20 config M68KCLASSIC
21 Here are the settings recommended fo !! 21 bool "Classic M68K CPU family support"
22 - "486" for the AMD/Cyrix/IBM/Intel !! 22
23 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5 !! 23 config COLDFIRE
24 - "586" for generic Pentium CPUs lac !! 24 bool "Coldfire CPU family support"
25 (time stamp counter) register. !! 25 select ARCH_REQUIRE_GPIOLIB
26 - "Pentium-Classic" for the Intel Pe !! 26 select ARCH_HAVE_CUSTOM_GPIO_H
27 - "Pentium-MMX" for the Intel Pentiu !! 27 select CPU_HAS_NO_BITFIELDS
28 - "Pentium-Pro" for the Intel Pentiu !! 28 select CPU_HAS_NO_MULDIV64
29 - "Pentium-II" for the Intel Pentium !! 29 select GENERIC_CSUM
30 - "Pentium-III" for the Intel Pentiu !! 30 select HAVE_CLK
31 - "Pentium-4" for the Intel Pentium <<
32 - "K6" for the AMD K6, K6-II and K6- <<
33 - "Athlon" for the AMD K7 family (At <<
34 - "Opteron/Athlon64/Hammer/K8" for a <<
35 - "Crusoe" for the Transmeta Crusoe <<
36 - "Efficeon" for the Transmeta Effic <<
37 - "Winchip-C6" for original IDT Winc <<
38 - "Winchip-2" for IDT Winchips with <<
39 - "AMD Elan" for the 32-bit AMD Elan <<
40 - "GeodeGX1" for Geode GX1 (Cyrix Me <<
41 - "Geode GX/LX" For AMD Geode GX and <<
42 - "CyrixIII/VIA C3" for VIA Cyrix II <<
43 - "VIA C3-2" for VIA C3-2 "Nehemiah" <<
44 - "VIA C7" for VIA C7. <<
45 - "Intel P4" for the Pentium 4/Netbu <<
46 - "Core 2/newer Xeon" for all core2 <<
47 - "Intel Atom" for the Atom-microarc <<
48 - "Generic-x86-64" for a kernel whic <<
49 <<
50 See each option's help text for addi <<
51 what to do, choose "486". <<
52 <<
53 config M486SX <<
54 bool "486SX" <<
55 depends on X86_32 <<
56 help <<
57 Select this for an 486-class CPU wit <<
58 AMD/Cyrix/IBM/Intel SL/SLC/SLC2/SLC3 <<
59 <<
60 config M486 <<
61 bool "486DX" <<
62 depends on X86_32 <<
63 help <<
64 Select this for an 486-class CPU suc <<
65 486DX/DX2/DX4 and UMC U5D. <<
66 <<
67 config M586 <<
68 bool "586/K5/5x86/6x86/6x86MX" <<
69 depends on X86_32 <<
70 help <<
71 Select this for an 586 or 686 series <<
72 the Cyrix 5x86, 6x86 and 6x86MX. Th <<
73 assume the RDTSC (Read Time Stamp Co <<
74 <<
75 config M586TSC <<
76 bool "Pentium-Classic" <<
77 depends on X86_32 <<
78 help <<
79 Select this for a Pentium Classic pr <<
80 Time Stamp Counter) instruction for <<
81 <<
82 config M586MMX <<
83 bool "Pentium-MMX" <<
84 depends on X86_32 <<
85 help <<
86 Select this for a Pentium with the M <<
87 extended instructions. <<
88 <<
89 config M686 <<
90 bool "Pentium-Pro" <<
91 depends on X86_32 <<
92 help <<
93 Select this for Intel Pentium Pro ch <<
94 Pentium Pro extended instructions, a <<
95 against the f00f bug found in earlie <<
96 <<
97 config MPENTIUMII <<
98 bool "Pentium-II/Celeron(pre-Coppermin <<
99 depends on X86_32 <<
100 help <<
101 Select this for Intel chips based on <<
102 pre-Coppermine Celeron core. This o <<
103 copy optimization, compiles the kern <<
104 tailored for the chip, and applies a <<
105 optimizations. <<
106 <<
107 config MPENTIUMIII <<
108 bool "Pentium-III/Celeron(Coppermine)/ <<
109 depends on X86_32 <<
110 help <<
111 Select this for Intel chips based on <<
112 Celeron-Coppermine core. This optio <<
113 extended prefetch instructions in ad <<
114 extensions. <<
115 <<
116 config MPENTIUMM <<
117 bool "Pentium M" <<
118 depends on X86_32 <<
119 help <<
120 Select this for Intel Pentium M (not <<
121 notebook chips. <<
122 <<
123 config MPENTIUM4 <<
124 bool "Pentium-4/Celeron(P4-based)/Pent <<
125 depends on X86_32 <<
126 help <<
127 Select this for Intel Pentium 4 chip <<
128 Pentium 4, Pentium D, P4-based Celer <<
129 Pentium-4 M (not Pentium M) chips. <<
130 flags optimized for the chip, uses t <<
131 applies any applicable optimizations <<
132 <<
133 CPUIDs: F[0-6][1-A] (in /proc/cpuinf <<
134 <<
135 Select this for: <<
136 Pentiums (Pentium 4, Pentium D, Ce <<
137 -Willamette <<
138 -Northwood <<
139 -Mobile Pentium 4 <<
140 -Mobile Pentium 4 M <<
141 -Extreme Edition (Gallatin) <<
142 -Prescott <<
143 -Prescott 2M <<
144 -Cedar Mill <<
145 -Presler <<
146 -Smithfiled <<
147 Xeons (Intel Xeon, Xeon MP, Xeon L <<
148 -Foster <<
149 -Prestonia <<
150 -Gallatin <<
151 -Nocona <<
152 -Irwindale <<
153 -Cranford <<
154 -Potomac <<
155 -Paxville <<
156 -Dempsey <<
157 <<
158 <<
159 config MK6 <<
160 bool "K6/K6-II/K6-III" <<
161 depends on X86_32 <<
162 help <<
163 Select this for an AMD K6-family pro <<
164 some extended instructions, and pass <<
165 flags to GCC. <<
166 <<
167 config MK7 <<
168 bool "Athlon/Duron/K7" <<
169 depends on X86_32 <<
170 help <<
171 Select this for an AMD Athlon K7-fam <<
172 some extended instructions, and pass <<
173 flags to GCC. <<
174 <<
175 config MK8 <<
176 bool "Opteron/Athlon64/Hammer/K8" <<
177 help <<
178 Select this for an AMD Opteron or At <<
179 Enables use of some extended instruc <<
180 optimization flags to GCC. <<
181 <<
182 config MCRUSOE <<
183 bool "Crusoe" <<
184 depends on X86_32 <<
185 help <<
186 Select this for a Transmeta Crusoe p <<
187 like a 586 with TSC, and sets some G <<
188 Pentium Pro with no alignment requir <<
189 <<
190 config MEFFICEON <<
191 bool "Efficeon" <<
192 depends on X86_32 <<
193 help <<
194 Select this for a Transmeta Efficeon <<
195 <<
196 config MWINCHIPC6 <<
197 bool "Winchip-C6" <<
198 depends on X86_32 <<
199 help <<
200 Select this for an IDT Winchip C6 ch <<
201 treat this chip as a 586TSC with som <<
202 and alignment requirements. <<
203 <<
204 config MWINCHIP3D <<
205 bool "Winchip-2/Winchip-2A/Winchip-3" <<
206 depends on X86_32 <<
207 help <<
208 Select this for an IDT Winchip-2, 2A <<
209 treat this chip as a 586TSC with som <<
210 and alignment requirements. Also en <<
211 stores for this CPU, which can incre <<
212 operations. <<
213 <<
214 config MELAN <<
215 bool "AMD Elan" <<
216 depends on X86_32 <<
217 help <<
218 Select this for an AMD Elan processo <<
219 <<
220 Do not use this option for K6/Athlon <<
221 <<
222 config MGEODEGX1 <<
223 bool "GeodeGX1" <<
224 depends on X86_32 <<
225 help <<
226 Select this for a Geode GX1 (Cyrix M <<
227 <<
228 config MGEODE_LX <<
229 bool "Geode GX/LX" <<
230 depends on X86_32 <<
231 help <<
232 Select this for AMD Geode GX and LX <<
233 <<
234 config MCYRIXIII <<
235 bool "CyrixIII/VIA-C3" <<
236 depends on X86_32 <<
237 help <<
238 Select this for a Cyrix III or C3 ch <<
239 treat this chip as a generic 586. Wh <<
240 it lacks the cmov extension which gc <<
241 generating 686 code. <<
242 Note that Nehemiah (Model 9) and abo <<
243 kernel due to them lacking the 3DNow <<
244 incarnations of the CPU. <<
245 <<
246 config MVIAC3_2 <<
247 bool "VIA C3-2 (Nehemiah)" <<
248 depends on X86_32 <<
249 help <<
250 Select this for a VIA C3 "Nehemiah". <<
251 of SSE and tells gcc to treat the CP <<
252 Note, this kernel will not boot on o <<
253 <<
254 config MVIAC7 <<
255 bool "VIA C7" <<
256 depends on X86_32 <<
257 help <<
258 Select this for a VIA C7. Selecting <<
259 shift and tells gcc to treat the CPU <<
260 <<
261 config MPSC <<
262 bool "Intel P4 / older Netburst based <<
263 depends on X86_64 <<
264 help <<
265 Optimize for Intel Pentium 4, Pentiu <<
266 Xeon CPUs with Intel 64bit which is <<
267 Note that the latest Xeons (Xeon 51x <<
268 Netburst core and shouldn't use this <<
269 using the cpu family field <<
270 in /proc/cpuinfo. Family 15 is an ol <<
271 <<
272 config MCORE2 <<
273 bool "Core 2/newer Xeon" <<
274 help <<
275 <<
276 Select this for Intel Core 2 and new <<
277 53xx) CPUs. You can distinguish newe <<
278 family in /proc/cpuinfo. Newer ones <<
279 (not a typo) <<
280 <<
281 config MATOM <<
282 bool "Intel Atom" <<
283 help <<
284 <<
285 Select this for the Intel Atom platf <<
286 in-order pipelining architecture and <<
287 accordingly optimized code. Use a re <<
288 support in order to fully benefit fr <<
289 <<
290 config GENERIC_CPU <<
291 bool "Generic-x86-64" <<
292 depends on X86_64 <<
293 help <<
294 Generic x86-64 CPU. <<
295 Run equally well on all x86-64 CPUs. <<
296 31
297 endchoice 32 endchoice
298 33
299 config X86_GENERIC !! 34 if M68KCLASSIC
300 bool "Generic x86 support" <<
301 depends on X86_32 <<
302 help <<
303 Instead of just including optimizati <<
304 x86 variant (e.g. PII, Crusoe or Ath <<
305 generic optimizations as well. This <<
306 perform better on x86 CPUs other tha <<
307 <<
308 This is really intended for distribu <<
309 generic optimizations. <<
310 <<
311 # <<
312 # Define implied options from the CPU selectio <<
313 config X86_INTERNODE_CACHE_SHIFT <<
314 int <<
315 default "12" if X86_VSMP <<
316 default X86_L1_CACHE_SHIFT <<
317 <<
318 config X86_L1_CACHE_SHIFT <<
319 int <<
320 default "7" if MPENTIUM4 || MPSC <<
321 default "6" if MK7 || MK8 || MPENTIUMM <<
322 default "4" if MELAN || M486SX || M486 <<
323 default "5" if MWINCHIP3D || MWINCHIPC <<
324 <<
325 config X86_F00F_BUG <<
326 def_bool y <<
327 depends on M586MMX || M586TSC || M586 <<
328 <<
329 config X86_INVD_BUG <<
330 def_bool y <<
331 depends on M486SX || M486 <<
332 <<
333 config X86_ALIGNMENT_16 <<
334 def_bool y <<
335 depends on MWINCHIP3D || MWINCHIPC6 || <<
336 <<
337 config X86_INTEL_USERCOPY <<
338 def_bool y <<
339 depends on MPENTIUM4 || MPENTIUMM || M <<
340 <<
341 config X86_USE_PPRO_CHECKSUM <<
342 def_bool y <<
343 depends on MWINCHIP3D || MWINCHIPC6 || <<
344 <<
345 # <<
346 # P6_NOPs are a relatively minor optimization <<
347 # 6 processor, except that it is broken on cer <<
348 # Furthermore, AMD chips prefer a totally diff <<
349 # (which work on all CPUs). In addition, it l <<
350 # does not understand them. <<
351 # <<
352 # As a result, disallow these if we're not com <<
353 # NOPs do work on all x86-64 capable chips); t <<
354 # the right-hand clause are the cores that ben <<
355 # <<
356 config X86_P6_NOP <<
357 def_bool y <<
358 depends on X86_64 <<
359 depends on (MCORE2 || MPENTIUM4 || MPS <<
360 <<
361 config X86_TSC <<
362 def_bool y <<
363 depends on (MWINCHIP3D || MCRUSOE || M <<
364 <<
365 config X86_HAVE_PAE <<
366 def_bool y <<
367 depends on MCRUSOE || MEFFICEON || MCY <<
368 <<
369 config X86_CMPXCHG64 <<
370 def_bool y <<
371 depends on X86_HAVE_PAE || M586TSC || <<
372 <<
373 # this should be set for all -march=.. options <<
374 # generates cmov. <<
375 config X86_CMOV <<
376 def_bool y <<
377 depends on (MK8 || MK7 || MCORE2 || MP <<
378 <<
379 config X86_MINIMUM_CPU_FAMILY <<
380 int <<
381 default "64" if X86_64 <<
382 default "6" if X86_32 && (MPENTIUM4 || <<
383 default "5" if X86_32 && X86_CMPXCHG64 <<
384 default "4" <<
385 <<
386 config X86_DEBUGCTLMSR <<
387 def_bool y <<
388 depends on !(MK6 || MWINCHIPC6 || MWIN <<
389 <<
390 config IA32_FEAT_CTL <<
391 def_bool y <<
392 depends on CPU_SUP_INTEL || CPU_SUP_CE <<
393 <<
394 config X86_VMX_FEATURE_NAMES <<
395 def_bool y <<
396 depends on IA32_FEAT_CTL <<
397 <<
398 menuconfig PROCESSOR_SELECT <<
399 bool "Supported processor vendors" if <<
400 help <<
401 This lets you choose what x86 vendor <<
402 will include. <<
403 35
404 config CPU_SUP_INTEL !! 36 config M68000
405 default y !! 37 bool "MC68000"
406 bool "Support Intel processors" if PRO !! 38 depends on !MMU
>> 39 select CPU_HAS_NO_BITFIELDS
>> 40 select CPU_HAS_NO_MULDIV64
>> 41 select CPU_HAS_NO_UNALIGNED
>> 42 select GENERIC_CSUM
>> 43 help
>> 44 The Freescale (was Motorola) 68000 CPU is the first generation of
>> 45 the well known M68K family of processors. The CPU core as well as
>> 46 being available as a stand alone CPU was also used in many
>> 47 System-On-Chip devices (eg 68328, 68302, etc). It does not contain
>> 48 a paging MMU.
>> 49
>> 50 config MCPU32
>> 51 bool
>> 52 select CPU_HAS_NO_BITFIELDS
>> 53 select CPU_HAS_NO_UNALIGNED
>> 54 help
>> 55 The Freescale (was then Motorola) CPU32 is a CPU core that is
>> 56 based on the 68020 processor. For the most part it is used in
>> 57 System-On-Chip parts, and does not contain a paging MMU.
>> 58
>> 59 config M68020
>> 60 bool "68020 support"
>> 61 depends on MMU
>> 62 select CPU_HAS_ADDRESS_SPACES
>> 63 help
>> 64 If you anticipate running this kernel on a computer with a MC68020
>> 65 processor, say Y. Otherwise, say N. Note that the 68020 requires a
>> 66 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the
>> 67 Sun 3, which provides its own version.
>> 68
>> 69 config M68030
>> 70 bool "68030 support"
>> 71 depends on MMU && !MMU_SUN3
>> 72 select CPU_HAS_ADDRESS_SPACES
>> 73 help
>> 74 If you anticipate running this kernel on a computer with a MC68030
>> 75 processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
>> 76 work, as it does not include an MMU (Memory Management Unit).
>> 77
>> 78 config M68040
>> 79 bool "68040 support"
>> 80 depends on MMU && !MMU_SUN3
>> 81 select CPU_HAS_ADDRESS_SPACES
>> 82 help
>> 83 If you anticipate running this kernel on a computer with a MC68LC040
>> 84 or MC68040 processor, say Y. Otherwise, say N. Note that an
>> 85 MC68EC040 will not work, as it does not include an MMU (Memory
>> 86 Management Unit).
>> 87
>> 88 config M68060
>> 89 bool "68060 support"
>> 90 depends on MMU && !MMU_SUN3
>> 91 select CPU_HAS_ADDRESS_SPACES
>> 92 help
>> 93 If you anticipate running this kernel on a computer with a MC68060
>> 94 processor, say Y. Otherwise, say N.
>> 95
>> 96 config M68328
>> 97 bool "MC68328"
>> 98 depends on !MMU
>> 99 select M68000
>> 100 help
>> 101 Motorola 68328 processor support.
>> 102
>> 103 config M68EZ328
>> 104 bool "MC68EZ328"
>> 105 depends on !MMU
>> 106 select M68000
>> 107 help
>> 108 Motorola 68EX328 processor support.
>> 109
>> 110 config M68VZ328
>> 111 bool "MC68VZ328"
>> 112 depends on !MMU
>> 113 select M68000
>> 114 help
>> 115 Motorola 68VZ328 processor support.
>> 116
>> 117 config M68360
>> 118 bool "MC68360"
>> 119 depends on !MMU
>> 120 select MCPU32
407 help 121 help
408 This enables detection, tunings and !! 122 Motorola 68360 processor support.
409 123
410 You need this enabled if you want yo !! 124 endif # M68KCLASSIC
411 Intel CPU. Disabling this option on <<
412 makes the kernel a tiny bit smaller. <<
413 CPU might render the kernel unbootab <<
414 125
415 If unsure, say N. !! 126 if COLDFIRE
416 127
417 config CPU_SUP_CYRIX_32 !! 128 choice
418 default y !! 129 prompt "ColdFire SoC type"
419 bool "Support Cyrix processors" if PRO !! 130 default M520x
420 depends on M486SX || M486 || M586 || M <<
421 help 131 help
422 This enables detection, tunings and !! 132 Select the type of ColdFire System-on-Chip (SoC) that you want
423 !! 133 to build for.
424 You need this enabled if you want yo <<
425 Cyrix CPU. Disabling this option on <<
426 makes the kernel a tiny bit smaller. <<
427 CPU might render the kernel unbootab <<
428 <<
429 If unsure, say N. <<
430 134
431 config CPU_SUP_AMD !! 135 config M5206
432 default y !! 136 bool "MCF5206"
433 bool "Support AMD processors" if PROCE !! 137 depends on !MMU
>> 138 select COLDFIRE_SW_A7
>> 139 select HAVE_MBAR
>> 140 help
>> 141 Motorola ColdFire 5206 processor support.
>> 142
>> 143 config M5206e
>> 144 bool "MCF5206e"
>> 145 depends on !MMU
>> 146 select COLDFIRE_SW_A7
>> 147 select HAVE_MBAR
>> 148 help
>> 149 Motorola ColdFire 5206e processor support.
>> 150
>> 151 config M520x
>> 152 bool "MCF520x"
>> 153 depends on !MMU
>> 154 select GENERIC_CLOCKEVENTS
>> 155 select HAVE_CACHE_SPLIT
>> 156 help
>> 157 Freescale Coldfire 5207/5208 processor support.
>> 158
>> 159 config M523x
>> 160 bool "MCF523x"
>> 161 depends on !MMU
>> 162 select GENERIC_CLOCKEVENTS
>> 163 select HAVE_CACHE_SPLIT
>> 164 select HAVE_IPSBAR
>> 165 help
>> 166 Freescale Coldfire 5230/1/2/4/5 processor support
>> 167
>> 168 config M5249
>> 169 bool "MCF5249"
>> 170 depends on !MMU
>> 171 select COLDFIRE_SW_A7
>> 172 select HAVE_MBAR
>> 173 help
>> 174 Motorola ColdFire 5249 processor support.
>> 175
>> 176 config M525x
>> 177 bool "MCF525x"
>> 178 depends on !MMU
>> 179 select COLDFIRE_SW_A7
>> 180 select HAVE_MBAR
>> 181 help
>> 182 Freescale (Motorola) Coldfire 5251/5253 processor support.
>> 183
>> 184 config M5271
>> 185 bool "MCF5271"
>> 186 depends on !MMU
>> 187 select M527x
>> 188 select HAVE_CACHE_SPLIT
>> 189 select HAVE_IPSBAR
>> 190 select GENERIC_CLOCKEVENTS
>> 191 help
>> 192 Freescale (Motorola) ColdFire 5270/5271 processor support.
>> 193
>> 194 config M5272
>> 195 bool "MCF5272"
>> 196 depends on !MMU
>> 197 select COLDFIRE_SW_A7
>> 198 select HAVE_MBAR
>> 199 help
>> 200 Motorola ColdFire 5272 processor support.
>> 201
>> 202 config M5275
>> 203 bool "MCF5275"
>> 204 depends on !MMU
>> 205 select M527x
>> 206 select HAVE_CACHE_SPLIT
>> 207 select HAVE_IPSBAR
>> 208 select GENERIC_CLOCKEVENTS
>> 209 help
>> 210 Freescale (Motorola) ColdFire 5274/5275 processor support.
>> 211
>> 212 config M528x
>> 213 bool "MCF528x"
>> 214 depends on !MMU
>> 215 select GENERIC_CLOCKEVENTS
>> 216 select HAVE_CACHE_SPLIT
>> 217 select HAVE_IPSBAR
>> 218 help
>> 219 Motorola ColdFire 5280/5282 processor support.
>> 220
>> 221 config M5307
>> 222 bool "MCF5307"
>> 223 depends on !MMU
>> 224 select COLDFIRE_SW_A7
>> 225 select HAVE_CACHE_CB
>> 226 select HAVE_MBAR
>> 227 help
>> 228 Motorola ColdFire 5307 processor support.
>> 229
>> 230 config M532x
>> 231 bool "MCF532x"
>> 232 depends on !MMU
>> 233 select M53xx
>> 234 select HAVE_CACHE_CB
>> 235 help
>> 236 Freescale (Motorola) ColdFire 532x processor support.
>> 237
>> 238 config M537x
>> 239 bool "MCF537x"
>> 240 depends on !MMU
>> 241 select M53xx
>> 242 select HAVE_CACHE_CB
>> 243 help
>> 244 Freescale ColdFire 537x processor support.
>> 245
>> 246 config M5407
>> 247 bool "MCF5407"
>> 248 depends on !MMU
>> 249 select COLDFIRE_SW_A7
>> 250 select HAVE_CACHE_CB
>> 251 select HAVE_MBAR
>> 252 help
>> 253 Motorola ColdFire 5407 processor support.
>> 254
>> 255 config M547x
>> 256 bool "MCF547x"
>> 257 select M54xx
>> 258 select MMU_COLDFIRE if MMU
>> 259 select HAVE_CACHE_CB
>> 260 select HAVE_MBAR
>> 261 help
>> 262 Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
>> 263
>> 264 config M548x
>> 265 bool "MCF548x"
>> 266 select MMU_COLDFIRE if MMU
>> 267 select M54xx
>> 268 select HAVE_CACHE_CB
>> 269 select HAVE_MBAR
>> 270 help
>> 271 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
>> 272
>> 273 config M5441x
>> 274 bool "MCF5441x"
>> 275 depends on !MMU
>> 276 select GENERIC_CLOCKEVENTS
>> 277 select HAVE_CACHE_CB
434 help 278 help
435 This enables detection, tunings and !! 279 Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
436 280
437 You need this enabled if you want yo !! 281 endchoice
438 AMD CPU. Disabling this option on ot <<
439 makes the kernel a tiny bit smaller. <<
440 CPU might render the kernel unbootab <<
441 282
442 If unsure, say N. !! 283 config M527x
>> 284 bool
443 285
444 config CPU_SUP_HYGON !! 286 config M53xx
445 default y !! 287 bool
446 bool "Support Hygon processors" if PRO <<
447 select CPU_SUP_AMD <<
448 help <<
449 This enables detection, tunings and <<
450 288
451 You need this enabled if you want yo !! 289 config M54xx
452 Hygon CPU. Disabling this option on !! 290 bool
453 makes the kernel a tiny bit smaller. <<
454 CPU might render the kernel unbootab <<
455 291
456 If unsure, say N. !! 292 endif # COLDFIRE
457 !! 293
458 config CPU_SUP_CENTAUR !! 294
>> 295 comment "Processor Specific Options"
>> 296
>> 297 config M68KFPU_EMU
>> 298 bool "Math emulation support"
>> 299 depends on MMU
>> 300 help
>> 301 At some point in the future, this will cause floating-point math
>> 302 instructions to be emulated by the kernel on machines that lack a
>> 303 floating-point math coprocessor. Thrill-seekers and chronically
>> 304 sleep-deprived psychotic hacker types can say Y now, everyone else
>> 305 should probably wait a while.
>> 306
>> 307 config M68KFPU_EMU_EXTRAPREC
>> 308 bool "Math emulation extra precision"
>> 309 depends on M68KFPU_EMU
>> 310 help
>> 311 The fpu uses normally a few bit more during calculations for
>> 312 correct rounding, the emulator can (often) do the same but this
>> 313 extra calculation can cost quite some time, so you can disable
>> 314 it here. The emulator will then "only" calculate with a 64 bit
>> 315 mantissa and round slightly incorrect, what is more than enough
>> 316 for normal usage.
>> 317
>> 318 config M68KFPU_EMU_ONLY
>> 319 bool "Math emulation only kernel"
>> 320 depends on M68KFPU_EMU
>> 321 help
>> 322 This option prevents any floating-point instructions from being
>> 323 compiled into the kernel, thereby the kernel doesn't save any
>> 324 floating point context anymore during task switches, so this
>> 325 kernel will only be usable on machines without a floating-point
>> 326 math coprocessor. This makes the kernel a bit faster as no tests
>> 327 needs to be executed whether a floating-point instruction in the
>> 328 kernel should be executed or not.
>> 329
>> 330 config ADVANCED
>> 331 bool "Advanced configuration options"
>> 332 depends on MMU
>> 333 ---help---
>> 334 This gives you access to some advanced options for the CPU. The
>> 335 defaults should be fine for most users, but these options may make
>> 336 it possible for you to improve performance somewhat if you know what
>> 337 you are doing.
>> 338
>> 339 Note that the answer to this question won't directly affect the
>> 340 kernel: saying N will just cause the configurator to skip all
>> 341 the questions about these options.
>> 342
>> 343 Most users should say N to this question.
>> 344
>> 345 config RMW_INSNS
>> 346 bool "Use read-modify-write instructions"
>> 347 depends on ADVANCED
>> 348 ---help---
>> 349 This allows to use certain instructions that work with indivisible
>> 350 read-modify-write bus cycles. While this is faster than the
>> 351 workaround of disabling interrupts, it can conflict with DMA
>> 352 ( = direct memory access) on many Amiga systems, and it is also said
>> 353 to destabilize other machines. It is very likely that this will
>> 354 cause serious problems on any Amiga or Atari Medusa if set. The only
>> 355 configuration where it should work are 68030-based Ataris, where it
>> 356 apparently improves performance. But you've been warned! Unless you
>> 357 really know what you are doing, say N. Try Y only if you're quite
>> 358 adventurous.
>> 359
>> 360 config SINGLE_MEMORY_CHUNK
>> 361 bool "Use one physical chunk of memory only" if ADVANCED && !SUN3
>> 362 depends on MMU
>> 363 default y if SUN3
>> 364 select NEED_MULTIPLE_NODES
>> 365 help
>> 366 Ignore all but the first contiguous chunk of physical memory for VM
>> 367 purposes. This will save a few bytes kernel size and may speed up
>> 368 some operations. Say N if not sure.
>> 369
>> 370 config ARCH_DISCONTIGMEM_ENABLE
>> 371 def_bool MMU && !SINGLE_MEMORY_CHUNK
>> 372
>> 373 config 060_WRITETHROUGH
>> 374 bool "Use write-through caching for 68060 supervisor accesses"
>> 375 depends on ADVANCED && M68060
>> 376 ---help---
>> 377 The 68060 generally uses copyback caching of recently accessed data.
>> 378 Copyback caching means that memory writes will be held in an on-chip
>> 379 cache and only written back to memory some time later. Saying Y
>> 380 here will force supervisor (kernel) accesses to use writethrough
>> 381 caching. Writethrough caching means that data is written to memory
>> 382 straight away, so that cache and memory data always agree.
>> 383 Writethrough caching is less efficient, but is needed for some
>> 384 drivers on 68060 based systems where the 68060 bus snooping signal
>> 385 is hardwired on. The 53c710 SCSI driver is known to suffer from
>> 386 this problem.
>> 387
>> 388 config M68K_L2_CACHE
>> 389 bool
>> 390 depends on MAC
459 default y 391 default y
460 bool "Support Centaur processors" if P <<
461 help <<
462 This enables detection, tunings and <<
463 <<
464 You need this enabled if you want yo <<
465 Centaur CPU. Disabling this option o <<
466 makes the kernel a tiny bit smaller. <<
467 CPU might render the kernel unbootab <<
468 392
469 If unsure, say N. !! 393 config NODES_SHIFT
470 !! 394 int
471 config CPU_SUP_TRANSMETA_32 !! 395 default "3"
472 default y !! 396 depends on !SINGLE_MEMORY_CHUNK
473 bool "Support Transmeta processors" if <<
474 depends on !64BIT <<
475 help <<
476 This enables detection, tunings and <<
477 397
478 You need this enabled if you want yo !! 398 config CPU_HAS_NO_BITFIELDS
479 Transmeta CPU. Disabling this option !! 399 bool
480 makes the kernel a tiny bit smaller. <<
481 CPU might render the kernel unbootab <<
482 400
483 If unsure, say N. !! 401 config CPU_HAS_NO_MULDIV64
>> 402 bool
484 403
485 config CPU_SUP_UMC_32 !! 404 config CPU_HAS_NO_UNALIGNED
486 default y !! 405 bool
487 bool "Support UMC processors" if PROCE !! 406
488 depends on M486SX || M486 || (EXPERT & !! 407 config CPU_HAS_ADDRESS_SPACES
>> 408 bool
>> 409
>> 410 config FPU
>> 411 bool
>> 412
>> 413 config COLDFIRE_SW_A7
>> 414 bool
>> 415
>> 416 config HAVE_CACHE_SPLIT
>> 417 bool
>> 418
>> 419 config HAVE_CACHE_CB
>> 420 bool
>> 421
>> 422 config HAVE_MBAR
>> 423 bool
>> 424
>> 425 config HAVE_IPSBAR
>> 426 bool
>> 427
>> 428 config CLOCK_FREQ
>> 429 int "Set the core clock frequency"
>> 430 default "25000000" if M5206
>> 431 default "54000000" if M5206e
>> 432 default "166666666" if M520x
>> 433 default "140000000" if M5249
>> 434 default "150000000" if M527x || M523x
>> 435 default "90000000" if M5307
>> 436 default "50000000" if M5407
>> 437 default "266000000" if M54xx
>> 438 default "66666666"
>> 439 depends on COLDFIRE
>> 440 help
>> 441 Define the CPU clock frequency in use. This is the core clock
>> 442 frequency, it may or may not be the same as the external clock
>> 443 crystal fitted to your board. Some processors have an internal
>> 444 PLL and can have their frequency programmed at run time, others
>> 445 use internal dividers. In general the kernel won't setup a PLL
>> 446 if it is fitted (there are some exceptions). This value will be
>> 447 specific to the exact CPU that you are using.
>> 448
>> 449 config OLDMASK
>> 450 bool "Old mask 5307 (1H55J) silicon"
>> 451 depends on M5307
489 help 452 help
490 This enables detection, tunings and !! 453 Build support for the older revision ColdFire 5307 silicon.
>> 454 Specifically this is the 1H55J mask revision.
491 455
492 You need this enabled if you want yo !! 456 if HAVE_CACHE_SPLIT
493 UMC CPU. Disabling this option on ot !! 457 choice
494 makes the kernel a tiny bit smaller. !! 458 prompt "Split Cache Configuration"
495 CPU might render the kernel unbootab !! 459 default CACHE_I
496 460
497 If unsure, say N. !! 461 config CACHE_I
>> 462 bool "Instruction"
>> 463 help
>> 464 Use all of the ColdFire CPU cache memory as an instruction cache.
498 465
499 config CPU_SUP_ZHAOXIN !! 466 config CACHE_D
500 default y !! 467 bool "Data"
501 bool "Support Zhaoxin processors" if P <<
502 help 468 help
503 This enables detection, tunings and !! 469 Use all of the ColdFire CPU cache memory as a data cache.
504 470
505 You need this enabled if you want yo !! 471 config CACHE_BOTH
506 Zhaoxin CPU. Disabling this option o !! 472 bool "Both"
507 makes the kernel a tiny bit smaller. !! 473 help
508 CPU might render the kernel unbootab !! 474 Split the ColdFire CPU cache, and use half as an instruction cache
>> 475 and half as a data cache.
>> 476 endchoice
>> 477 endif
509 478
510 If unsure, say N. !! 479 if HAVE_CACHE_CB
>> 480 choice
>> 481 prompt "Data cache mode"
>> 482 default CACHE_WRITETHRU
511 483
512 config CPU_SUP_VORTEX_32 !! 484 config CACHE_WRITETHRU
513 default y !! 485 bool "Write-through"
514 bool "Support Vortex processors" if PR <<
515 depends on X86_32 <<
516 help 486 help
517 This enables detection, tunings and !! 487 The ColdFire CPU cache is set into Write-through mode.
518 488
519 You need this enabled if you want yo !! 489 config CACHE_COPYBACK
520 Vortex CPU. Disabling this option on !! 490 bool "Copy-back"
521 makes the kernel a tiny bit smaller. !! 491 help
>> 492 The ColdFire CPU cache is set into Copy-back mode.
>> 493 endchoice
>> 494 endif
522 495
523 If unsure, say N. <<
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