1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 # Put here option for CPU selection and depend !! 2 comment "Processor Type"
>> 3
3 choice 4 choice
4 prompt "Processor family" !! 5 prompt "CPU family support"
5 default M686 if X86_32 !! 6 default M68KCLASSIC if MMU
6 default GENERIC_CPU if X86_64 !! 7 default COLDFIRE if !MMU
7 help !! 8 help
8 This is the processor type of your C !! 9 The Freescale (was Motorola) M68K family of processors implements
9 used for optimizing purposes. In ord !! 10 the full 68000 processor instruction set.
10 that can run on all supported x86 CP !! 11 The Freescale ColdFire family of processors is a modern derivative
11 optimally fast), you can specify "48 !! 12 of the 68000 processor family. They are mainly targeted at embedded
12 !! 13 applications, and are all System-On-Chip (SOC) devices, as opposed
13 Note that the 386 is no longer suppo !! 14 to stand alone CPUs. They implement a subset of the original 68000
14 AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, !! 15 processor instruction set.
15 UMC 486SX-S and the NexGen Nx586. !! 16 If you anticipate running this kernel on a computer with a classic
16 !! 17 MC68xxx processor, select M68KCLASSIC.
17 The kernel will not necessarily run !! 18 If you anticipate running this kernel on a computer with a ColdFire
18 the one you have chosen, e.g. a Pent !! 19 processor, select COLDFIRE.
19 a PPro, but not necessarily on a i48 !! 20
20 !! 21 config M68KCLASSIC
21 Here are the settings recommended fo !! 22 bool "Classic M68K CPU family support"
22 - "486" for the AMD/Cyrix/IBM/Intel !! 23 select HAVE_ARCH_PFN_VALID
23 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5 !! 24
24 - "586" for generic Pentium CPUs lac !! 25 config COLDFIRE
25 (time stamp counter) register. !! 26 bool "Coldfire CPU family support"
26 - "Pentium-Classic" for the Intel Pe !! 27 select ARCH_HAVE_CUSTOM_GPIO_H
27 - "Pentium-MMX" for the Intel Pentiu !! 28 select CPU_HAS_NO_BITFIELDS
28 - "Pentium-Pro" for the Intel Pentiu !! 29 select CPU_HAS_NO_MULDIV64
29 - "Pentium-II" for the Intel Pentium !! 30 select GENERIC_CSUM
30 - "Pentium-III" for the Intel Pentiu !! 31 select GPIOLIB
31 - "Pentium-4" for the Intel Pentium !! 32 select HAVE_LEGACY_CLK
32 - "K6" for the AMD K6, K6-II and K6- <<
33 - "Athlon" for the AMD K7 family (At <<
34 - "Opteron/Athlon64/Hammer/K8" for a <<
35 - "Crusoe" for the Transmeta Crusoe <<
36 - "Efficeon" for the Transmeta Effic <<
37 - "Winchip-C6" for original IDT Winc <<
38 - "Winchip-2" for IDT Winchips with <<
39 - "AMD Elan" for the 32-bit AMD Elan <<
40 - "GeodeGX1" for Geode GX1 (Cyrix Me <<
41 - "Geode GX/LX" For AMD Geode GX and <<
42 - "CyrixIII/VIA C3" for VIA Cyrix II <<
43 - "VIA C3-2" for VIA C3-2 "Nehemiah" <<
44 - "VIA C7" for VIA C7. <<
45 - "Intel P4" for the Pentium 4/Netbu <<
46 - "Core 2/newer Xeon" for all core2 <<
47 - "Intel Atom" for the Atom-microarc <<
48 - "Generic-x86-64" for a kernel whic <<
49 <<
50 See each option's help text for addi <<
51 what to do, choose "486". <<
52 <<
53 config M486SX <<
54 bool "486SX" <<
55 depends on X86_32 <<
56 help <<
57 Select this for an 486-class CPU wit <<
58 AMD/Cyrix/IBM/Intel SL/SLC/SLC2/SLC3 <<
59 <<
60 config M486 <<
61 bool "486DX" <<
62 depends on X86_32 <<
63 help <<
64 Select this for an 486-class CPU suc <<
65 486DX/DX2/DX4 and UMC U5D. <<
66 <<
67 config M586 <<
68 bool "586/K5/5x86/6x86/6x86MX" <<
69 depends on X86_32 <<
70 help <<
71 Select this for an 586 or 686 series <<
72 the Cyrix 5x86, 6x86 and 6x86MX. Th <<
73 assume the RDTSC (Read Time Stamp Co <<
74 <<
75 config M586TSC <<
76 bool "Pentium-Classic" <<
77 depends on X86_32 <<
78 help <<
79 Select this for a Pentium Classic pr <<
80 Time Stamp Counter) instruction for <<
81 <<
82 config M586MMX <<
83 bool "Pentium-MMX" <<
84 depends on X86_32 <<
85 help <<
86 Select this for a Pentium with the M <<
87 extended instructions. <<
88 <<
89 config M686 <<
90 bool "Pentium-Pro" <<
91 depends on X86_32 <<
92 help <<
93 Select this for Intel Pentium Pro ch <<
94 Pentium Pro extended instructions, a <<
95 against the f00f bug found in earlie <<
96 <<
97 config MPENTIUMII <<
98 bool "Pentium-II/Celeron(pre-Coppermin <<
99 depends on X86_32 <<
100 help <<
101 Select this for Intel chips based on <<
102 pre-Coppermine Celeron core. This o <<
103 copy optimization, compiles the kern <<
104 tailored for the chip, and applies a <<
105 optimizations. <<
106 <<
107 config MPENTIUMIII <<
108 bool "Pentium-III/Celeron(Coppermine)/ <<
109 depends on X86_32 <<
110 help <<
111 Select this for Intel chips based on <<
112 Celeron-Coppermine core. This optio <<
113 extended prefetch instructions in ad <<
114 extensions. <<
115 <<
116 config MPENTIUMM <<
117 bool "Pentium M" <<
118 depends on X86_32 <<
119 help <<
120 Select this for Intel Pentium M (not <<
121 notebook chips. <<
122 <<
123 config MPENTIUM4 <<
124 bool "Pentium-4/Celeron(P4-based)/Pent <<
125 depends on X86_32 <<
126 help <<
127 Select this for Intel Pentium 4 chip <<
128 Pentium 4, Pentium D, P4-based Celer <<
129 Pentium-4 M (not Pentium M) chips. <<
130 flags optimized for the chip, uses t <<
131 applies any applicable optimizations <<
132 <<
133 CPUIDs: F[0-6][1-A] (in /proc/cpuinf <<
134 <<
135 Select this for: <<
136 Pentiums (Pentium 4, Pentium D, Ce <<
137 -Willamette <<
138 -Northwood <<
139 -Mobile Pentium 4 <<
140 -Mobile Pentium 4 M <<
141 -Extreme Edition (Gallatin) <<
142 -Prescott <<
143 -Prescott 2M <<
144 -Cedar Mill <<
145 -Presler <<
146 -Smithfiled <<
147 Xeons (Intel Xeon, Xeon MP, Xeon L <<
148 -Foster <<
149 -Prestonia <<
150 -Gallatin <<
151 -Nocona <<
152 -Irwindale <<
153 -Cranford <<
154 -Potomac <<
155 -Paxville <<
156 -Dempsey <<
157 <<
158 <<
159 config MK6 <<
160 bool "K6/K6-II/K6-III" <<
161 depends on X86_32 <<
162 help <<
163 Select this for an AMD K6-family pro <<
164 some extended instructions, and pass <<
165 flags to GCC. <<
166 <<
167 config MK7 <<
168 bool "Athlon/Duron/K7" <<
169 depends on X86_32 <<
170 help <<
171 Select this for an AMD Athlon K7-fam <<
172 some extended instructions, and pass <<
173 flags to GCC. <<
174 <<
175 config MK8 <<
176 bool "Opteron/Athlon64/Hammer/K8" <<
177 help <<
178 Select this for an AMD Opteron or At <<
179 Enables use of some extended instruc <<
180 optimization flags to GCC. <<
181 <<
182 config MCRUSOE <<
183 bool "Crusoe" <<
184 depends on X86_32 <<
185 help <<
186 Select this for a Transmeta Crusoe p <<
187 like a 586 with TSC, and sets some G <<
188 Pentium Pro with no alignment requir <<
189 <<
190 config MEFFICEON <<
191 bool "Efficeon" <<
192 depends on X86_32 <<
193 help <<
194 Select this for a Transmeta Efficeon <<
195 <<
196 config MWINCHIPC6 <<
197 bool "Winchip-C6" <<
198 depends on X86_32 <<
199 help <<
200 Select this for an IDT Winchip C6 ch <<
201 treat this chip as a 586TSC with som <<
202 and alignment requirements. <<
203 <<
204 config MWINCHIP3D <<
205 bool "Winchip-2/Winchip-2A/Winchip-3" <<
206 depends on X86_32 <<
207 help <<
208 Select this for an IDT Winchip-2, 2A <<
209 treat this chip as a 586TSC with som <<
210 and alignment requirements. Also en <<
211 stores for this CPU, which can incre <<
212 operations. <<
213 <<
214 config MELAN <<
215 bool "AMD Elan" <<
216 depends on X86_32 <<
217 help <<
218 Select this for an AMD Elan processo <<
219 <<
220 Do not use this option for K6/Athlon <<
221 <<
222 config MGEODEGX1 <<
223 bool "GeodeGX1" <<
224 depends on X86_32 <<
225 help <<
226 Select this for a Geode GX1 (Cyrix M <<
227 <<
228 config MGEODE_LX <<
229 bool "Geode GX/LX" <<
230 depends on X86_32 <<
231 help <<
232 Select this for AMD Geode GX and LX <<
233 <<
234 config MCYRIXIII <<
235 bool "CyrixIII/VIA-C3" <<
236 depends on X86_32 <<
237 help <<
238 Select this for a Cyrix III or C3 ch <<
239 treat this chip as a generic 586. Wh <<
240 it lacks the cmov extension which gc <<
241 generating 686 code. <<
242 Note that Nehemiah (Model 9) and abo <<
243 kernel due to them lacking the 3DNow <<
244 incarnations of the CPU. <<
245 <<
246 config MVIAC3_2 <<
247 bool "VIA C3-2 (Nehemiah)" <<
248 depends on X86_32 <<
249 help <<
250 Select this for a VIA C3 "Nehemiah". <<
251 of SSE and tells gcc to treat the CP <<
252 Note, this kernel will not boot on o <<
253 <<
254 config MVIAC7 <<
255 bool "VIA C7" <<
256 depends on X86_32 <<
257 help <<
258 Select this for a VIA C7. Selecting <<
259 shift and tells gcc to treat the CPU <<
260 <<
261 config MPSC <<
262 bool "Intel P4 / older Netburst based <<
263 depends on X86_64 <<
264 help <<
265 Optimize for Intel Pentium 4, Pentiu <<
266 Xeon CPUs with Intel 64bit which is <<
267 Note that the latest Xeons (Xeon 51x <<
268 Netburst core and shouldn't use this <<
269 using the cpu family field <<
270 in /proc/cpuinfo. Family 15 is an ol <<
271 <<
272 config MCORE2 <<
273 bool "Core 2/newer Xeon" <<
274 help <<
275 <<
276 Select this for Intel Core 2 and new <<
277 53xx) CPUs. You can distinguish newe <<
278 family in /proc/cpuinfo. Newer ones <<
279 (not a typo) <<
280 <<
281 config MATOM <<
282 bool "Intel Atom" <<
283 help <<
284 <<
285 Select this for the Intel Atom platf <<
286 in-order pipelining architecture and <<
287 accordingly optimized code. Use a re <<
288 support in order to fully benefit fr <<
289 <<
290 config GENERIC_CPU <<
291 bool "Generic-x86-64" <<
292 depends on X86_64 <<
293 help <<
294 Generic x86-64 CPU. <<
295 Run equally well on all x86-64 CPUs. <<
296 33
297 endchoice 34 endchoice
298 35
299 config X86_GENERIC !! 36 if M68KCLASSIC
300 bool "Generic x86 support" <<
301 depends on X86_32 <<
302 help <<
303 Instead of just including optimizati <<
304 x86 variant (e.g. PII, Crusoe or Ath <<
305 generic optimizations as well. This <<
306 perform better on x86 CPUs other tha <<
307 <<
308 This is really intended for distribu <<
309 generic optimizations. <<
310 <<
311 # <<
312 # Define implied options from the CPU selectio <<
313 config X86_INTERNODE_CACHE_SHIFT <<
314 int <<
315 default "12" if X86_VSMP <<
316 default X86_L1_CACHE_SHIFT <<
317 <<
318 config X86_L1_CACHE_SHIFT <<
319 int <<
320 default "7" if MPENTIUM4 || MPSC <<
321 default "6" if MK7 || MK8 || MPENTIUMM <<
322 default "4" if MELAN || M486SX || M486 <<
323 default "5" if MWINCHIP3D || MWINCHIPC <<
324 <<
325 config X86_F00F_BUG <<
326 def_bool y <<
327 depends on M586MMX || M586TSC || M586 <<
328 <<
329 config X86_INVD_BUG <<
330 def_bool y <<
331 depends on M486SX || M486 <<
332 <<
333 config X86_ALIGNMENT_16 <<
334 def_bool y <<
335 depends on MWINCHIP3D || MWINCHIPC6 || <<
336 <<
337 config X86_INTEL_USERCOPY <<
338 def_bool y <<
339 depends on MPENTIUM4 || MPENTIUMM || M <<
340 <<
341 config X86_USE_PPRO_CHECKSUM <<
342 def_bool y <<
343 depends on MWINCHIP3D || MWINCHIPC6 || <<
344 <<
345 # <<
346 # P6_NOPs are a relatively minor optimization <<
347 # 6 processor, except that it is broken on cer <<
348 # Furthermore, AMD chips prefer a totally diff <<
349 # (which work on all CPUs). In addition, it l <<
350 # does not understand them. <<
351 # <<
352 # As a result, disallow these if we're not com <<
353 # NOPs do work on all x86-64 capable chips); t <<
354 # the right-hand clause are the cores that ben <<
355 # <<
356 config X86_P6_NOP <<
357 def_bool y <<
358 depends on X86_64 <<
359 depends on (MCORE2 || MPENTIUM4 || MPS <<
360 <<
361 config X86_TSC <<
362 def_bool y <<
363 depends on (MWINCHIP3D || MCRUSOE || M <<
364 <<
365 config X86_HAVE_PAE <<
366 def_bool y <<
367 depends on MCRUSOE || MEFFICEON || MCY <<
368 <<
369 config X86_CMPXCHG64 <<
370 def_bool y <<
371 depends on X86_HAVE_PAE || M586TSC || <<
372 <<
373 # this should be set for all -march=.. options <<
374 # generates cmov. <<
375 config X86_CMOV <<
376 def_bool y <<
377 depends on (MK8 || MK7 || MCORE2 || MP <<
378 <<
379 config X86_MINIMUM_CPU_FAMILY <<
380 int <<
381 default "64" if X86_64 <<
382 default "6" if X86_32 && (MPENTIUM4 || <<
383 default "5" if X86_32 && X86_CMPXCHG64 <<
384 default "4" <<
385 <<
386 config X86_DEBUGCTLMSR <<
387 def_bool y <<
388 depends on !(MK6 || MWINCHIPC6 || MWIN <<
389 <<
390 config IA32_FEAT_CTL <<
391 def_bool y <<
392 depends on CPU_SUP_INTEL || CPU_SUP_CE <<
393 <<
394 config X86_VMX_FEATURE_NAMES <<
395 def_bool y <<
396 depends on IA32_FEAT_CTL <<
397 <<
398 menuconfig PROCESSOR_SELECT <<
399 bool "Supported processor vendors" if <<
400 help <<
401 This lets you choose what x86 vendor <<
402 will include. <<
403 37
404 config CPU_SUP_INTEL !! 38 config M68000
405 default y !! 39 bool
406 bool "Support Intel processors" if PRO !! 40 depends on !MMU
>> 41 select CPU_HAS_NO_BITFIELDS
>> 42 select CPU_HAS_NO_MULDIV64
>> 43 select CPU_HAS_NO_UNALIGNED
>> 44 select GENERIC_CSUM
>> 45 select CPU_NO_EFFICIENT_FFS
>> 46 select HAVE_ARCH_HASH
>> 47 help
>> 48 The Freescale (was Motorola) 68000 CPU is the first generation of
>> 49 the well known M68K family of processors. The CPU core as well as
>> 50 being available as a stand alone CPU was also used in many
>> 51 System-On-Chip devices (eg 68328, 68302, etc). It does not contain
>> 52 a paging MMU.
>> 53
>> 54 config MCPU32
>> 55 bool
>> 56 select CPU_HAS_NO_BITFIELDS
>> 57 select CPU_HAS_NO_UNALIGNED
>> 58 select CPU_NO_EFFICIENT_FFS
>> 59 help
>> 60 The Freescale (was then Motorola) CPU32 is a CPU core that is
>> 61 based on the 68020 processor. For the most part it is used in
>> 62 System-On-Chip parts, and does not contain a paging MMU.
>> 63
>> 64 config M68020
>> 65 bool "68020 support"
>> 66 depends on MMU
>> 67 select FPU
>> 68 select CPU_HAS_ADDRESS_SPACES
>> 69 help
>> 70 If you anticipate running this kernel on a computer with a MC68020
>> 71 processor, say Y. Otherwise, say N. Note that the 68020 requires a
>> 72 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the
>> 73 Sun 3, which provides its own version.
>> 74
>> 75 config M68030
>> 76 bool "68030 support"
>> 77 depends on MMU && !MMU_SUN3
>> 78 select FPU
>> 79 select CPU_HAS_ADDRESS_SPACES
>> 80 help
>> 81 If you anticipate running this kernel on a computer with a MC68030
>> 82 processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
>> 83 work, as it does not include an MMU (Memory Management Unit).
>> 84
>> 85 config M68040
>> 86 bool "68040 support"
>> 87 depends on MMU && !MMU_SUN3
>> 88 select FPU
>> 89 select CPU_HAS_ADDRESS_SPACES
>> 90 help
>> 91 If you anticipate running this kernel on a computer with a MC68LC040
>> 92 or MC68040 processor, say Y. Otherwise, say N. Note that an
>> 93 MC68EC040 will not work, as it does not include an MMU (Memory
>> 94 Management Unit).
>> 95
>> 96 config M68060
>> 97 bool "68060 support"
>> 98 depends on MMU && !MMU_SUN3
>> 99 select FPU
>> 100 select CPU_HAS_ADDRESS_SPACES
>> 101 help
>> 102 If you anticipate running this kernel on a computer with a MC68060
>> 103 processor, say Y. Otherwise, say N.
>> 104
>> 105 config M68328
>> 106 bool
>> 107 depends on !MMU
>> 108 select LEGACY_TIMER_TICK
>> 109 select M68000
>> 110 help
>> 111 Motorola 68328 processor support.
>> 112
>> 113 config M68EZ328
>> 114 bool
>> 115 depends on !MMU
>> 116 select LEGACY_TIMER_TICK
>> 117 select M68000
>> 118 help
>> 119 Motorola 68EX328 processor support.
>> 120
>> 121 config M68VZ328
>> 122 bool
>> 123 depends on !MMU
>> 124 select LEGACY_TIMER_TICK
>> 125 select M68000
407 help 126 help
408 This enables detection, tunings and !! 127 Motorola 68VZ328 processor support.
409 128
410 You need this enabled if you want yo !! 129 endif # M68KCLASSIC
411 Intel CPU. Disabling this option on <<
412 makes the kernel a tiny bit smaller. <<
413 CPU might render the kernel unbootab <<
414 130
415 If unsure, say N. !! 131 if COLDFIRE
416 132
417 config CPU_SUP_CYRIX_32 !! 133 choice
418 default y !! 134 prompt "ColdFire SoC type"
419 bool "Support Cyrix processors" if PRO !! 135 default M520x
420 depends on M486SX || M486 || M586 || M <<
421 help 136 help
422 This enables detection, tunings and !! 137 Select the type of ColdFire System-on-Chip (SoC) that you want
423 !! 138 to build for.
424 You need this enabled if you want yo <<
425 Cyrix CPU. Disabling this option on <<
426 makes the kernel a tiny bit smaller. <<
427 CPU might render the kernel unbootab <<
428 <<
429 If unsure, say N. <<
430 139
431 config CPU_SUP_AMD !! 140 config M5206
432 default y !! 141 bool "MCF5206"
433 bool "Support AMD processors" if PROCE !! 142 depends on !MMU
>> 143 select COLDFIRE_SW_A7
>> 144 select COLDFIRE_TIMERS
>> 145 select HAVE_MBAR
>> 146 select CPU_NO_EFFICIENT_FFS
>> 147 help
>> 148 Motorola ColdFire 5206 processor support.
>> 149
>> 150 config M5206e
>> 151 bool "MCF5206e"
>> 152 depends on !MMU
>> 153 select COLDFIRE_SW_A7
>> 154 select COLDFIRE_TIMERS
>> 155 select HAVE_MBAR
>> 156 select CPU_NO_EFFICIENT_FFS
>> 157 help
>> 158 Motorola ColdFire 5206e processor support.
>> 159
>> 160 config M520x
>> 161 bool "MCF520x"
>> 162 depends on !MMU
>> 163 select COLDFIRE_PIT_TIMER
>> 164 select HAVE_CACHE_SPLIT
>> 165 help
>> 166 Freescale Coldfire 5207/5208 processor support.
>> 167
>> 168 config M523x
>> 169 bool "MCF523x"
>> 170 depends on !MMU
>> 171 select COLDFIRE_PIT_TIMER
>> 172 select HAVE_CACHE_SPLIT
>> 173 select HAVE_IPSBAR
>> 174 help
>> 175 Freescale Coldfire 5230/1/2/4/5 processor support
>> 176
>> 177 config M5249
>> 178 bool "MCF5249"
>> 179 depends on !MMU
>> 180 select COLDFIRE_SW_A7
>> 181 select COLDFIRE_TIMERS
>> 182 select HAVE_MBAR
>> 183 select CPU_NO_EFFICIENT_FFS
>> 184 help
>> 185 Motorola ColdFire 5249 processor support.
>> 186
>> 187 config M525x
>> 188 bool "MCF525x"
>> 189 depends on !MMU
>> 190 select COLDFIRE_SW_A7
>> 191 select COLDFIRE_TIMERS
>> 192 select HAVE_MBAR
>> 193 select CPU_NO_EFFICIENT_FFS
>> 194 help
>> 195 Freescale (Motorola) Coldfire 5251/5253 processor support.
>> 196
>> 197 config M5271
>> 198 bool "MCF5271"
>> 199 depends on !MMU
>> 200 select COLDFIRE_PIT_TIMER
>> 201 select M527x
>> 202 select HAVE_CACHE_SPLIT
>> 203 select HAVE_IPSBAR
>> 204 help
>> 205 Freescale (Motorola) ColdFire 5270/5271 processor support.
>> 206
>> 207 config M5272
>> 208 bool "MCF5272"
>> 209 depends on !MMU
>> 210 select COLDFIRE_SW_A7
>> 211 select COLDFIRE_TIMERS
>> 212 select HAVE_MBAR
>> 213 select CPU_NO_EFFICIENT_FFS
>> 214 help
>> 215 Motorola ColdFire 5272 processor support.
>> 216
>> 217 config M5275
>> 218 bool "MCF5275"
>> 219 depends on !MMU
>> 220 select COLDFIRE_PIT_TIMER
>> 221 select M527x
>> 222 select HAVE_CACHE_SPLIT
>> 223 select HAVE_IPSBAR
>> 224 help
>> 225 Freescale (Motorola) ColdFire 5274/5275 processor support.
>> 226
>> 227 config M528x
>> 228 bool "MCF528x"
>> 229 depends on !MMU
>> 230 select COLDFIRE_PIT_TIMER
>> 231 select HAVE_CACHE_SPLIT
>> 232 select HAVE_IPSBAR
>> 233 help
>> 234 Motorola ColdFire 5280/5282 processor support.
>> 235
>> 236 config M5307
>> 237 bool "MCF5307"
>> 238 depends on !MMU
>> 239 select COLDFIRE_TIMERS
>> 240 select COLDFIRE_SW_A7
>> 241 select HAVE_CACHE_CB
>> 242 select HAVE_MBAR
>> 243 select CPU_NO_EFFICIENT_FFS
>> 244 help
>> 245 Motorola ColdFire 5307 processor support.
>> 246
>> 247 config M532x
>> 248 bool "MCF532x"
>> 249 depends on !MMU
>> 250 select COLDFIRE_TIMERS
>> 251 select M53xx
>> 252 select HAVE_CACHE_CB
>> 253 help
>> 254 Freescale (Motorola) ColdFire 532x processor support.
>> 255
>> 256 config M537x
>> 257 bool "MCF537x"
>> 258 depends on !MMU
>> 259 select COLDFIRE_TIMERS
>> 260 select M53xx
>> 261 select HAVE_CACHE_CB
>> 262 help
>> 263 Freescale ColdFire 537x processor support.
>> 264
>> 265 config M5407
>> 266 bool "MCF5407"
>> 267 depends on !MMU
>> 268 select COLDFIRE_SW_A7
>> 269 select COLDFIRE_TIMERS
>> 270 select HAVE_CACHE_CB
>> 271 select HAVE_MBAR
>> 272 select CPU_NO_EFFICIENT_FFS
>> 273 help
>> 274 Motorola ColdFire 5407 processor support.
>> 275
>> 276 config M547x
>> 277 bool "MCF547x"
>> 278 select M54xx
>> 279 select COLDFIRE_SLTIMERS
>> 280 select MMU_COLDFIRE if MMU
>> 281 select FPU if MMU
>> 282 select HAVE_CACHE_CB
>> 283 select HAVE_MBAR
>> 284 select CPU_NO_EFFICIENT_FFS
>> 285 help
>> 286 Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
>> 287
>> 288 config M548x
>> 289 bool "MCF548x"
>> 290 select COLDFIRE_SLTIMERS
>> 291 select MMU_COLDFIRE if MMU
>> 292 select FPU if MMU
>> 293 select M54xx
>> 294 select HAVE_CACHE_CB
>> 295 select HAVE_MBAR
>> 296 select CPU_NO_EFFICIENT_FFS
>> 297 help
>> 298 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
>> 299
>> 300 config M5441x
>> 301 bool "MCF5441x"
>> 302 select COLDFIRE_PIT_TIMER
>> 303 select MMU_COLDFIRE if MMU
>> 304 select HAVE_CACHE_CB
434 help 305 help
435 This enables detection, tunings and !! 306 Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
436 <<
437 You need this enabled if you want yo <<
438 AMD CPU. Disabling this option on ot <<
439 makes the kernel a tiny bit smaller. <<
440 CPU might render the kernel unbootab <<
441 307
442 If unsure, say N. !! 308 endchoice
443 <<
444 config CPU_SUP_HYGON <<
445 default y <<
446 bool "Support Hygon processors" if PRO <<
447 select CPU_SUP_AMD <<
448 help <<
449 This enables detection, tunings and <<
450 309
451 You need this enabled if you want yo !! 310 config M527x
452 Hygon CPU. Disabling this option on !! 311 bool
453 makes the kernel a tiny bit smaller. <<
454 CPU might render the kernel unbootab <<
455 312
456 If unsure, say N. !! 313 config M53xx
>> 314 bool
457 315
458 config CPU_SUP_CENTAUR !! 316 config M54xx
>> 317 select HAVE_PCI
>> 318 bool
>> 319
>> 320 config COLDFIRE_PIT_TIMER
>> 321 bool
>> 322
>> 323 config COLDFIRE_TIMERS
>> 324 bool
>> 325 select LEGACY_TIMER_TICK
>> 326
>> 327 config COLDFIRE_SLTIMERS
>> 328 bool
>> 329 select LEGACY_TIMER_TICK
>> 330
>> 331 endif # COLDFIRE
>> 332
>> 333
>> 334 comment "Processor Specific Options"
>> 335
>> 336 config M68KFPU_EMU
>> 337 bool "Math emulation support"
>> 338 depends on MMU
>> 339 help
>> 340 At some point in the future, this will cause floating-point math
>> 341 instructions to be emulated by the kernel on machines that lack a
>> 342 floating-point math coprocessor. Thrill-seekers and chronically
>> 343 sleep-deprived psychotic hacker types can say Y now, everyone else
>> 344 should probably wait a while.
>> 345
>> 346 config M68KFPU_EMU_EXTRAPREC
>> 347 bool "Math emulation extra precision"
>> 348 depends on M68KFPU_EMU
>> 349 help
>> 350 The fpu uses normally a few bit more during calculations for
>> 351 correct rounding, the emulator can (often) do the same but this
>> 352 extra calculation can cost quite some time, so you can disable
>> 353 it here. The emulator will then "only" calculate with a 64 bit
>> 354 mantissa and round slightly incorrect, what is more than enough
>> 355 for normal usage.
>> 356
>> 357 config M68KFPU_EMU_ONLY
>> 358 bool "Math emulation only kernel"
>> 359 depends on M68KFPU_EMU
>> 360 help
>> 361 This option prevents any floating-point instructions from being
>> 362 compiled into the kernel, thereby the kernel doesn't save any
>> 363 floating point context anymore during task switches, so this
>> 364 kernel will only be usable on machines without a floating-point
>> 365 math coprocessor. This makes the kernel a bit faster as no tests
>> 366 needs to be executed whether a floating-point instruction in the
>> 367 kernel should be executed or not.
>> 368
>> 369 config ADVANCED
>> 370 bool "Advanced configuration options"
>> 371 depends on MMU
>> 372 help
>> 373 This gives you access to some advanced options for the CPU. The
>> 374 defaults should be fine for most users, but these options may make
>> 375 it possible for you to improve performance somewhat if you know what
>> 376 you are doing.
>> 377
>> 378 Note that the answer to this question won't directly affect the
>> 379 kernel: saying N will just cause the configurator to skip all
>> 380 the questions about these options.
>> 381
>> 382 Most users should say N to this question.
>> 383
>> 384 config RMW_INSNS
>> 385 bool "Use read-modify-write instructions"
>> 386 depends on ADVANCED
>> 387 help
>> 388 This allows to use certain instructions that work with indivisible
>> 389 read-modify-write bus cycles. While this is faster than the
>> 390 workaround of disabling interrupts, it can conflict with DMA
>> 391 ( = direct memory access) on many Amiga systems, and it is also said
>> 392 to destabilize other machines. It is very likely that this will
>> 393 cause serious problems on any Amiga or Atari Medusa if set. The only
>> 394 configuration where it should work are 68030-based Ataris, where it
>> 395 apparently improves performance. But you've been warned! Unless you
>> 396 really know what you are doing, say N. Try Y only if you're quite
>> 397 adventurous.
>> 398
>> 399 config SINGLE_MEMORY_CHUNK
>> 400 bool "Use one physical chunk of memory only" if ADVANCED && !SUN3
>> 401 depends on MMU
>> 402 default y if SUN3 || MMU_COLDFIRE
>> 403 help
>> 404 Ignore all but the first contiguous chunk of physical memory for VM
>> 405 purposes. This will save a few bytes kernel size and may speed up
>> 406 some operations.
>> 407 When this option os set to N, you may want to lower "Maximum zone
>> 408 order" to save memory that could be wasted for unused memory map.
>> 409 Say N if not sure.
>> 410
>> 411 config ARCH_DISCONTIGMEM_ENABLE
>> 412 depends on BROKEN
>> 413 def_bool MMU && !SINGLE_MEMORY_CHUNK
>> 414
>> 415 config FORCE_MAX_ZONEORDER
>> 416 int "Maximum zone order" if ADVANCED
>> 417 depends on !SINGLE_MEMORY_CHUNK
>> 418 default "11"
>> 419 help
>> 420 The kernel memory allocator divides physically contiguous memory
>> 421 blocks into "zones", where each zone is a power of two number of
>> 422 pages. This option selects the largest power of two that the kernel
>> 423 keeps in the memory allocator. If you need to allocate very large
>> 424 blocks of physically contiguous memory, then you may need to
>> 425 increase this value.
>> 426
>> 427 For systems that have holes in their physical address space this
>> 428 value also defines the minimal size of the hole that allows
>> 429 freeing unused memory map.
>> 430
>> 431 This config option is actually maximum order plus one. For example,
>> 432 a value of 11 means that the largest free memory block is 2^10 pages.
>> 433
>> 434 config 060_WRITETHROUGH
>> 435 bool "Use write-through caching for 68060 supervisor accesses"
>> 436 depends on ADVANCED && M68060
>> 437 help
>> 438 The 68060 generally uses copyback caching of recently accessed data.
>> 439 Copyback caching means that memory writes will be held in an on-chip
>> 440 cache and only written back to memory some time later. Saying Y
>> 441 here will force supervisor (kernel) accesses to use writethrough
>> 442 caching. Writethrough caching means that data is written to memory
>> 443 straight away, so that cache and memory data always agree.
>> 444 Writethrough caching is less efficient, but is needed for some
>> 445 drivers on 68060 based systems where the 68060 bus snooping signal
>> 446 is hardwired on. The 53c710 SCSI driver is known to suffer from
>> 447 this problem.
>> 448
>> 449 config M68K_L2_CACHE
>> 450 bool
>> 451 depends on MAC
459 default y 452 default y
460 bool "Support Centaur processors" if P <<
461 help <<
462 This enables detection, tunings and <<
463 <<
464 You need this enabled if you want yo <<
465 Centaur CPU. Disabling this option o <<
466 makes the kernel a tiny bit smaller. <<
467 CPU might render the kernel unbootab <<
468 <<
469 If unsure, say N. <<
470 453
471 config CPU_SUP_TRANSMETA_32 !! 454 config NODES_SHIFT
472 default y !! 455 int
473 bool "Support Transmeta processors" if !! 456 default "3"
474 depends on !64BIT !! 457 depends on DISCONTIGMEM
475 help <<
476 This enables detection, tunings and <<
477 458
478 You need this enabled if you want yo !! 459 config CPU_HAS_NO_BITFIELDS
479 Transmeta CPU. Disabling this option !! 460 bool
480 makes the kernel a tiny bit smaller. <<
481 CPU might render the kernel unbootab <<
482 461
483 If unsure, say N. !! 462 config CPU_HAS_NO_MULDIV64
>> 463 bool
484 464
485 config CPU_SUP_UMC_32 !! 465 config CPU_HAS_NO_UNALIGNED
486 default y !! 466 bool
487 bool "Support UMC processors" if PROCE !! 467
488 depends on M486SX || M486 || (EXPERT & !! 468 config CPU_HAS_ADDRESS_SPACES
>> 469 bool
>> 470
>> 471 config FPU
>> 472 bool
>> 473
>> 474 config COLDFIRE_SW_A7
>> 475 bool
>> 476
>> 477 config HAVE_CACHE_SPLIT
>> 478 bool
>> 479
>> 480 config HAVE_CACHE_CB
>> 481 bool
>> 482
>> 483 config HAVE_MBAR
>> 484 bool
>> 485
>> 486 config HAVE_IPSBAR
>> 487 bool
>> 488
>> 489 config CLOCK_FREQ
>> 490 int "Set the core clock frequency"
>> 491 default "25000000" if M5206
>> 492 default "54000000" if M5206e
>> 493 default "166666666" if M520x
>> 494 default "140000000" if M5249
>> 495 default "150000000" if M527x || M523x
>> 496 default "90000000" if M5307
>> 497 default "50000000" if M5407
>> 498 default "266000000" if M54xx
>> 499 default "66666666"
>> 500 depends on COLDFIRE
>> 501 help
>> 502 Define the CPU clock frequency in use. This is the core clock
>> 503 frequency, it may or may not be the same as the external clock
>> 504 crystal fitted to your board. Some processors have an internal
>> 505 PLL and can have their frequency programmed at run time, others
>> 506 use internal dividers. In general the kernel won't setup a PLL
>> 507 if it is fitted (there are some exceptions). This value will be
>> 508 specific to the exact CPU that you are using.
>> 509
>> 510 config OLDMASK
>> 511 bool "Old mask 5307 (1H55J) silicon"
>> 512 depends on M5307
489 help 513 help
490 This enables detection, tunings and !! 514 Build support for the older revision ColdFire 5307 silicon.
>> 515 Specifically this is the 1H55J mask revision.
491 516
492 You need this enabled if you want yo !! 517 if HAVE_CACHE_SPLIT
493 UMC CPU. Disabling this option on ot !! 518 choice
494 makes the kernel a tiny bit smaller. !! 519 prompt "Split Cache Configuration"
495 CPU might render the kernel unbootab !! 520 default CACHE_I
496 521
497 If unsure, say N. !! 522 config CACHE_I
>> 523 bool "Instruction"
>> 524 help
>> 525 Use all of the ColdFire CPU cache memory as an instruction cache.
498 526
499 config CPU_SUP_ZHAOXIN !! 527 config CACHE_D
500 default y !! 528 bool "Data"
501 bool "Support Zhaoxin processors" if P <<
502 help 529 help
503 This enables detection, tunings and !! 530 Use all of the ColdFire CPU cache memory as a data cache.
504 531
505 You need this enabled if you want yo !! 532 config CACHE_BOTH
506 Zhaoxin CPU. Disabling this option o !! 533 bool "Both"
507 makes the kernel a tiny bit smaller. !! 534 help
508 CPU might render the kernel unbootab !! 535 Split the ColdFire CPU cache, and use half as an instruction cache
>> 536 and half as a data cache.
>> 537 endchoice
>> 538 endif
509 539
510 If unsure, say N. !! 540 if HAVE_CACHE_CB
>> 541 choice
>> 542 prompt "Data cache mode"
>> 543 default CACHE_WRITETHRU
511 544
512 config CPU_SUP_VORTEX_32 !! 545 config CACHE_WRITETHRU
513 default y !! 546 bool "Write-through"
514 bool "Support Vortex processors" if PR <<
515 depends on X86_32 <<
516 help 547 help
517 This enables detection, tunings and !! 548 The ColdFire CPU cache is set into Write-through mode.
518 549
519 You need this enabled if you want yo !! 550 config CACHE_COPYBACK
520 Vortex CPU. Disabling this option on !! 551 bool "Copy-back"
521 makes the kernel a tiny bit smaller. !! 552 help
>> 553 The ColdFire CPU cache is set into Copy-back mode.
>> 554 endchoice
>> 555 endif
522 556
523 If unsure, say N. <<
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