1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 # Put here option for CPU selection and depend !! 2 comment "Processor Type"
>> 3
3 choice 4 choice
4 prompt "Processor family" !! 5 prompt "CPU family support"
5 default M686 if X86_32 !! 6 default M68KCLASSIC if MMU
6 default GENERIC_CPU if X86_64 !! 7 default COLDFIRE if !MMU
7 help !! 8 help
8 This is the processor type of your C !! 9 The Freescale (was Motorola) M68K family of processors implements
9 used for optimizing purposes. In ord !! 10 the full 68000 processor instruction set.
10 that can run on all supported x86 CP !! 11 The Freescale ColdFire family of processors is a modern derivative
11 optimally fast), you can specify "48 !! 12 of the 68000 processor family. They are mainly targeted at embedded
12 !! 13 applications, and are all System-On-Chip (SOC) devices, as opposed
13 Note that the 386 is no longer suppo !! 14 to stand alone CPUs. They implement a subset of the original 68000
14 AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, !! 15 processor instruction set.
15 UMC 486SX-S and the NexGen Nx586. !! 16 If you anticipate running this kernel on a computer with a classic
16 !! 17 MC68xxx processor, select M68KCLASSIC.
17 The kernel will not necessarily run !! 18 If you anticipate running this kernel on a computer with a ColdFire
18 the one you have chosen, e.g. a Pent !! 19 processor, select COLDFIRE.
19 a PPro, but not necessarily on a i48 !! 20
20 !! 21 config M68KCLASSIC
21 Here are the settings recommended fo !! 22 bool "Classic M68K CPU family support"
22 - "486" for the AMD/Cyrix/IBM/Intel !! 23 select HAVE_ARCH_PFN_VALID
23 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5 !! 24
24 - "586" for generic Pentium CPUs lac !! 25 config COLDFIRE
25 (time stamp counter) register. !! 26 bool "Coldfire CPU family support"
26 - "Pentium-Classic" for the Intel Pe !! 27 select ARCH_HAVE_CUSTOM_GPIO_H
27 - "Pentium-MMX" for the Intel Pentiu !! 28 select CPU_HAS_NO_BITFIELDS
28 - "Pentium-Pro" for the Intel Pentiu !! 29 select CPU_HAS_NO_CAS
29 - "Pentium-II" for the Intel Pentium !! 30 select CPU_HAS_NO_MULDIV64
30 - "Pentium-III" for the Intel Pentiu !! 31 select GENERIC_CSUM
31 - "Pentium-4" for the Intel Pentium !! 32 select GPIOLIB
32 - "K6" for the AMD K6, K6-II and K6- !! 33 select HAVE_LEGACY_CLK
33 - "Athlon" for the AMD K7 family (At <<
34 - "Opteron/Athlon64/Hammer/K8" for a <<
35 - "Crusoe" for the Transmeta Crusoe <<
36 - "Efficeon" for the Transmeta Effic <<
37 - "Winchip-C6" for original IDT Winc <<
38 - "Winchip-2" for IDT Winchips with <<
39 - "AMD Elan" for the 32-bit AMD Elan <<
40 - "GeodeGX1" for Geode GX1 (Cyrix Me <<
41 - "Geode GX/LX" For AMD Geode GX and <<
42 - "CyrixIII/VIA C3" for VIA Cyrix II <<
43 - "VIA C3-2" for VIA C3-2 "Nehemiah" <<
44 - "VIA C7" for VIA C7. <<
45 - "Intel P4" for the Pentium 4/Netbu <<
46 - "Core 2/newer Xeon" for all core2 <<
47 - "Intel Atom" for the Atom-microarc <<
48 - "Generic-x86-64" for a kernel whic <<
49 <<
50 See each option's help text for addi <<
51 what to do, choose "486". <<
52 <<
53 config M486SX <<
54 bool "486SX" <<
55 depends on X86_32 <<
56 help <<
57 Select this for an 486-class CPU wit <<
58 AMD/Cyrix/IBM/Intel SL/SLC/SLC2/SLC3 <<
59 <<
60 config M486 <<
61 bool "486DX" <<
62 depends on X86_32 <<
63 help <<
64 Select this for an 486-class CPU suc <<
65 486DX/DX2/DX4 and UMC U5D. <<
66 <<
67 config M586 <<
68 bool "586/K5/5x86/6x86/6x86MX" <<
69 depends on X86_32 <<
70 help <<
71 Select this for an 586 or 686 series <<
72 the Cyrix 5x86, 6x86 and 6x86MX. Th <<
73 assume the RDTSC (Read Time Stamp Co <<
74 <<
75 config M586TSC <<
76 bool "Pentium-Classic" <<
77 depends on X86_32 <<
78 help <<
79 Select this for a Pentium Classic pr <<
80 Time Stamp Counter) instruction for <<
81 <<
82 config M586MMX <<
83 bool "Pentium-MMX" <<
84 depends on X86_32 <<
85 help <<
86 Select this for a Pentium with the M <<
87 extended instructions. <<
88 <<
89 config M686 <<
90 bool "Pentium-Pro" <<
91 depends on X86_32 <<
92 help <<
93 Select this for Intel Pentium Pro ch <<
94 Pentium Pro extended instructions, a <<
95 against the f00f bug found in earlie <<
96 <<
97 config MPENTIUMII <<
98 bool "Pentium-II/Celeron(pre-Coppermin <<
99 depends on X86_32 <<
100 help <<
101 Select this for Intel chips based on <<
102 pre-Coppermine Celeron core. This o <<
103 copy optimization, compiles the kern <<
104 tailored for the chip, and applies a <<
105 optimizations. <<
106 <<
107 config MPENTIUMIII <<
108 bool "Pentium-III/Celeron(Coppermine)/ <<
109 depends on X86_32 <<
110 help <<
111 Select this for Intel chips based on <<
112 Celeron-Coppermine core. This optio <<
113 extended prefetch instructions in ad <<
114 extensions. <<
115 <<
116 config MPENTIUMM <<
117 bool "Pentium M" <<
118 depends on X86_32 <<
119 help <<
120 Select this for Intel Pentium M (not <<
121 notebook chips. <<
122 <<
123 config MPENTIUM4 <<
124 bool "Pentium-4/Celeron(P4-based)/Pent <<
125 depends on X86_32 <<
126 help <<
127 Select this for Intel Pentium 4 chip <<
128 Pentium 4, Pentium D, P4-based Celer <<
129 Pentium-4 M (not Pentium M) chips. <<
130 flags optimized for the chip, uses t <<
131 applies any applicable optimizations <<
132 <<
133 CPUIDs: F[0-6][1-A] (in /proc/cpuinf <<
134 <<
135 Select this for: <<
136 Pentiums (Pentium 4, Pentium D, Ce <<
137 -Willamette <<
138 -Northwood <<
139 -Mobile Pentium 4 <<
140 -Mobile Pentium 4 M <<
141 -Extreme Edition (Gallatin) <<
142 -Prescott <<
143 -Prescott 2M <<
144 -Cedar Mill <<
145 -Presler <<
146 -Smithfiled <<
147 Xeons (Intel Xeon, Xeon MP, Xeon L <<
148 -Foster <<
149 -Prestonia <<
150 -Gallatin <<
151 -Nocona <<
152 -Irwindale <<
153 -Cranford <<
154 -Potomac <<
155 -Paxville <<
156 -Dempsey <<
157 <<
158 <<
159 config MK6 <<
160 bool "K6/K6-II/K6-III" <<
161 depends on X86_32 <<
162 help <<
163 Select this for an AMD K6-family pro <<
164 some extended instructions, and pass <<
165 flags to GCC. <<
166 <<
167 config MK7 <<
168 bool "Athlon/Duron/K7" <<
169 depends on X86_32 <<
170 help <<
171 Select this for an AMD Athlon K7-fam <<
172 some extended instructions, and pass <<
173 flags to GCC. <<
174 <<
175 config MK8 <<
176 bool "Opteron/Athlon64/Hammer/K8" <<
177 help <<
178 Select this for an AMD Opteron or At <<
179 Enables use of some extended instruc <<
180 optimization flags to GCC. <<
181 <<
182 config MCRUSOE <<
183 bool "Crusoe" <<
184 depends on X86_32 <<
185 help <<
186 Select this for a Transmeta Crusoe p <<
187 like a 586 with TSC, and sets some G <<
188 Pentium Pro with no alignment requir <<
189 <<
190 config MEFFICEON <<
191 bool "Efficeon" <<
192 depends on X86_32 <<
193 help <<
194 Select this for a Transmeta Efficeon <<
195 <<
196 config MWINCHIPC6 <<
197 bool "Winchip-C6" <<
198 depends on X86_32 <<
199 help <<
200 Select this for an IDT Winchip C6 ch <<
201 treat this chip as a 586TSC with som <<
202 and alignment requirements. <<
203 <<
204 config MWINCHIP3D <<
205 bool "Winchip-2/Winchip-2A/Winchip-3" <<
206 depends on X86_32 <<
207 help <<
208 Select this for an IDT Winchip-2, 2A <<
209 treat this chip as a 586TSC with som <<
210 and alignment requirements. Also en <<
211 stores for this CPU, which can incre <<
212 operations. <<
213 <<
214 config MELAN <<
215 bool "AMD Elan" <<
216 depends on X86_32 <<
217 help <<
218 Select this for an AMD Elan processo <<
219 <<
220 Do not use this option for K6/Athlon <<
221 <<
222 config MGEODEGX1 <<
223 bool "GeodeGX1" <<
224 depends on X86_32 <<
225 help <<
226 Select this for a Geode GX1 (Cyrix M <<
227 <<
228 config MGEODE_LX <<
229 bool "Geode GX/LX" <<
230 depends on X86_32 <<
231 help <<
232 Select this for AMD Geode GX and LX <<
233 <<
234 config MCYRIXIII <<
235 bool "CyrixIII/VIA-C3" <<
236 depends on X86_32 <<
237 help <<
238 Select this for a Cyrix III or C3 ch <<
239 treat this chip as a generic 586. Wh <<
240 it lacks the cmov extension which gc <<
241 generating 686 code. <<
242 Note that Nehemiah (Model 9) and abo <<
243 kernel due to them lacking the 3DNow <<
244 incarnations of the CPU. <<
245 <<
246 config MVIAC3_2 <<
247 bool "VIA C3-2 (Nehemiah)" <<
248 depends on X86_32 <<
249 help <<
250 Select this for a VIA C3 "Nehemiah". <<
251 of SSE and tells gcc to treat the CP <<
252 Note, this kernel will not boot on o <<
253 <<
254 config MVIAC7 <<
255 bool "VIA C7" <<
256 depends on X86_32 <<
257 help <<
258 Select this for a VIA C7. Selecting <<
259 shift and tells gcc to treat the CPU <<
260 <<
261 config MPSC <<
262 bool "Intel P4 / older Netburst based <<
263 depends on X86_64 <<
264 help <<
265 Optimize for Intel Pentium 4, Pentiu <<
266 Xeon CPUs with Intel 64bit which is <<
267 Note that the latest Xeons (Xeon 51x <<
268 Netburst core and shouldn't use this <<
269 using the cpu family field <<
270 in /proc/cpuinfo. Family 15 is an ol <<
271 <<
272 config MCORE2 <<
273 bool "Core 2/newer Xeon" <<
274 help <<
275 <<
276 Select this for Intel Core 2 and new <<
277 53xx) CPUs. You can distinguish newe <<
278 family in /proc/cpuinfo. Newer ones <<
279 (not a typo) <<
280 <<
281 config MATOM <<
282 bool "Intel Atom" <<
283 help <<
284 <<
285 Select this for the Intel Atom platf <<
286 in-order pipelining architecture and <<
287 accordingly optimized code. Use a re <<
288 support in order to fully benefit fr <<
289 <<
290 config GENERIC_CPU <<
291 bool "Generic-x86-64" <<
292 depends on X86_64 <<
293 help <<
294 Generic x86-64 CPU. <<
295 Run equally well on all x86-64 CPUs. <<
296 34
297 endchoice 35 endchoice
298 36
299 config X86_GENERIC !! 37 if M68KCLASSIC
300 bool "Generic x86 support" <<
301 depends on X86_32 <<
302 help <<
303 Instead of just including optimizati <<
304 x86 variant (e.g. PII, Crusoe or Ath <<
305 generic optimizations as well. This <<
306 perform better on x86 CPUs other tha <<
307 <<
308 This is really intended for distribu <<
309 generic optimizations. <<
310 <<
311 # <<
312 # Define implied options from the CPU selectio <<
313 config X86_INTERNODE_CACHE_SHIFT <<
314 int <<
315 default "12" if X86_VSMP <<
316 default X86_L1_CACHE_SHIFT <<
317 <<
318 config X86_L1_CACHE_SHIFT <<
319 int <<
320 default "7" if MPENTIUM4 || MPSC <<
321 default "6" if MK7 || MK8 || MPENTIUMM <<
322 default "4" if MELAN || M486SX || M486 <<
323 default "5" if MWINCHIP3D || MWINCHIPC <<
324 <<
325 config X86_F00F_BUG <<
326 def_bool y <<
327 depends on M586MMX || M586TSC || M586 <<
328 <<
329 config X86_INVD_BUG <<
330 def_bool y <<
331 depends on M486SX || M486 <<
332 <<
333 config X86_ALIGNMENT_16 <<
334 def_bool y <<
335 depends on MWINCHIP3D || MWINCHIPC6 || <<
336 <<
337 config X86_INTEL_USERCOPY <<
338 def_bool y <<
339 depends on MPENTIUM4 || MPENTIUMM || M <<
340 <<
341 config X86_USE_PPRO_CHECKSUM <<
342 def_bool y <<
343 depends on MWINCHIP3D || MWINCHIPC6 || <<
344 <<
345 # <<
346 # P6_NOPs are a relatively minor optimization <<
347 # 6 processor, except that it is broken on cer <<
348 # Furthermore, AMD chips prefer a totally diff <<
349 # (which work on all CPUs). In addition, it l <<
350 # does not understand them. <<
351 # <<
352 # As a result, disallow these if we're not com <<
353 # NOPs do work on all x86-64 capable chips); t <<
354 # the right-hand clause are the cores that ben <<
355 # <<
356 config X86_P6_NOP <<
357 def_bool y <<
358 depends on X86_64 <<
359 depends on (MCORE2 || MPENTIUM4 || MPS <<
360 <<
361 config X86_TSC <<
362 def_bool y <<
363 depends on (MWINCHIP3D || MCRUSOE || M <<
364 <<
365 config X86_HAVE_PAE <<
366 def_bool y <<
367 depends on MCRUSOE || MEFFICEON || MCY <<
368 <<
369 config X86_CMPXCHG64 <<
370 def_bool y <<
371 depends on X86_HAVE_PAE || M586TSC || <<
372 <<
373 # this should be set for all -march=.. options <<
374 # generates cmov. <<
375 config X86_CMOV <<
376 def_bool y <<
377 depends on (MK8 || MK7 || MCORE2 || MP <<
378 <<
379 config X86_MINIMUM_CPU_FAMILY <<
380 int <<
381 default "64" if X86_64 <<
382 default "6" if X86_32 && (MPENTIUM4 || <<
383 default "5" if X86_32 && X86_CMPXCHG64 <<
384 default "4" <<
385 <<
386 config X86_DEBUGCTLMSR <<
387 def_bool y <<
388 depends on !(MK6 || MWINCHIPC6 || MWIN <<
389 <<
390 config IA32_FEAT_CTL <<
391 def_bool y <<
392 depends on CPU_SUP_INTEL || CPU_SUP_CE <<
393 <<
394 config X86_VMX_FEATURE_NAMES <<
395 def_bool y <<
396 depends on IA32_FEAT_CTL <<
397 <<
398 menuconfig PROCESSOR_SELECT <<
399 bool "Supported processor vendors" if <<
400 help <<
401 This lets you choose what x86 vendor <<
402 will include. <<
403 38
404 config CPU_SUP_INTEL !! 39 config M68000
405 default y !! 40 bool
406 bool "Support Intel processors" if PRO !! 41 depends on !MMU
>> 42 select CPU_HAS_NO_BITFIELDS
>> 43 select CPU_HAS_NO_CAS
>> 44 select CPU_HAS_NO_MULDIV64
>> 45 select CPU_HAS_NO_UNALIGNED
>> 46 select GENERIC_CSUM
>> 47 select CPU_NO_EFFICIENT_FFS
>> 48 select HAVE_ARCH_HASH
>> 49 help
>> 50 The Freescale (was Motorola) 68000 CPU is the first generation of
>> 51 the well known M68K family of processors. The CPU core as well as
>> 52 being available as a stand alone CPU was also used in many
>> 53 System-On-Chip devices (eg 68328, 68302, etc). It does not contain
>> 54 a paging MMU.
>> 55
>> 56 config MCPU32
>> 57 bool
>> 58 select CPU_HAS_NO_BITFIELDS
>> 59 select CPU_HAS_NO_CAS
>> 60 select CPU_HAS_NO_UNALIGNED
>> 61 select CPU_NO_EFFICIENT_FFS
>> 62 help
>> 63 The Freescale (was then Motorola) CPU32 is a CPU core that is
>> 64 based on the 68020 processor. For the most part it is used in
>> 65 System-On-Chip parts, and does not contain a paging MMU.
>> 66
>> 67 config M68020
>> 68 bool "68020 support"
>> 69 depends on MMU
>> 70 select FPU
>> 71 select CPU_HAS_ADDRESS_SPACES
>> 72 help
>> 73 If you anticipate running this kernel on a computer with a MC68020
>> 74 processor, say Y. Otherwise, say N. Note that the 68020 requires a
>> 75 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the
>> 76 Sun 3, which provides its own version.
>> 77
>> 78 config M68030
>> 79 bool "68030 support"
>> 80 depends on MMU && !MMU_SUN3
>> 81 select FPU
>> 82 select CPU_HAS_ADDRESS_SPACES
>> 83 help
>> 84 If you anticipate running this kernel on a computer with a MC68030
>> 85 processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
>> 86 work, as it does not include an MMU (Memory Management Unit).
>> 87
>> 88 config M68040
>> 89 bool "68040 support"
>> 90 depends on MMU && !MMU_SUN3
>> 91 select FPU
>> 92 select CPU_HAS_ADDRESS_SPACES
>> 93 help
>> 94 If you anticipate running this kernel on a computer with a MC68LC040
>> 95 or MC68040 processor, say Y. Otherwise, say N. Note that an
>> 96 MC68EC040 will not work, as it does not include an MMU (Memory
>> 97 Management Unit).
>> 98
>> 99 config M68060
>> 100 bool "68060 support"
>> 101 depends on MMU && !MMU_SUN3
>> 102 select FPU
>> 103 select CPU_HAS_ADDRESS_SPACES
>> 104 help
>> 105 If you anticipate running this kernel on a computer with a MC68060
>> 106 processor, say Y. Otherwise, say N.
>> 107
>> 108 config M68328
>> 109 bool
>> 110 depends on !MMU
>> 111 select LEGACY_TIMER_TICK
>> 112 select M68000
>> 113 help
>> 114 Motorola 68328 processor support.
>> 115
>> 116 config M68EZ328
>> 117 bool
>> 118 depends on !MMU
>> 119 select LEGACY_TIMER_TICK
>> 120 select M68000
>> 121 help
>> 122 Motorola 68EX328 processor support.
>> 123
>> 124 config M68VZ328
>> 125 bool
>> 126 depends on !MMU
>> 127 select LEGACY_TIMER_TICK
>> 128 select M68000
407 help 129 help
408 This enables detection, tunings and !! 130 Motorola 68VZ328 processor support.
409 131
410 You need this enabled if you want yo !! 132 endif # M68KCLASSIC
411 Intel CPU. Disabling this option on <<
412 makes the kernel a tiny bit smaller. <<
413 CPU might render the kernel unbootab <<
414 133
415 If unsure, say N. !! 134 if COLDFIRE
416 135
417 config CPU_SUP_CYRIX_32 !! 136 choice
418 default y !! 137 prompt "ColdFire SoC type"
419 bool "Support Cyrix processors" if PRO !! 138 default M520x
420 depends on M486SX || M486 || M586 || M <<
421 help 139 help
422 This enables detection, tunings and !! 140 Select the type of ColdFire System-on-Chip (SoC) that you want
423 !! 141 to build for.
424 You need this enabled if you want yo <<
425 Cyrix CPU. Disabling this option on <<
426 makes the kernel a tiny bit smaller. <<
427 CPU might render the kernel unbootab <<
428 <<
429 If unsure, say N. <<
430 142
431 config CPU_SUP_AMD !! 143 config M5206
432 default y !! 144 bool "MCF5206"
433 bool "Support AMD processors" if PROCE !! 145 depends on !MMU
>> 146 select COLDFIRE_SW_A7
>> 147 select COLDFIRE_TIMERS
>> 148 select HAVE_MBAR
>> 149 select CPU_NO_EFFICIENT_FFS
>> 150 help
>> 151 Motorola ColdFire 5206 processor support.
>> 152
>> 153 config M5206e
>> 154 bool "MCF5206e"
>> 155 depends on !MMU
>> 156 select COLDFIRE_SW_A7
>> 157 select COLDFIRE_TIMERS
>> 158 select HAVE_MBAR
>> 159 select CPU_NO_EFFICIENT_FFS
>> 160 help
>> 161 Motorola ColdFire 5206e processor support.
>> 162
>> 163 config M520x
>> 164 bool "MCF520x"
>> 165 depends on !MMU
>> 166 select COLDFIRE_PIT_TIMER
>> 167 select HAVE_CACHE_SPLIT
>> 168 help
>> 169 Freescale Coldfire 5207/5208 processor support.
>> 170
>> 171 config M523x
>> 172 bool "MCF523x"
>> 173 depends on !MMU
>> 174 select COLDFIRE_PIT_TIMER
>> 175 select HAVE_CACHE_SPLIT
>> 176 select HAVE_IPSBAR
>> 177 help
>> 178 Freescale Coldfire 5230/1/2/4/5 processor support
>> 179
>> 180 config M5249
>> 181 bool "MCF5249"
>> 182 depends on !MMU
>> 183 select COLDFIRE_SW_A7
>> 184 select COLDFIRE_TIMERS
>> 185 select HAVE_MBAR
>> 186 select CPU_NO_EFFICIENT_FFS
>> 187 help
>> 188 Motorola ColdFire 5249 processor support.
>> 189
>> 190 config M525x
>> 191 bool "MCF525x"
>> 192 depends on !MMU
>> 193 select COLDFIRE_SW_A7
>> 194 select COLDFIRE_TIMERS
>> 195 select HAVE_MBAR
>> 196 select CPU_NO_EFFICIENT_FFS
>> 197 help
>> 198 Freescale (Motorola) Coldfire 5251/5253 processor support.
>> 199
>> 200 config M5271
>> 201 bool "MCF5271"
>> 202 depends on !MMU
>> 203 select COLDFIRE_PIT_TIMER
>> 204 select M527x
>> 205 select HAVE_CACHE_SPLIT
>> 206 select HAVE_IPSBAR
>> 207 help
>> 208 Freescale (Motorola) ColdFire 5270/5271 processor support.
>> 209
>> 210 config M5272
>> 211 bool "MCF5272"
>> 212 depends on !MMU
>> 213 select COLDFIRE_SW_A7
>> 214 select COLDFIRE_TIMERS
>> 215 select HAVE_MBAR
>> 216 select CPU_NO_EFFICIENT_FFS
>> 217 help
>> 218 Motorola ColdFire 5272 processor support.
>> 219
>> 220 config M5275
>> 221 bool "MCF5275"
>> 222 depends on !MMU
>> 223 select COLDFIRE_PIT_TIMER
>> 224 select M527x
>> 225 select HAVE_CACHE_SPLIT
>> 226 select HAVE_IPSBAR
>> 227 help
>> 228 Freescale (Motorola) ColdFire 5274/5275 processor support.
>> 229
>> 230 config M528x
>> 231 bool "MCF528x"
>> 232 depends on !MMU
>> 233 select COLDFIRE_PIT_TIMER
>> 234 select HAVE_CACHE_SPLIT
>> 235 select HAVE_IPSBAR
>> 236 help
>> 237 Motorola ColdFire 5280/5282 processor support.
>> 238
>> 239 config M5307
>> 240 bool "MCF5307"
>> 241 depends on !MMU
>> 242 select COLDFIRE_TIMERS
>> 243 select COLDFIRE_SW_A7
>> 244 select HAVE_CACHE_CB
>> 245 select HAVE_MBAR
>> 246 select CPU_NO_EFFICIENT_FFS
>> 247 help
>> 248 Motorola ColdFire 5307 processor support.
>> 249
>> 250 config M532x
>> 251 bool "MCF532x"
>> 252 depends on !MMU
>> 253 select COLDFIRE_TIMERS
>> 254 select M53xx
>> 255 select HAVE_CACHE_CB
>> 256 help
>> 257 Freescale (Motorola) ColdFire 532x processor support.
>> 258
>> 259 config M537x
>> 260 bool "MCF537x"
>> 261 depends on !MMU
>> 262 select COLDFIRE_TIMERS
>> 263 select M53xx
>> 264 select HAVE_CACHE_CB
>> 265 help
>> 266 Freescale ColdFire 537x processor support.
>> 267
>> 268 config M5407
>> 269 bool "MCF5407"
>> 270 depends on !MMU
>> 271 select COLDFIRE_SW_A7
>> 272 select COLDFIRE_TIMERS
>> 273 select HAVE_CACHE_CB
>> 274 select HAVE_MBAR
>> 275 select CPU_NO_EFFICIENT_FFS
>> 276 help
>> 277 Motorola ColdFire 5407 processor support.
>> 278
>> 279 config M547x
>> 280 bool "MCF547x"
>> 281 select M54xx
>> 282 select COLDFIRE_SLTIMERS
>> 283 select MMU_COLDFIRE if MMU
>> 284 select FPU if MMU
>> 285 select HAVE_CACHE_CB
>> 286 select HAVE_MBAR
>> 287 select CPU_NO_EFFICIENT_FFS
>> 288 help
>> 289 Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
>> 290
>> 291 config M548x
>> 292 bool "MCF548x"
>> 293 select COLDFIRE_SLTIMERS
>> 294 select MMU_COLDFIRE if MMU
>> 295 select FPU if MMU
>> 296 select M54xx
>> 297 select HAVE_CACHE_CB
>> 298 select HAVE_MBAR
>> 299 select CPU_NO_EFFICIENT_FFS
>> 300 help
>> 301 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
>> 302
>> 303 config M5441x
>> 304 bool "MCF5441x"
>> 305 select COLDFIRE_PIT_TIMER
>> 306 select MMU_COLDFIRE if MMU
>> 307 select HAVE_CACHE_CB
434 help 308 help
435 This enables detection, tunings and !! 309 Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
436 <<
437 You need this enabled if you want yo <<
438 AMD CPU. Disabling this option on ot <<
439 makes the kernel a tiny bit smaller. <<
440 CPU might render the kernel unbootab <<
441 310
442 If unsure, say N. !! 311 endchoice
443 <<
444 config CPU_SUP_HYGON <<
445 default y <<
446 bool "Support Hygon processors" if PRO <<
447 select CPU_SUP_AMD <<
448 help <<
449 This enables detection, tunings and <<
450 312
451 You need this enabled if you want yo !! 313 config M527x
452 Hygon CPU. Disabling this option on !! 314 bool
453 makes the kernel a tiny bit smaller. <<
454 CPU might render the kernel unbootab <<
455 315
456 If unsure, say N. !! 316 config M53xx
>> 317 bool
457 318
458 config CPU_SUP_CENTAUR !! 319 config M54xx
>> 320 select HAVE_PCI
>> 321 bool
>> 322
>> 323 config COLDFIRE_PIT_TIMER
>> 324 bool
>> 325
>> 326 config COLDFIRE_TIMERS
>> 327 bool
>> 328 select LEGACY_TIMER_TICK
>> 329
>> 330 config COLDFIRE_SLTIMERS
>> 331 bool
>> 332 select LEGACY_TIMER_TICK
>> 333
>> 334 endif # COLDFIRE
>> 335
>> 336
>> 337 comment "Processor Specific Options"
>> 338
>> 339 config M68KFPU_EMU
>> 340 bool "Math emulation support"
>> 341 depends on MMU
>> 342 help
>> 343 At some point in the future, this will cause floating-point math
>> 344 instructions to be emulated by the kernel on machines that lack a
>> 345 floating-point math coprocessor. Thrill-seekers and chronically
>> 346 sleep-deprived psychotic hacker types can say Y now, everyone else
>> 347 should probably wait a while.
>> 348
>> 349 config M68KFPU_EMU_EXTRAPREC
>> 350 bool "Math emulation extra precision"
>> 351 depends on M68KFPU_EMU
>> 352 help
>> 353 The fpu uses normally a few bit more during calculations for
>> 354 correct rounding, the emulator can (often) do the same but this
>> 355 extra calculation can cost quite some time, so you can disable
>> 356 it here. The emulator will then "only" calculate with a 64 bit
>> 357 mantissa and round slightly incorrect, what is more than enough
>> 358 for normal usage.
>> 359
>> 360 config M68KFPU_EMU_ONLY
>> 361 bool "Math emulation only kernel"
>> 362 depends on M68KFPU_EMU
>> 363 help
>> 364 This option prevents any floating-point instructions from being
>> 365 compiled into the kernel, thereby the kernel doesn't save any
>> 366 floating point context anymore during task switches, so this
>> 367 kernel will only be usable on machines without a floating-point
>> 368 math coprocessor. This makes the kernel a bit faster as no tests
>> 369 needs to be executed whether a floating-point instruction in the
>> 370 kernel should be executed or not.
>> 371
>> 372 config ADVANCED
>> 373 bool "Advanced configuration options"
>> 374 depends on MMU
>> 375 help
>> 376 This gives you access to some advanced options for the CPU. The
>> 377 defaults should be fine for most users, but these options may make
>> 378 it possible for you to improve performance somewhat if you know what
>> 379 you are doing.
>> 380
>> 381 Note that the answer to this question won't directly affect the
>> 382 kernel: saying N will just cause the configurator to skip all
>> 383 the questions about these options.
>> 384
>> 385 Most users should say N to this question.
>> 386
>> 387 config RMW_INSNS
>> 388 bool "Use read-modify-write instructions"
>> 389 depends on ADVANCED && !CPU_HAS_NO_CAS
>> 390 help
>> 391 This allows to use certain instructions that work with indivisible
>> 392 read-modify-write bus cycles. While this is faster than the
>> 393 workaround of disabling interrupts, it can conflict with DMA
>> 394 ( = direct memory access) on many Amiga systems, and it is also said
>> 395 to destabilize other machines. It is very likely that this will
>> 396 cause serious problems on any Amiga or Atari Medusa if set. The only
>> 397 configuration where it should work are 68030-based Ataris, where it
>> 398 apparently improves performance. But you've been warned! Unless you
>> 399 really know what you are doing, say N. Try Y only if you're quite
>> 400 adventurous.
>> 401
>> 402 config SINGLE_MEMORY_CHUNK
>> 403 bool "Use one physical chunk of memory only" if ADVANCED && !SUN3
>> 404 depends on MMU
>> 405 default y if SUN3 || MMU_COLDFIRE
>> 406 help
>> 407 Ignore all but the first contiguous chunk of physical memory for VM
>> 408 purposes. This will save a few bytes kernel size and may speed up
>> 409 some operations.
>> 410 When this option os set to N, you may want to lower "Maximum zone
>> 411 order" to save memory that could be wasted for unused memory map.
>> 412 Say N if not sure.
>> 413
>> 414 config ARCH_DISCONTIGMEM_ENABLE
>> 415 depends on BROKEN
>> 416 def_bool MMU && !SINGLE_MEMORY_CHUNK
>> 417
>> 418 config FORCE_MAX_ZONEORDER
>> 419 int "Maximum zone order" if ADVANCED
>> 420 depends on !SINGLE_MEMORY_CHUNK
>> 421 default "11"
>> 422 help
>> 423 The kernel memory allocator divides physically contiguous memory
>> 424 blocks into "zones", where each zone is a power of two number of
>> 425 pages. This option selects the largest power of two that the kernel
>> 426 keeps in the memory allocator. If you need to allocate very large
>> 427 blocks of physically contiguous memory, then you may need to
>> 428 increase this value.
>> 429
>> 430 For systems that have holes in their physical address space this
>> 431 value also defines the minimal size of the hole that allows
>> 432 freeing unused memory map.
>> 433
>> 434 This config option is actually maximum order plus one. For example,
>> 435 a value of 11 means that the largest free memory block is 2^10 pages.
>> 436
>> 437 config 060_WRITETHROUGH
>> 438 bool "Use write-through caching for 68060 supervisor accesses"
>> 439 depends on ADVANCED && M68060
>> 440 help
>> 441 The 68060 generally uses copyback caching of recently accessed data.
>> 442 Copyback caching means that memory writes will be held in an on-chip
>> 443 cache and only written back to memory some time later. Saying Y
>> 444 here will force supervisor (kernel) accesses to use writethrough
>> 445 caching. Writethrough caching means that data is written to memory
>> 446 straight away, so that cache and memory data always agree.
>> 447 Writethrough caching is less efficient, but is needed for some
>> 448 drivers on 68060 based systems where the 68060 bus snooping signal
>> 449 is hardwired on. The 53c710 SCSI driver is known to suffer from
>> 450 this problem.
>> 451
>> 452 config M68K_L2_CACHE
>> 453 bool
>> 454 depends on MAC
459 default y 455 default y
460 bool "Support Centaur processors" if P <<
461 help <<
462 This enables detection, tunings and <<
463 <<
464 You need this enabled if you want yo <<
465 Centaur CPU. Disabling this option o <<
466 makes the kernel a tiny bit smaller. <<
467 CPU might render the kernel unbootab <<
468 <<
469 If unsure, say N. <<
470 456
471 config CPU_SUP_TRANSMETA_32 !! 457 config NODES_SHIFT
472 default y !! 458 int
473 bool "Support Transmeta processors" if !! 459 default "3"
474 depends on !64BIT !! 460 depends on DISCONTIGMEM
475 help <<
476 This enables detection, tunings and <<
477 461
478 You need this enabled if you want yo !! 462 config CPU_HAS_NO_BITFIELDS
479 Transmeta CPU. Disabling this option !! 463 bool
480 makes the kernel a tiny bit smaller. <<
481 CPU might render the kernel unbootab <<
482 464
483 If unsure, say N. !! 465 config CPU_HAS_NO_CAS
>> 466 bool
484 467
485 config CPU_SUP_UMC_32 !! 468 config CPU_HAS_NO_MULDIV64
486 default y !! 469 bool
487 bool "Support UMC processors" if PROCE !! 470
488 depends on M486SX || M486 || (EXPERT & !! 471 config CPU_HAS_NO_UNALIGNED
>> 472 bool
>> 473
>> 474 config CPU_HAS_ADDRESS_SPACES
>> 475 bool
>> 476
>> 477 config FPU
>> 478 bool
>> 479
>> 480 config COLDFIRE_SW_A7
>> 481 bool
>> 482
>> 483 config HAVE_CACHE_SPLIT
>> 484 bool
>> 485
>> 486 config HAVE_CACHE_CB
>> 487 bool
>> 488
>> 489 config HAVE_MBAR
>> 490 bool
>> 491
>> 492 config HAVE_IPSBAR
>> 493 bool
>> 494
>> 495 config CLOCK_FREQ
>> 496 int "Set the core clock frequency"
>> 497 default "25000000" if M5206
>> 498 default "54000000" if M5206e
>> 499 default "166666666" if M520x
>> 500 default "140000000" if M5249
>> 501 default "150000000" if M527x || M523x
>> 502 default "90000000" if M5307
>> 503 default "50000000" if M5407
>> 504 default "266000000" if M54xx
>> 505 default "66666666"
>> 506 depends on COLDFIRE
>> 507 help
>> 508 Define the CPU clock frequency in use. This is the core clock
>> 509 frequency, it may or may not be the same as the external clock
>> 510 crystal fitted to your board. Some processors have an internal
>> 511 PLL and can have their frequency programmed at run time, others
>> 512 use internal dividers. In general the kernel won't setup a PLL
>> 513 if it is fitted (there are some exceptions). This value will be
>> 514 specific to the exact CPU that you are using.
>> 515
>> 516 config OLDMASK
>> 517 bool "Old mask 5307 (1H55J) silicon"
>> 518 depends on M5307
489 help 519 help
490 This enables detection, tunings and !! 520 Build support for the older revision ColdFire 5307 silicon.
>> 521 Specifically this is the 1H55J mask revision.
491 522
492 You need this enabled if you want yo !! 523 if HAVE_CACHE_SPLIT
493 UMC CPU. Disabling this option on ot !! 524 choice
494 makes the kernel a tiny bit smaller. !! 525 prompt "Split Cache Configuration"
495 CPU might render the kernel unbootab !! 526 default CACHE_I
496 527
497 If unsure, say N. !! 528 config CACHE_I
>> 529 bool "Instruction"
>> 530 help
>> 531 Use all of the ColdFire CPU cache memory as an instruction cache.
498 532
499 config CPU_SUP_ZHAOXIN !! 533 config CACHE_D
500 default y !! 534 bool "Data"
501 bool "Support Zhaoxin processors" if P <<
502 help 535 help
503 This enables detection, tunings and !! 536 Use all of the ColdFire CPU cache memory as a data cache.
504 537
505 You need this enabled if you want yo !! 538 config CACHE_BOTH
506 Zhaoxin CPU. Disabling this option o !! 539 bool "Both"
507 makes the kernel a tiny bit smaller. !! 540 help
508 CPU might render the kernel unbootab !! 541 Split the ColdFire CPU cache, and use half as an instruction cache
>> 542 and half as a data cache.
>> 543 endchoice
>> 544 endif
509 545
510 If unsure, say N. !! 546 if HAVE_CACHE_CB
>> 547 choice
>> 548 prompt "Data cache mode"
>> 549 default CACHE_WRITETHRU
511 550
512 config CPU_SUP_VORTEX_32 !! 551 config CACHE_WRITETHRU
513 default y !! 552 bool "Write-through"
514 bool "Support Vortex processors" if PR <<
515 depends on X86_32 <<
516 help 553 help
517 This enables detection, tunings and !! 554 The ColdFire CPU cache is set into Write-through mode.
518 555
519 You need this enabled if you want yo !! 556 config CACHE_COPYBACK
520 Vortex CPU. Disabling this option on !! 557 bool "Copy-back"
521 makes the kernel a tiny bit smaller. !! 558 help
>> 559 The ColdFire CPU cache is set into Copy-back mode.
>> 560 endchoice
>> 561 endif
522 562
523 If unsure, say N. <<
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