1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 # Put here option for CPU selection and depend !! 2 comment "Processor Type"
>> 3
3 choice 4 choice
4 prompt "Processor family" !! 5 prompt "CPU family support"
5 default M686 if X86_32 !! 6 default M68KCLASSIC if MMU
6 default GENERIC_CPU if X86_64 !! 7 default COLDFIRE if !MMU
7 help !! 8 help
8 This is the processor type of your C !! 9 The Freescale (was Motorola) M68K family of processors implements
9 used for optimizing purposes. In ord !! 10 the full 68000 processor instruction set.
10 that can run on all supported x86 CP !! 11 The Freescale ColdFire family of processors is a modern derivative
11 optimally fast), you can specify "48 !! 12 of the 68000 processor family. They are mainly targeted at embedded
12 !! 13 applications, and are all System-On-Chip (SOC) devices, as opposed
13 Note that the 386 is no longer suppo !! 14 to stand alone CPUs. They implement a subset of the original 68000
14 AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, !! 15 processor instruction set.
15 UMC 486SX-S and the NexGen Nx586. !! 16 If you anticipate running this kernel on a computer with a classic
16 !! 17 MC68xxx processor, select M68KCLASSIC.
17 The kernel will not necessarily run !! 18 If you anticipate running this kernel on a computer with a ColdFire
18 the one you have chosen, e.g. a Pent !! 19 processor, select COLDFIRE.
19 a PPro, but not necessarily on a i48 !! 20
20 !! 21 config M68KCLASSIC
21 Here are the settings recommended fo !! 22 bool "Classic M68K CPU family support"
22 - "486" for the AMD/Cyrix/IBM/Intel !! 23 select HAVE_ARCH_PFN_VALID
23 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5 !! 24
24 - "586" for generic Pentium CPUs lac !! 25 config COLDFIRE
25 (time stamp counter) register. !! 26 bool "Coldfire CPU family support"
26 - "Pentium-Classic" for the Intel Pe !! 27 select CPU_HAS_NO_BITFIELDS
27 - "Pentium-MMX" for the Intel Pentiu !! 28 select CPU_HAS_NO_CAS
28 - "Pentium-Pro" for the Intel Pentiu !! 29 select CPU_HAS_NO_MULDIV64
29 - "Pentium-II" for the Intel Pentium !! 30 select GENERIC_CSUM
30 - "Pentium-III" for the Intel Pentiu !! 31 select GPIOLIB
31 - "Pentium-4" for the Intel Pentium !! 32 select HAVE_LEGACY_CLK
32 - "K6" for the AMD K6, K6-II and K6- !! 33 select HAVE_PAGE_SIZE_8KB if !MMU
33 - "Athlon" for the AMD K7 family (At <<
34 - "Opteron/Athlon64/Hammer/K8" for a <<
35 - "Crusoe" for the Transmeta Crusoe <<
36 - "Efficeon" for the Transmeta Effic <<
37 - "Winchip-C6" for original IDT Winc <<
38 - "Winchip-2" for IDT Winchips with <<
39 - "AMD Elan" for the 32-bit AMD Elan <<
40 - "GeodeGX1" for Geode GX1 (Cyrix Me <<
41 - "Geode GX/LX" For AMD Geode GX and <<
42 - "CyrixIII/VIA C3" for VIA Cyrix II <<
43 - "VIA C3-2" for VIA C3-2 "Nehemiah" <<
44 - "VIA C7" for VIA C7. <<
45 - "Intel P4" for the Pentium 4/Netbu <<
46 - "Core 2/newer Xeon" for all core2 <<
47 - "Intel Atom" for the Atom-microarc <<
48 - "Generic-x86-64" for a kernel whic <<
49 <<
50 See each option's help text for addi <<
51 what to do, choose "486". <<
52 <<
53 config M486SX <<
54 bool "486SX" <<
55 depends on X86_32 <<
56 help <<
57 Select this for an 486-class CPU wit <<
58 AMD/Cyrix/IBM/Intel SL/SLC/SLC2/SLC3 <<
59 <<
60 config M486 <<
61 bool "486DX" <<
62 depends on X86_32 <<
63 help <<
64 Select this for an 486-class CPU suc <<
65 486DX/DX2/DX4 and UMC U5D. <<
66 <<
67 config M586 <<
68 bool "586/K5/5x86/6x86/6x86MX" <<
69 depends on X86_32 <<
70 help <<
71 Select this for an 586 or 686 series <<
72 the Cyrix 5x86, 6x86 and 6x86MX. Th <<
73 assume the RDTSC (Read Time Stamp Co <<
74 <<
75 config M586TSC <<
76 bool "Pentium-Classic" <<
77 depends on X86_32 <<
78 help <<
79 Select this for a Pentium Classic pr <<
80 Time Stamp Counter) instruction for <<
81 <<
82 config M586MMX <<
83 bool "Pentium-MMX" <<
84 depends on X86_32 <<
85 help <<
86 Select this for a Pentium with the M <<
87 extended instructions. <<
88 <<
89 config M686 <<
90 bool "Pentium-Pro" <<
91 depends on X86_32 <<
92 help <<
93 Select this for Intel Pentium Pro ch <<
94 Pentium Pro extended instructions, a <<
95 against the f00f bug found in earlie <<
96 <<
97 config MPENTIUMII <<
98 bool "Pentium-II/Celeron(pre-Coppermin <<
99 depends on X86_32 <<
100 help <<
101 Select this for Intel chips based on <<
102 pre-Coppermine Celeron core. This o <<
103 copy optimization, compiles the kern <<
104 tailored for the chip, and applies a <<
105 optimizations. <<
106 <<
107 config MPENTIUMIII <<
108 bool "Pentium-III/Celeron(Coppermine)/ <<
109 depends on X86_32 <<
110 help <<
111 Select this for Intel chips based on <<
112 Celeron-Coppermine core. This optio <<
113 extended prefetch instructions in ad <<
114 extensions. <<
115 <<
116 config MPENTIUMM <<
117 bool "Pentium M" <<
118 depends on X86_32 <<
119 help <<
120 Select this for Intel Pentium M (not <<
121 notebook chips. <<
122 <<
123 config MPENTIUM4 <<
124 bool "Pentium-4/Celeron(P4-based)/Pent <<
125 depends on X86_32 <<
126 help <<
127 Select this for Intel Pentium 4 chip <<
128 Pentium 4, Pentium D, P4-based Celer <<
129 Pentium-4 M (not Pentium M) chips. <<
130 flags optimized for the chip, uses t <<
131 applies any applicable optimizations <<
132 <<
133 CPUIDs: F[0-6][1-A] (in /proc/cpuinf <<
134 <<
135 Select this for: <<
136 Pentiums (Pentium 4, Pentium D, Ce <<
137 -Willamette <<
138 -Northwood <<
139 -Mobile Pentium 4 <<
140 -Mobile Pentium 4 M <<
141 -Extreme Edition (Gallatin) <<
142 -Prescott <<
143 -Prescott 2M <<
144 -Cedar Mill <<
145 -Presler <<
146 -Smithfiled <<
147 Xeons (Intel Xeon, Xeon MP, Xeon L <<
148 -Foster <<
149 -Prestonia <<
150 -Gallatin <<
151 -Nocona <<
152 -Irwindale <<
153 -Cranford <<
154 -Potomac <<
155 -Paxville <<
156 -Dempsey <<
157 <<
158 <<
159 config MK6 <<
160 bool "K6/K6-II/K6-III" <<
161 depends on X86_32 <<
162 help <<
163 Select this for an AMD K6-family pro <<
164 some extended instructions, and pass <<
165 flags to GCC. <<
166 <<
167 config MK7 <<
168 bool "Athlon/Duron/K7" <<
169 depends on X86_32 <<
170 help <<
171 Select this for an AMD Athlon K7-fam <<
172 some extended instructions, and pass <<
173 flags to GCC. <<
174 <<
175 config MK8 <<
176 bool "Opteron/Athlon64/Hammer/K8" <<
177 help <<
178 Select this for an AMD Opteron or At <<
179 Enables use of some extended instruc <<
180 optimization flags to GCC. <<
181 <<
182 config MCRUSOE <<
183 bool "Crusoe" <<
184 depends on X86_32 <<
185 help <<
186 Select this for a Transmeta Crusoe p <<
187 like a 586 with TSC, and sets some G <<
188 Pentium Pro with no alignment requir <<
189 <<
190 config MEFFICEON <<
191 bool "Efficeon" <<
192 depends on X86_32 <<
193 help <<
194 Select this for a Transmeta Efficeon <<
195 <<
196 config MWINCHIPC6 <<
197 bool "Winchip-C6" <<
198 depends on X86_32 <<
199 help <<
200 Select this for an IDT Winchip C6 ch <<
201 treat this chip as a 586TSC with som <<
202 and alignment requirements. <<
203 <<
204 config MWINCHIP3D <<
205 bool "Winchip-2/Winchip-2A/Winchip-3" <<
206 depends on X86_32 <<
207 help <<
208 Select this for an IDT Winchip-2, 2A <<
209 treat this chip as a 586TSC with som <<
210 and alignment requirements. Also en <<
211 stores for this CPU, which can incre <<
212 operations. <<
213 <<
214 config MELAN <<
215 bool "AMD Elan" <<
216 depends on X86_32 <<
217 help <<
218 Select this for an AMD Elan processo <<
219 <<
220 Do not use this option for K6/Athlon <<
221 <<
222 config MGEODEGX1 <<
223 bool "GeodeGX1" <<
224 depends on X86_32 <<
225 help <<
226 Select this for a Geode GX1 (Cyrix M <<
227 <<
228 config MGEODE_LX <<
229 bool "Geode GX/LX" <<
230 depends on X86_32 <<
231 help <<
232 Select this for AMD Geode GX and LX <<
233 <<
234 config MCYRIXIII <<
235 bool "CyrixIII/VIA-C3" <<
236 depends on X86_32 <<
237 help <<
238 Select this for a Cyrix III or C3 ch <<
239 treat this chip as a generic 586. Wh <<
240 it lacks the cmov extension which gc <<
241 generating 686 code. <<
242 Note that Nehemiah (Model 9) and abo <<
243 kernel due to them lacking the 3DNow <<
244 incarnations of the CPU. <<
245 <<
246 config MVIAC3_2 <<
247 bool "VIA C3-2 (Nehemiah)" <<
248 depends on X86_32 <<
249 help <<
250 Select this for a VIA C3 "Nehemiah". <<
251 of SSE and tells gcc to treat the CP <<
252 Note, this kernel will not boot on o <<
253 <<
254 config MVIAC7 <<
255 bool "VIA C7" <<
256 depends on X86_32 <<
257 help <<
258 Select this for a VIA C7. Selecting <<
259 shift and tells gcc to treat the CPU <<
260 <<
261 config MPSC <<
262 bool "Intel P4 / older Netburst based <<
263 depends on X86_64 <<
264 help <<
265 Optimize for Intel Pentium 4, Pentiu <<
266 Xeon CPUs with Intel 64bit which is <<
267 Note that the latest Xeons (Xeon 51x <<
268 Netburst core and shouldn't use this <<
269 using the cpu family field <<
270 in /proc/cpuinfo. Family 15 is an ol <<
271 <<
272 config MCORE2 <<
273 bool "Core 2/newer Xeon" <<
274 help <<
275 <<
276 Select this for Intel Core 2 and new <<
277 53xx) CPUs. You can distinguish newe <<
278 family in /proc/cpuinfo. Newer ones <<
279 (not a typo) <<
280 <<
281 config MATOM <<
282 bool "Intel Atom" <<
283 help <<
284 <<
285 Select this for the Intel Atom platf <<
286 in-order pipelining architecture and <<
287 accordingly optimized code. Use a re <<
288 support in order to fully benefit fr <<
289 <<
290 config GENERIC_CPU <<
291 bool "Generic-x86-64" <<
292 depends on X86_64 <<
293 help <<
294 Generic x86-64 CPU. <<
295 Run equally well on all x86-64 CPUs. <<
296 34
297 endchoice 35 endchoice
298 36
299 config X86_GENERIC !! 37 if M68KCLASSIC
300 bool "Generic x86 support" <<
301 depends on X86_32 <<
302 help <<
303 Instead of just including optimizati <<
304 x86 variant (e.g. PII, Crusoe or Ath <<
305 generic optimizations as well. This <<
306 perform better on x86 CPUs other tha <<
307 <<
308 This is really intended for distribu <<
309 generic optimizations. <<
310 <<
311 # <<
312 # Define implied options from the CPU selectio <<
313 config X86_INTERNODE_CACHE_SHIFT <<
314 int <<
315 default "12" if X86_VSMP <<
316 default X86_L1_CACHE_SHIFT <<
317 <<
318 config X86_L1_CACHE_SHIFT <<
319 int <<
320 default "7" if MPENTIUM4 || MPSC <<
321 default "6" if MK7 || MK8 || MPENTIUMM <<
322 default "4" if MELAN || M486SX || M486 <<
323 default "5" if MWINCHIP3D || MWINCHIPC <<
324 <<
325 config X86_F00F_BUG <<
326 def_bool y <<
327 depends on M586MMX || M586TSC || M586 <<
328 <<
329 config X86_INVD_BUG <<
330 def_bool y <<
331 depends on M486SX || M486 <<
332 <<
333 config X86_ALIGNMENT_16 <<
334 def_bool y <<
335 depends on MWINCHIP3D || MWINCHIPC6 || <<
336 <<
337 config X86_INTEL_USERCOPY <<
338 def_bool y <<
339 depends on MPENTIUM4 || MPENTIUMM || M <<
340 <<
341 config X86_USE_PPRO_CHECKSUM <<
342 def_bool y <<
343 depends on MWINCHIP3D || MWINCHIPC6 || <<
344 <<
345 # <<
346 # P6_NOPs are a relatively minor optimization <<
347 # 6 processor, except that it is broken on cer <<
348 # Furthermore, AMD chips prefer a totally diff <<
349 # (which work on all CPUs). In addition, it l <<
350 # does not understand them. <<
351 # <<
352 # As a result, disallow these if we're not com <<
353 # NOPs do work on all x86-64 capable chips); t <<
354 # the right-hand clause are the cores that ben <<
355 # <<
356 config X86_P6_NOP <<
357 def_bool y <<
358 depends on X86_64 <<
359 depends on (MCORE2 || MPENTIUM4 || MPS <<
360 <<
361 config X86_TSC <<
362 def_bool y <<
363 depends on (MWINCHIP3D || MCRUSOE || M <<
364 <<
365 config X86_HAVE_PAE <<
366 def_bool y <<
367 depends on MCRUSOE || MEFFICEON || MCY <<
368 <<
369 config X86_CMPXCHG64 <<
370 def_bool y <<
371 depends on X86_HAVE_PAE || M586TSC || <<
372 <<
373 # this should be set for all -march=.. options <<
374 # generates cmov. <<
375 config X86_CMOV <<
376 def_bool y <<
377 depends on (MK8 || MK7 || MCORE2 || MP <<
378 <<
379 config X86_MINIMUM_CPU_FAMILY <<
380 int <<
381 default "64" if X86_64 <<
382 default "6" if X86_32 && (MPENTIUM4 || <<
383 default "5" if X86_32 && X86_CMPXCHG64 <<
384 default "4" <<
385 38
386 config X86_DEBUGCTLMSR !! 39 config M68000
387 def_bool y 40 def_bool y
388 depends on !(MK6 || MWINCHIPC6 || MWIN !! 41 depends on !MMU
>> 42 select CPU_HAS_NO_BITFIELDS
>> 43 select CPU_HAS_NO_CAS
>> 44 select CPU_HAS_NO_MULDIV64
>> 45 select CPU_HAS_NO_UNALIGNED
>> 46 select GENERIC_CSUM
>> 47 select CPU_NO_EFFICIENT_FFS
>> 48 select HAVE_ARCH_HASH
>> 49 select HAVE_PAGE_SIZE_4KB
>> 50 select LEGACY_TIMER_TICK
>> 51 help
>> 52 The Freescale (was Motorola) 68000 CPU is the first generation of
>> 53 the well known M68K family of processors. The CPU core as well as
>> 54 being available as a stand alone CPU was also used in many
>> 55 System-On-Chip devices (eg 68328, 68302, etc). It does not contain
>> 56 a paging MMU.
>> 57
>> 58 config M68020
>> 59 bool "68020 support"
>> 60 depends on MMU
>> 61 select FPU
>> 62 select CPU_HAS_ADDRESS_SPACES
>> 63 help
>> 64 If you anticipate running this kernel on a computer with a MC68020
>> 65 processor, say Y. Otherwise, say N. Note that the 68020 requires a
>> 66 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the
>> 67 Sun 3, which provides its own version.
>> 68
>> 69 config M68030
>> 70 bool "68030 support"
>> 71 depends on MMU && !MMU_SUN3
>> 72 select FPU
>> 73 select CPU_HAS_ADDRESS_SPACES
>> 74 help
>> 75 If you anticipate running this kernel on a computer with a MC68030
>> 76 processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
>> 77 work, as it does not include an MMU (Memory Management Unit).
>> 78
>> 79 config M68040
>> 80 bool "68040 support"
>> 81 depends on MMU && !MMU_SUN3
>> 82 select FPU
>> 83 select CPU_HAS_ADDRESS_SPACES
>> 84 help
>> 85 If you anticipate running this kernel on a computer with a MC68LC040
>> 86 or MC68040 processor, say Y. Otherwise, say N. Note that an
>> 87 MC68EC040 will not work, as it does not include an MMU (Memory
>> 88 Management Unit).
>> 89
>> 90 config M68060
>> 91 bool "68060 support"
>> 92 depends on MMU && !MMU_SUN3
>> 93 select FPU
>> 94 select CPU_HAS_ADDRESS_SPACES
>> 95 help
>> 96 If you anticipate running this kernel on a computer with a MC68060
>> 97 processor, say Y. Otherwise, say N.
>> 98
>> 99 config M68328
>> 100 bool
>> 101 depends on !MMU
>> 102 select M68000
>> 103 help
>> 104 Motorola 68328 processor support.
>> 105
>> 106 config M68EZ328
>> 107 bool
>> 108 depends on !MMU
>> 109 select M68000
>> 110 help
>> 111 Motorola 68EX328 processor support.
>> 112
>> 113 config M68VZ328
>> 114 bool
>> 115 depends on !MMU
>> 116 select M68000
>> 117 help
>> 118 Motorola 68VZ328 processor support.
389 119
390 config IA32_FEAT_CTL !! 120 endif # M68KCLASSIC
391 def_bool y <<
392 depends on CPU_SUP_INTEL || CPU_SUP_CE <<
393 121
394 config X86_VMX_FEATURE_NAMES !! 122 if COLDFIRE
395 def_bool y <<
396 depends on IA32_FEAT_CTL <<
397 123
398 menuconfig PROCESSOR_SELECT !! 124 choice
399 bool "Supported processor vendors" if !! 125 prompt "ColdFire SoC type"
>> 126 default M520x
400 help 127 help
401 This lets you choose what x86 vendor !! 128 Select the type of ColdFire System-on-Chip (SoC) that you want
402 will include. !! 129 to build for.
403 130
404 config CPU_SUP_INTEL !! 131 config M5206
405 default y !! 132 bool "MCF5206"
406 bool "Support Intel processors" if PRO !! 133 depends on !MMU
>> 134 select COLDFIRE_SW_A7
>> 135 select COLDFIRE_TIMERS
>> 136 select HAVE_MBAR
>> 137 select CPU_NO_EFFICIENT_FFS
>> 138 help
>> 139 Motorola ColdFire 5206 processor support.
>> 140
>> 141 config M5206e
>> 142 bool "MCF5206e"
>> 143 depends on !MMU
>> 144 select COLDFIRE_SW_A7
>> 145 select COLDFIRE_TIMERS
>> 146 select HAVE_MBAR
>> 147 select CPU_NO_EFFICIENT_FFS
>> 148 help
>> 149 Motorola ColdFire 5206e processor support.
>> 150
>> 151 config M520x
>> 152 bool "MCF520x"
>> 153 depends on !MMU
>> 154 select COLDFIRE_PIT_TIMER
>> 155 select HAVE_CACHE_SPLIT
>> 156 help
>> 157 Freescale Coldfire 5207/5208 processor support.
>> 158
>> 159 config M523x
>> 160 bool "MCF523x"
>> 161 depends on !MMU
>> 162 select COLDFIRE_PIT_TIMER
>> 163 select HAVE_CACHE_SPLIT
>> 164 select HAVE_IPSBAR
>> 165 help
>> 166 Freescale Coldfire 5230/1/2/4/5 processor support
>> 167
>> 168 config M5249
>> 169 bool "MCF5249"
>> 170 depends on !MMU
>> 171 select COLDFIRE_SW_A7
>> 172 select COLDFIRE_TIMERS
>> 173 select HAVE_MBAR
>> 174 select CPU_NO_EFFICIENT_FFS
>> 175 help
>> 176 Motorola ColdFire 5249 processor support.
>> 177
>> 178 config M525x
>> 179 bool "MCF525x"
>> 180 depends on !MMU
>> 181 select COLDFIRE_SW_A7
>> 182 select COLDFIRE_TIMERS
>> 183 select HAVE_MBAR
>> 184 select CPU_NO_EFFICIENT_FFS
>> 185 help
>> 186 Freescale (Motorola) Coldfire 5251/5253 processor support.
>> 187
>> 188 config M5271
>> 189 bool "MCF5271"
>> 190 depends on !MMU
>> 191 select COLDFIRE_PIT_TIMER
>> 192 select M527x
>> 193 select HAVE_CACHE_SPLIT
>> 194 select HAVE_IPSBAR
>> 195 help
>> 196 Freescale (Motorola) ColdFire 5270/5271 processor support.
>> 197
>> 198 config M5272
>> 199 bool "MCF5272"
>> 200 depends on !MMU
>> 201 select COLDFIRE_SW_A7
>> 202 select COLDFIRE_TIMERS
>> 203 select HAVE_MBAR
>> 204 select CPU_NO_EFFICIENT_FFS
>> 205 help
>> 206 Motorola ColdFire 5272 processor support.
>> 207
>> 208 config M5275
>> 209 bool "MCF5275"
>> 210 depends on !MMU
>> 211 select COLDFIRE_PIT_TIMER
>> 212 select M527x
>> 213 select HAVE_CACHE_SPLIT
>> 214 select HAVE_IPSBAR
>> 215 help
>> 216 Freescale (Motorola) ColdFire 5274/5275 processor support.
>> 217
>> 218 config M528x
>> 219 bool "MCF528x"
>> 220 depends on !MMU
>> 221 select COLDFIRE_PIT_TIMER
>> 222 select HAVE_CACHE_SPLIT
>> 223 select HAVE_IPSBAR
>> 224 help
>> 225 Motorola ColdFire 5280/5282 processor support.
>> 226
>> 227 config M5307
>> 228 bool "MCF5307"
>> 229 depends on !MMU
>> 230 select COLDFIRE_TIMERS
>> 231 select COLDFIRE_SW_A7
>> 232 select HAVE_CACHE_CB
>> 233 select HAVE_MBAR
>> 234 select CPU_NO_EFFICIENT_FFS
>> 235 help
>> 236 Motorola ColdFire 5307 processor support.
>> 237
>> 238 config M532x
>> 239 bool "MCF532x"
>> 240 depends on !MMU
>> 241 select COLDFIRE_TIMERS
>> 242 select M53xx
>> 243 select HAVE_CACHE_CB
>> 244 help
>> 245 Freescale (Motorola) ColdFire 532x processor support.
>> 246
>> 247 config M537x
>> 248 bool "MCF537x"
>> 249 depends on !MMU
>> 250 select COLDFIRE_TIMERS
>> 251 select M53xx
>> 252 select HAVE_CACHE_CB
>> 253 help
>> 254 Freescale ColdFire 537x processor support.
>> 255
>> 256 config M5407
>> 257 bool "MCF5407"
>> 258 depends on !MMU
>> 259 select COLDFIRE_SW_A7
>> 260 select COLDFIRE_TIMERS
>> 261 select HAVE_CACHE_CB
>> 262 select HAVE_MBAR
>> 263 select CPU_NO_EFFICIENT_FFS
>> 264 help
>> 265 Motorola ColdFire 5407 processor support.
>> 266
>> 267 config M547x
>> 268 bool "MCF547x"
>> 269 select M54xx
>> 270 select COLDFIRE_SLTIMERS
>> 271 select MMU_COLDFIRE if MMU
>> 272 select FPU if MMU
>> 273 select HAVE_CACHE_CB
>> 274 select HAVE_MBAR
>> 275 select CPU_NO_EFFICIENT_FFS
>> 276 help
>> 277 Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
>> 278
>> 279 config M548x
>> 280 bool "MCF548x"
>> 281 select COLDFIRE_SLTIMERS
>> 282 select MMU_COLDFIRE if MMU
>> 283 select FPU if MMU
>> 284 select M54xx
>> 285 select HAVE_CACHE_CB
>> 286 select HAVE_MBAR
>> 287 select CPU_NO_EFFICIENT_FFS
>> 288 help
>> 289 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
>> 290
>> 291 config M5441x
>> 292 bool "MCF5441x"
>> 293 select COLDFIRE_PIT_TIMER
>> 294 select MMU_COLDFIRE if MMU
>> 295 select HAVE_CACHE_CB
407 help 296 help
408 This enables detection, tunings and !! 297 Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
409 298
410 You need this enabled if you want yo !! 299 endchoice
411 Intel CPU. Disabling this option on <<
412 makes the kernel a tiny bit smaller. <<
413 CPU might render the kernel unbootab <<
414 <<
415 If unsure, say N. <<
416 <<
417 config CPU_SUP_CYRIX_32 <<
418 default y <<
419 bool "Support Cyrix processors" if PRO <<
420 depends on M486SX || M486 || M586 || M <<
421 help <<
422 This enables detection, tunings and <<
423 300
424 You need this enabled if you want yo !! 301 config M527x
425 Cyrix CPU. Disabling this option on !! 302 bool
426 makes the kernel a tiny bit smaller. <<
427 CPU might render the kernel unbootab <<
428 303
429 If unsure, say N. !! 304 config M53xx
>> 305 bool
430 306
431 config CPU_SUP_AMD !! 307 config M54xx
>> 308 select HAVE_PCI
>> 309 bool
>> 310
>> 311 config COLDFIRE_PIT_TIMER
>> 312 bool
>> 313
>> 314 config COLDFIRE_TIMERS
>> 315 bool
>> 316 select LEGACY_TIMER_TICK
>> 317
>> 318 config COLDFIRE_SLTIMERS
>> 319 bool
>> 320 select LEGACY_TIMER_TICK
>> 321
>> 322 endif # COLDFIRE
>> 323
>> 324 comment "Processor Specific Options"
>> 325
>> 326 config M68KFPU_EMU
>> 327 bool "Math emulation support"
>> 328 depends on M68KCLASSIC && FPU
>> 329 help
>> 330 At some point in the future, this will cause floating-point math
>> 331 instructions to be emulated by the kernel on machines that lack a
>> 332 floating-point math coprocessor. Thrill-seekers and chronically
>> 333 sleep-deprived psychotic hacker types can say Y now, everyone else
>> 334 should probably wait a while.
>> 335
>> 336 config M68KFPU_EMU_EXTRAPREC
>> 337 bool "Math emulation extra precision"
>> 338 depends on M68KFPU_EMU
>> 339 help
>> 340 The fpu uses normally a few bit more during calculations for
>> 341 correct rounding, the emulator can (often) do the same but this
>> 342 extra calculation can cost quite some time, so you can disable
>> 343 it here. The emulator will then "only" calculate with a 64 bit
>> 344 mantissa and round slightly incorrect, what is more than enough
>> 345 for normal usage.
>> 346
>> 347 config M68KFPU_EMU_ONLY
>> 348 bool "Math emulation only kernel"
>> 349 depends on M68KFPU_EMU
>> 350 help
>> 351 This option prevents any floating-point instructions from being
>> 352 compiled into the kernel, thereby the kernel doesn't save any
>> 353 floating point context anymore during task switches, so this
>> 354 kernel will only be usable on machines without a floating-point
>> 355 math coprocessor. This makes the kernel a bit faster as no tests
>> 356 needs to be executed whether a floating-point instruction in the
>> 357 kernel should be executed or not.
>> 358
>> 359 config ADVANCED
>> 360 bool "Advanced configuration options"
>> 361 depends on MMU
>> 362 help
>> 363 This gives you access to some advanced options for the CPU. The
>> 364 defaults should be fine for most users, but these options may make
>> 365 it possible for you to improve performance somewhat if you know what
>> 366 you are doing.
>> 367
>> 368 Note that the answer to this question won't directly affect the
>> 369 kernel: saying N will just cause the configurator to skip all
>> 370 the questions about these options.
>> 371
>> 372 Most users should say N to this question.
>> 373
>> 374 config RMW_INSNS
>> 375 bool "Use read-modify-write instructions"
>> 376 depends on ADVANCED && !CPU_HAS_NO_CAS
>> 377 help
>> 378 This allows to use certain instructions that work with indivisible
>> 379 read-modify-write bus cycles. While this is faster than the
>> 380 workaround of disabling interrupts, it can conflict with DMA
>> 381 ( = direct memory access) on many Amiga systems, and it is also said
>> 382 to destabilize other machines. It is very likely that this will
>> 383 cause serious problems on any Amiga or Atari Medusa if set. The only
>> 384 configuration where it should work are 68030-based Ataris, where it
>> 385 apparently improves performance. But you've been warned! Unless you
>> 386 really know what you are doing, say N. Try Y only if you're quite
>> 387 adventurous.
>> 388
>> 389 config SINGLE_MEMORY_CHUNK
>> 390 bool "Use one physical chunk of memory only" if ADVANCED && !SUN3
>> 391 depends on MMU
>> 392 default y if SUN3 || MMU_COLDFIRE
>> 393 help
>> 394 Ignore all but the first contiguous chunk of physical memory for VM
>> 395 purposes. This will save a few bytes kernel size and may speed up
>> 396 some operations.
>> 397 When this option os set to N, you may want to lower "Maximum zone
>> 398 order" to save memory that could be wasted for unused memory map.
>> 399 Say N if not sure.
>> 400
>> 401 config ARCH_FORCE_MAX_ORDER
>> 402 int "Order of maximal physically contiguous allocations" if ADVANCED
>> 403 depends on !SINGLE_MEMORY_CHUNK
>> 404 default "10"
>> 405 help
>> 406 The kernel page allocator limits the size of maximal physically
>> 407 contiguous allocations. The limit is called MAX_PAGE_ORDER and it
>> 408 defines the maximal power of two of number of pages that can be
>> 409 allocated as a single contiguous block. This option allows
>> 410 overriding the default setting when ability to allocate very
>> 411 large blocks of physically contiguous memory is required.
>> 412
>> 413 For systems that have holes in their physical address space this
>> 414 value also defines the minimal size of the hole that allows
>> 415 freeing unused memory map.
>> 416
>> 417 Don't change if unsure.
>> 418
>> 419 config 060_WRITETHROUGH
>> 420 bool "Use write-through caching for 68060 supervisor accesses"
>> 421 depends on ADVANCED && M68060
>> 422 help
>> 423 The 68060 generally uses copyback caching of recently accessed data.
>> 424 Copyback caching means that memory writes will be held in an on-chip
>> 425 cache and only written back to memory some time later. Saying Y
>> 426 here will force supervisor (kernel) accesses to use writethrough
>> 427 caching. Writethrough caching means that data is written to memory
>> 428 straight away, so that cache and memory data always agree.
>> 429 Writethrough caching is less efficient, but is needed for some
>> 430 drivers on 68060 based systems where the 68060 bus snooping signal
>> 431 is hardwired on. The 53c710 SCSI driver is known to suffer from
>> 432 this problem.
>> 433
>> 434 config M68K_L2_CACHE
>> 435 bool
>> 436 depends on MAC
432 default y 437 default y
433 bool "Support AMD processors" if PROCE <<
434 help <<
435 This enables detection, tunings and <<
436 <<
437 You need this enabled if you want yo <<
438 AMD CPU. Disabling this option on ot <<
439 makes the kernel a tiny bit smaller. <<
440 CPU might render the kernel unbootab <<
441 438
442 If unsure, say N. !! 439 config CPU_HAS_NO_BITFIELDS
>> 440 bool
443 441
444 config CPU_SUP_HYGON !! 442 config CPU_HAS_NO_CAS
445 default y !! 443 bool
446 bool "Support Hygon processors" if PRO <<
447 select CPU_SUP_AMD <<
448 help <<
449 This enables detection, tunings and <<
450 444
451 You need this enabled if you want yo !! 445 config CPU_HAS_NO_MULDIV64
452 Hygon CPU. Disabling this option on !! 446 bool
453 makes the kernel a tiny bit smaller. <<
454 CPU might render the kernel unbootab <<
455 447
456 If unsure, say N. !! 448 config CPU_HAS_NO_UNALIGNED
457 !! 449 bool
458 config CPU_SUP_CENTAUR !! 450
459 default y !! 451 config CPU_HAS_ADDRESS_SPACES
460 bool "Support Centaur processors" if P !! 452 bool
>> 453 select ALTERNATE_USER_ADDRESS_SPACE
>> 454
>> 455 config FPU
>> 456 bool
>> 457
>> 458 config COLDFIRE_SW_A7
>> 459 bool
>> 460
>> 461 config HAVE_CACHE_SPLIT
>> 462 bool
>> 463
>> 464 config HAVE_CACHE_CB
>> 465 bool
>> 466
>> 467 config HAVE_MBAR
>> 468 bool
>> 469
>> 470 config HAVE_IPSBAR
>> 471 bool
>> 472
>> 473 config CLOCK_FREQ
>> 474 int "Set the core clock frequency"
>> 475 default "25000000" if M5206
>> 476 default "54000000" if M5206e
>> 477 default "166666666" if M520x
>> 478 default "140000000" if M5249
>> 479 default "150000000" if M527x || M523x
>> 480 default "90000000" if M5307
>> 481 default "50000000" if M5407
>> 482 default "266000000" if M54xx
>> 483 default "66666666"
>> 484 depends on COLDFIRE
>> 485 help
>> 486 Define the CPU clock frequency in use. This is the core clock
>> 487 frequency, it may or may not be the same as the external clock
>> 488 crystal fitted to your board. Some processors have an internal
>> 489 PLL and can have their frequency programmed at run time, others
>> 490 use internal dividers. In general the kernel won't setup a PLL
>> 491 if it is fitted (there are some exceptions). This value will be
>> 492 specific to the exact CPU that you are using.
>> 493
>> 494 config OLDMASK
>> 495 bool "Old mask 5307 (1H55J) silicon"
>> 496 depends on M5307
461 help 497 help
462 This enables detection, tunings and !! 498 Build support for the older revision ColdFire 5307 silicon.
>> 499 Specifically this is the 1H55J mask revision.
463 500
464 You need this enabled if you want yo !! 501 if HAVE_CACHE_SPLIT
465 Centaur CPU. Disabling this option o !! 502 choice
466 makes the kernel a tiny bit smaller. !! 503 prompt "Split Cache Configuration"
467 CPU might render the kernel unbootab !! 504 default CACHE_I
468 <<
469 If unsure, say N. <<
470 505
471 config CPU_SUP_TRANSMETA_32 !! 506 config CACHE_I
472 default y !! 507 bool "Instruction"
473 bool "Support Transmeta processors" if <<
474 depends on !64BIT <<
475 help 508 help
476 This enables detection, tunings and !! 509 Use all of the ColdFire CPU cache memory as an instruction cache.
477 510
478 You need this enabled if you want yo !! 511 config CACHE_D
479 Transmeta CPU. Disabling this option !! 512 bool "Data"
480 makes the kernel a tiny bit smaller. <<
481 CPU might render the kernel unbootab <<
482 <<
483 If unsure, say N. <<
484 <<
485 config CPU_SUP_UMC_32 <<
486 default y <<
487 bool "Support UMC processors" if PROCE <<
488 depends on M486SX || M486 || (EXPERT & <<
489 help 513 help
490 This enables detection, tunings and !! 514 Use all of the ColdFire CPU cache memory as a data cache.
491 <<
492 You need this enabled if you want yo <<
493 UMC CPU. Disabling this option on ot <<
494 makes the kernel a tiny bit smaller. <<
495 CPU might render the kernel unbootab <<
496 515
497 If unsure, say N. !! 516 config CACHE_BOTH
498 !! 517 bool "Both"
499 config CPU_SUP_ZHAOXIN <<
500 default y <<
501 bool "Support Zhaoxin processors" if P <<
502 help 518 help
503 This enables detection, tunings and !! 519 Split the ColdFire CPU cache, and use half as an instruction cache
>> 520 and half as a data cache.
>> 521 endchoice
>> 522 endif # HAVE_CACHE_SPLIT
504 523
505 You need this enabled if you want yo !! 524 if HAVE_CACHE_CB
506 Zhaoxin CPU. Disabling this option o !! 525 choice
507 makes the kernel a tiny bit smaller. !! 526 prompt "Data cache mode"
508 CPU might render the kernel unbootab !! 527 default CACHE_WRITETHRU
509 528
510 If unsure, say N. !! 529 config CACHE_WRITETHRU
>> 530 bool "Write-through"
>> 531 help
>> 532 The ColdFire CPU cache is set into Write-through mode.
511 533
512 config CPU_SUP_VORTEX_32 !! 534 config CACHE_COPYBACK
513 default y !! 535 bool "Copy-back"
514 bool "Support Vortex processors" if PR <<
515 depends on X86_32 <<
516 help 536 help
517 This enables detection, tunings and !! 537 The ColdFire CPU cache is set into Copy-back mode.
>> 538 endchoice
>> 539 endif # HAVE_CACHE_CB
518 540
519 You need this enabled if you want yo !! 541 # Coldfire cores that do not have a data cache configured can do coherent DMA.
520 Vortex CPU. Disabling this option on !! 542 config COLDFIRE_COHERENT_DMA
521 makes the kernel a tiny bit smaller. !! 543 bool
>> 544 default y
>> 545 depends on COLDFIRE
>> 546 depends on !HAVE_CACHE_CB && !CACHE_D && !CACHE_BOTH
522 547
523 If unsure, say N. !! 548 config M68K_NONCOHERENT_DMA
>> 549 bool
>> 550 default y
>> 551 depends on HAS_DMA && !COLDFIRE_COHERENT_DMA
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.