1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 # Put here option for CPU selection and depend !! 2 comment "Processor Type"
>> 3
3 choice 4 choice
4 prompt "Processor family" !! 5 prompt "CPU family support"
5 default M686 if X86_32 !! 6 default M68KCLASSIC if MMU
6 default GENERIC_CPU if X86_64 !! 7 default COLDFIRE if !MMU
7 help !! 8 help
8 This is the processor type of your C !! 9 The Freescale (was Motorola) M68K family of processors implements
9 used for optimizing purposes. In ord !! 10 the full 68000 processor instruction set.
10 that can run on all supported x86 CP !! 11 The Freescale ColdFire family of processors is a modern derivative
11 optimally fast), you can specify "48 !! 12 of the 68000 processor family. They are mainly targeted at embedded
12 !! 13 applications, and are all System-On-Chip (SOC) devices, as opposed
13 Note that the 386 is no longer suppo !! 14 to stand alone CPUs. They implement a subset of the original 68000
14 AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, !! 15 processor instruction set.
15 UMC 486SX-S and the NexGen Nx586. !! 16 If you anticipate running this kernel on a computer with a classic
16 !! 17 MC68xxx processor, select M68KCLASSIC.
17 The kernel will not necessarily run !! 18 If you anticipate running this kernel on a computer with a ColdFire
18 the one you have chosen, e.g. a Pent !! 19 processor, select COLDFIRE.
19 a PPro, but not necessarily on a i48 !! 20
20 !! 21 config M68KCLASSIC
21 Here are the settings recommended fo !! 22 bool "Classic M68K CPU family support"
22 - "486" for the AMD/Cyrix/IBM/Intel !! 23 select HAVE_ARCH_PFN_VALID
23 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5 !! 24
24 - "586" for generic Pentium CPUs lac !! 25 config COLDFIRE
25 (time stamp counter) register. !! 26 bool "Coldfire CPU family support"
26 - "Pentium-Classic" for the Intel Pe !! 27 select CPU_HAS_NO_BITFIELDS
27 - "Pentium-MMX" for the Intel Pentiu !! 28 select CPU_HAS_NO_CAS
28 - "Pentium-Pro" for the Intel Pentiu !! 29 select CPU_HAS_NO_MULDIV64
29 - "Pentium-II" for the Intel Pentium !! 30 select GENERIC_CSUM
30 - "Pentium-III" for the Intel Pentiu !! 31 select GPIOLIB
31 - "Pentium-4" for the Intel Pentium !! 32 select HAVE_LEGACY_CLK
32 - "K6" for the AMD K6, K6-II and K6- <<
33 - "Athlon" for the AMD K7 family (At <<
34 - "Opteron/Athlon64/Hammer/K8" for a <<
35 - "Crusoe" for the Transmeta Crusoe <<
36 - "Efficeon" for the Transmeta Effic <<
37 - "Winchip-C6" for original IDT Winc <<
38 - "Winchip-2" for IDT Winchips with <<
39 - "AMD Elan" for the 32-bit AMD Elan <<
40 - "GeodeGX1" for Geode GX1 (Cyrix Me <<
41 - "Geode GX/LX" For AMD Geode GX and <<
42 - "CyrixIII/VIA C3" for VIA Cyrix II <<
43 - "VIA C3-2" for VIA C3-2 "Nehemiah" <<
44 - "VIA C7" for VIA C7. <<
45 - "Intel P4" for the Pentium 4/Netbu <<
46 - "Core 2/newer Xeon" for all core2 <<
47 - "Intel Atom" for the Atom-microarc <<
48 - "Generic-x86-64" for a kernel whic <<
49 <<
50 See each option's help text for addi <<
51 what to do, choose "486". <<
52 <<
53 config M486SX <<
54 bool "486SX" <<
55 depends on X86_32 <<
56 help <<
57 Select this for an 486-class CPU wit <<
58 AMD/Cyrix/IBM/Intel SL/SLC/SLC2/SLC3 <<
59 <<
60 config M486 <<
61 bool "486DX" <<
62 depends on X86_32 <<
63 help <<
64 Select this for an 486-class CPU suc <<
65 486DX/DX2/DX4 and UMC U5D. <<
66 <<
67 config M586 <<
68 bool "586/K5/5x86/6x86/6x86MX" <<
69 depends on X86_32 <<
70 help <<
71 Select this for an 586 or 686 series <<
72 the Cyrix 5x86, 6x86 and 6x86MX. Th <<
73 assume the RDTSC (Read Time Stamp Co <<
74 <<
75 config M586TSC <<
76 bool "Pentium-Classic" <<
77 depends on X86_32 <<
78 help <<
79 Select this for a Pentium Classic pr <<
80 Time Stamp Counter) instruction for <<
81 <<
82 config M586MMX <<
83 bool "Pentium-MMX" <<
84 depends on X86_32 <<
85 help <<
86 Select this for a Pentium with the M <<
87 extended instructions. <<
88 <<
89 config M686 <<
90 bool "Pentium-Pro" <<
91 depends on X86_32 <<
92 help <<
93 Select this for Intel Pentium Pro ch <<
94 Pentium Pro extended instructions, a <<
95 against the f00f bug found in earlie <<
96 <<
97 config MPENTIUMII <<
98 bool "Pentium-II/Celeron(pre-Coppermin <<
99 depends on X86_32 <<
100 help <<
101 Select this for Intel chips based on <<
102 pre-Coppermine Celeron core. This o <<
103 copy optimization, compiles the kern <<
104 tailored for the chip, and applies a <<
105 optimizations. <<
106 <<
107 config MPENTIUMIII <<
108 bool "Pentium-III/Celeron(Coppermine)/ <<
109 depends on X86_32 <<
110 help <<
111 Select this for Intel chips based on <<
112 Celeron-Coppermine core. This optio <<
113 extended prefetch instructions in ad <<
114 extensions. <<
115 <<
116 config MPENTIUMM <<
117 bool "Pentium M" <<
118 depends on X86_32 <<
119 help <<
120 Select this for Intel Pentium M (not <<
121 notebook chips. <<
122 <<
123 config MPENTIUM4 <<
124 bool "Pentium-4/Celeron(P4-based)/Pent <<
125 depends on X86_32 <<
126 help <<
127 Select this for Intel Pentium 4 chip <<
128 Pentium 4, Pentium D, P4-based Celer <<
129 Pentium-4 M (not Pentium M) chips. <<
130 flags optimized for the chip, uses t <<
131 applies any applicable optimizations <<
132 <<
133 CPUIDs: F[0-6][1-A] (in /proc/cpuinf <<
134 <<
135 Select this for: <<
136 Pentiums (Pentium 4, Pentium D, Ce <<
137 -Willamette <<
138 -Northwood <<
139 -Mobile Pentium 4 <<
140 -Mobile Pentium 4 M <<
141 -Extreme Edition (Gallatin) <<
142 -Prescott <<
143 -Prescott 2M <<
144 -Cedar Mill <<
145 -Presler <<
146 -Smithfiled <<
147 Xeons (Intel Xeon, Xeon MP, Xeon L <<
148 -Foster <<
149 -Prestonia <<
150 -Gallatin <<
151 -Nocona <<
152 -Irwindale <<
153 -Cranford <<
154 -Potomac <<
155 -Paxville <<
156 -Dempsey <<
157 <<
158 <<
159 config MK6 <<
160 bool "K6/K6-II/K6-III" <<
161 depends on X86_32 <<
162 help <<
163 Select this for an AMD K6-family pro <<
164 some extended instructions, and pass <<
165 flags to GCC. <<
166 <<
167 config MK7 <<
168 bool "Athlon/Duron/K7" <<
169 depends on X86_32 <<
170 help <<
171 Select this for an AMD Athlon K7-fam <<
172 some extended instructions, and pass <<
173 flags to GCC. <<
174 <<
175 config MK8 <<
176 bool "Opteron/Athlon64/Hammer/K8" <<
177 help <<
178 Select this for an AMD Opteron or At <<
179 Enables use of some extended instruc <<
180 optimization flags to GCC. <<
181 <<
182 config MCRUSOE <<
183 bool "Crusoe" <<
184 depends on X86_32 <<
185 help <<
186 Select this for a Transmeta Crusoe p <<
187 like a 586 with TSC, and sets some G <<
188 Pentium Pro with no alignment requir <<
189 <<
190 config MEFFICEON <<
191 bool "Efficeon" <<
192 depends on X86_32 <<
193 help <<
194 Select this for a Transmeta Efficeon <<
195 <<
196 config MWINCHIPC6 <<
197 bool "Winchip-C6" <<
198 depends on X86_32 <<
199 help <<
200 Select this for an IDT Winchip C6 ch <<
201 treat this chip as a 586TSC with som <<
202 and alignment requirements. <<
203 <<
204 config MWINCHIP3D <<
205 bool "Winchip-2/Winchip-2A/Winchip-3" <<
206 depends on X86_32 <<
207 help <<
208 Select this for an IDT Winchip-2, 2A <<
209 treat this chip as a 586TSC with som <<
210 and alignment requirements. Also en <<
211 stores for this CPU, which can incre <<
212 operations. <<
213 <<
214 config MELAN <<
215 bool "AMD Elan" <<
216 depends on X86_32 <<
217 help <<
218 Select this for an AMD Elan processo <<
219 <<
220 Do not use this option for K6/Athlon <<
221 <<
222 config MGEODEGX1 <<
223 bool "GeodeGX1" <<
224 depends on X86_32 <<
225 help <<
226 Select this for a Geode GX1 (Cyrix M <<
227 <<
228 config MGEODE_LX <<
229 bool "Geode GX/LX" <<
230 depends on X86_32 <<
231 help <<
232 Select this for AMD Geode GX and LX <<
233 <<
234 config MCYRIXIII <<
235 bool "CyrixIII/VIA-C3" <<
236 depends on X86_32 <<
237 help <<
238 Select this for a Cyrix III or C3 ch <<
239 treat this chip as a generic 586. Wh <<
240 it lacks the cmov extension which gc <<
241 generating 686 code. <<
242 Note that Nehemiah (Model 9) and abo <<
243 kernel due to them lacking the 3DNow <<
244 incarnations of the CPU. <<
245 <<
246 config MVIAC3_2 <<
247 bool "VIA C3-2 (Nehemiah)" <<
248 depends on X86_32 <<
249 help <<
250 Select this for a VIA C3 "Nehemiah". <<
251 of SSE and tells gcc to treat the CP <<
252 Note, this kernel will not boot on o <<
253 <<
254 config MVIAC7 <<
255 bool "VIA C7" <<
256 depends on X86_32 <<
257 help <<
258 Select this for a VIA C7. Selecting <<
259 shift and tells gcc to treat the CPU <<
260 <<
261 config MPSC <<
262 bool "Intel P4 / older Netburst based <<
263 depends on X86_64 <<
264 help <<
265 Optimize for Intel Pentium 4, Pentiu <<
266 Xeon CPUs with Intel 64bit which is <<
267 Note that the latest Xeons (Xeon 51x <<
268 Netburst core and shouldn't use this <<
269 using the cpu family field <<
270 in /proc/cpuinfo. Family 15 is an ol <<
271 <<
272 config MCORE2 <<
273 bool "Core 2/newer Xeon" <<
274 help <<
275 <<
276 Select this for Intel Core 2 and new <<
277 53xx) CPUs. You can distinguish newe <<
278 family in /proc/cpuinfo. Newer ones <<
279 (not a typo) <<
280 <<
281 config MATOM <<
282 bool "Intel Atom" <<
283 help <<
284 <<
285 Select this for the Intel Atom platf <<
286 in-order pipelining architecture and <<
287 accordingly optimized code. Use a re <<
288 support in order to fully benefit fr <<
289 <<
290 config GENERIC_CPU <<
291 bool "Generic-x86-64" <<
292 depends on X86_64 <<
293 help <<
294 Generic x86-64 CPU. <<
295 Run equally well on all x86-64 CPUs. <<
296 33
297 endchoice 34 endchoice
298 35
299 config X86_GENERIC !! 36 if M68KCLASSIC
300 bool "Generic x86 support" <<
301 depends on X86_32 <<
302 help <<
303 Instead of just including optimizati <<
304 x86 variant (e.g. PII, Crusoe or Ath <<
305 generic optimizations as well. This <<
306 perform better on x86 CPUs other tha <<
307 <<
308 This is really intended for distribu <<
309 generic optimizations. <<
310 <<
311 # <<
312 # Define implied options from the CPU selectio <<
313 config X86_INTERNODE_CACHE_SHIFT <<
314 int <<
315 default "12" if X86_VSMP <<
316 default X86_L1_CACHE_SHIFT <<
317 <<
318 config X86_L1_CACHE_SHIFT <<
319 int <<
320 default "7" if MPENTIUM4 || MPSC <<
321 default "6" if MK7 || MK8 || MPENTIUMM <<
322 default "4" if MELAN || M486SX || M486 <<
323 default "5" if MWINCHIP3D || MWINCHIPC <<
324 <<
325 config X86_F00F_BUG <<
326 def_bool y <<
327 depends on M586MMX || M586TSC || M586 <<
328 <<
329 config X86_INVD_BUG <<
330 def_bool y <<
331 depends on M486SX || M486 <<
332 <<
333 config X86_ALIGNMENT_16 <<
334 def_bool y <<
335 depends on MWINCHIP3D || MWINCHIPC6 || <<
336 <<
337 config X86_INTEL_USERCOPY <<
338 def_bool y <<
339 depends on MPENTIUM4 || MPENTIUMM || M <<
340 <<
341 config X86_USE_PPRO_CHECKSUM <<
342 def_bool y <<
343 depends on MWINCHIP3D || MWINCHIPC6 || <<
344 <<
345 # <<
346 # P6_NOPs are a relatively minor optimization <<
347 # 6 processor, except that it is broken on cer <<
348 # Furthermore, AMD chips prefer a totally diff <<
349 # (which work on all CPUs). In addition, it l <<
350 # does not understand them. <<
351 # <<
352 # As a result, disallow these if we're not com <<
353 # NOPs do work on all x86-64 capable chips); t <<
354 # the right-hand clause are the cores that ben <<
355 # <<
356 config X86_P6_NOP <<
357 def_bool y <<
358 depends on X86_64 <<
359 depends on (MCORE2 || MPENTIUM4 || MPS <<
360 <<
361 config X86_TSC <<
362 def_bool y <<
363 depends on (MWINCHIP3D || MCRUSOE || M <<
364 <<
365 config X86_HAVE_PAE <<
366 def_bool y <<
367 depends on MCRUSOE || MEFFICEON || MCY <<
368 <<
369 config X86_CMPXCHG64 <<
370 def_bool y <<
371 depends on X86_HAVE_PAE || M586TSC || <<
372 <<
373 # this should be set for all -march=.. options <<
374 # generates cmov. <<
375 config X86_CMOV <<
376 def_bool y <<
377 depends on (MK8 || MK7 || MCORE2 || MP <<
378 <<
379 config X86_MINIMUM_CPU_FAMILY <<
380 int <<
381 default "64" if X86_64 <<
382 default "6" if X86_32 && (MPENTIUM4 || <<
383 default "5" if X86_32 && X86_CMPXCHG64 <<
384 default "4" <<
385 37
386 config X86_DEBUGCTLMSR !! 38 config M68000
387 def_bool y 39 def_bool y
388 depends on !(MK6 || MWINCHIPC6 || MWIN !! 40 depends on !MMU
>> 41 select CPU_HAS_NO_BITFIELDS
>> 42 select CPU_HAS_NO_CAS
>> 43 select CPU_HAS_NO_MULDIV64
>> 44 select CPU_HAS_NO_UNALIGNED
>> 45 select GENERIC_CSUM
>> 46 select CPU_NO_EFFICIENT_FFS
>> 47 select HAVE_ARCH_HASH
>> 48 select LEGACY_TIMER_TICK
>> 49 help
>> 50 The Freescale (was Motorola) 68000 CPU is the first generation of
>> 51 the well known M68K family of processors. The CPU core as well as
>> 52 being available as a stand alone CPU was also used in many
>> 53 System-On-Chip devices (eg 68328, 68302, etc). It does not contain
>> 54 a paging MMU.
>> 55
>> 56 config M68020
>> 57 bool "68020 support"
>> 58 depends on MMU
>> 59 select FPU
>> 60 select CPU_HAS_ADDRESS_SPACES
>> 61 help
>> 62 If you anticipate running this kernel on a computer with a MC68020
>> 63 processor, say Y. Otherwise, say N. Note that the 68020 requires a
>> 64 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the
>> 65 Sun 3, which provides its own version.
>> 66
>> 67 config M68030
>> 68 bool "68030 support"
>> 69 depends on MMU && !MMU_SUN3
>> 70 select FPU
>> 71 select CPU_HAS_ADDRESS_SPACES
>> 72 help
>> 73 If you anticipate running this kernel on a computer with a MC68030
>> 74 processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
>> 75 work, as it does not include an MMU (Memory Management Unit).
>> 76
>> 77 config M68040
>> 78 bool "68040 support"
>> 79 depends on MMU && !MMU_SUN3
>> 80 select FPU
>> 81 select CPU_HAS_ADDRESS_SPACES
>> 82 help
>> 83 If you anticipate running this kernel on a computer with a MC68LC040
>> 84 or MC68040 processor, say Y. Otherwise, say N. Note that an
>> 85 MC68EC040 will not work, as it does not include an MMU (Memory
>> 86 Management Unit).
>> 87
>> 88 config M68060
>> 89 bool "68060 support"
>> 90 depends on MMU && !MMU_SUN3
>> 91 select FPU
>> 92 select CPU_HAS_ADDRESS_SPACES
>> 93 help
>> 94 If you anticipate running this kernel on a computer with a MC68060
>> 95 processor, say Y. Otherwise, say N.
>> 96
>> 97 config M68328
>> 98 bool
>> 99 depends on !MMU
>> 100 select M68000
>> 101 help
>> 102 Motorola 68328 processor support.
>> 103
>> 104 config M68EZ328
>> 105 bool
>> 106 depends on !MMU
>> 107 select M68000
>> 108 help
>> 109 Motorola 68EX328 processor support.
>> 110
>> 111 config M68VZ328
>> 112 bool
>> 113 depends on !MMU
>> 114 select M68000
>> 115 help
>> 116 Motorola 68VZ328 processor support.
389 117
390 config IA32_FEAT_CTL !! 118 endif # M68KCLASSIC
391 def_bool y <<
392 depends on CPU_SUP_INTEL || CPU_SUP_CE <<
393 119
394 config X86_VMX_FEATURE_NAMES !! 120 if COLDFIRE
395 def_bool y <<
396 depends on IA32_FEAT_CTL <<
397 121
398 menuconfig PROCESSOR_SELECT !! 122 choice
399 bool "Supported processor vendors" if !! 123 prompt "ColdFire SoC type"
>> 124 default M520x
400 help 125 help
401 This lets you choose what x86 vendor !! 126 Select the type of ColdFire System-on-Chip (SoC) that you want
402 will include. !! 127 to build for.
403 128
404 config CPU_SUP_INTEL !! 129 config M5206
405 default y !! 130 bool "MCF5206"
406 bool "Support Intel processors" if PRO !! 131 depends on !MMU
>> 132 select COLDFIRE_SW_A7
>> 133 select COLDFIRE_TIMERS
>> 134 select HAVE_MBAR
>> 135 select CPU_NO_EFFICIENT_FFS
>> 136 help
>> 137 Motorola ColdFire 5206 processor support.
>> 138
>> 139 config M5206e
>> 140 bool "MCF5206e"
>> 141 depends on !MMU
>> 142 select COLDFIRE_SW_A7
>> 143 select COLDFIRE_TIMERS
>> 144 select HAVE_MBAR
>> 145 select CPU_NO_EFFICIENT_FFS
>> 146 help
>> 147 Motorola ColdFire 5206e processor support.
>> 148
>> 149 config M520x
>> 150 bool "MCF520x"
>> 151 depends on !MMU
>> 152 select COLDFIRE_PIT_TIMER
>> 153 select HAVE_CACHE_SPLIT
>> 154 help
>> 155 Freescale Coldfire 5207/5208 processor support.
>> 156
>> 157 config M523x
>> 158 bool "MCF523x"
>> 159 depends on !MMU
>> 160 select COLDFIRE_PIT_TIMER
>> 161 select HAVE_CACHE_SPLIT
>> 162 select HAVE_IPSBAR
>> 163 help
>> 164 Freescale Coldfire 5230/1/2/4/5 processor support
>> 165
>> 166 config M5249
>> 167 bool "MCF5249"
>> 168 depends on !MMU
>> 169 select COLDFIRE_SW_A7
>> 170 select COLDFIRE_TIMERS
>> 171 select HAVE_MBAR
>> 172 select CPU_NO_EFFICIENT_FFS
>> 173 help
>> 174 Motorola ColdFire 5249 processor support.
>> 175
>> 176 config M525x
>> 177 bool "MCF525x"
>> 178 depends on !MMU
>> 179 select COLDFIRE_SW_A7
>> 180 select COLDFIRE_TIMERS
>> 181 select HAVE_MBAR
>> 182 select CPU_NO_EFFICIENT_FFS
>> 183 help
>> 184 Freescale (Motorola) Coldfire 5251/5253 processor support.
>> 185
>> 186 config M5271
>> 187 bool "MCF5271"
>> 188 depends on !MMU
>> 189 select COLDFIRE_PIT_TIMER
>> 190 select M527x
>> 191 select HAVE_CACHE_SPLIT
>> 192 select HAVE_IPSBAR
>> 193 help
>> 194 Freescale (Motorola) ColdFire 5270/5271 processor support.
>> 195
>> 196 config M5272
>> 197 bool "MCF5272"
>> 198 depends on !MMU
>> 199 select COLDFIRE_SW_A7
>> 200 select COLDFIRE_TIMERS
>> 201 select HAVE_MBAR
>> 202 select CPU_NO_EFFICIENT_FFS
>> 203 help
>> 204 Motorola ColdFire 5272 processor support.
>> 205
>> 206 config M5275
>> 207 bool "MCF5275"
>> 208 depends on !MMU
>> 209 select COLDFIRE_PIT_TIMER
>> 210 select M527x
>> 211 select HAVE_CACHE_SPLIT
>> 212 select HAVE_IPSBAR
>> 213 help
>> 214 Freescale (Motorola) ColdFire 5274/5275 processor support.
>> 215
>> 216 config M528x
>> 217 bool "MCF528x"
>> 218 depends on !MMU
>> 219 select COLDFIRE_PIT_TIMER
>> 220 select HAVE_CACHE_SPLIT
>> 221 select HAVE_IPSBAR
>> 222 help
>> 223 Motorola ColdFire 5280/5282 processor support.
>> 224
>> 225 config M5307
>> 226 bool "MCF5307"
>> 227 depends on !MMU
>> 228 select COLDFIRE_TIMERS
>> 229 select COLDFIRE_SW_A7
>> 230 select HAVE_CACHE_CB
>> 231 select HAVE_MBAR
>> 232 select CPU_NO_EFFICIENT_FFS
>> 233 help
>> 234 Motorola ColdFire 5307 processor support.
>> 235
>> 236 config M532x
>> 237 bool "MCF532x"
>> 238 depends on !MMU
>> 239 select COLDFIRE_TIMERS
>> 240 select M53xx
>> 241 select HAVE_CACHE_CB
>> 242 help
>> 243 Freescale (Motorola) ColdFire 532x processor support.
>> 244
>> 245 config M537x
>> 246 bool "MCF537x"
>> 247 depends on !MMU
>> 248 select COLDFIRE_TIMERS
>> 249 select M53xx
>> 250 select HAVE_CACHE_CB
>> 251 help
>> 252 Freescale ColdFire 537x processor support.
>> 253
>> 254 config M5407
>> 255 bool "MCF5407"
>> 256 depends on !MMU
>> 257 select COLDFIRE_SW_A7
>> 258 select COLDFIRE_TIMERS
>> 259 select HAVE_CACHE_CB
>> 260 select HAVE_MBAR
>> 261 select CPU_NO_EFFICIENT_FFS
>> 262 help
>> 263 Motorola ColdFire 5407 processor support.
>> 264
>> 265 config M547x
>> 266 bool "MCF547x"
>> 267 select M54xx
>> 268 select COLDFIRE_SLTIMERS
>> 269 select MMU_COLDFIRE if MMU
>> 270 select FPU if MMU
>> 271 select HAVE_CACHE_CB
>> 272 select HAVE_MBAR
>> 273 select CPU_NO_EFFICIENT_FFS
>> 274 help
>> 275 Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
>> 276
>> 277 config M548x
>> 278 bool "MCF548x"
>> 279 select COLDFIRE_SLTIMERS
>> 280 select MMU_COLDFIRE if MMU
>> 281 select FPU if MMU
>> 282 select M54xx
>> 283 select HAVE_CACHE_CB
>> 284 select HAVE_MBAR
>> 285 select CPU_NO_EFFICIENT_FFS
>> 286 help
>> 287 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
>> 288
>> 289 config M5441x
>> 290 bool "MCF5441x"
>> 291 select COLDFIRE_PIT_TIMER
>> 292 select MMU_COLDFIRE if MMU
>> 293 select HAVE_CACHE_CB
407 help 294 help
408 This enables detection, tunings and !! 295 Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
409 296
410 You need this enabled if you want yo !! 297 endchoice
411 Intel CPU. Disabling this option on <<
412 makes the kernel a tiny bit smaller. <<
413 CPU might render the kernel unbootab <<
414 <<
415 If unsure, say N. <<
416 <<
417 config CPU_SUP_CYRIX_32 <<
418 default y <<
419 bool "Support Cyrix processors" if PRO <<
420 depends on M486SX || M486 || M586 || M <<
421 help <<
422 This enables detection, tunings and <<
423 298
424 You need this enabled if you want yo !! 299 config M527x
425 Cyrix CPU. Disabling this option on !! 300 bool
426 makes the kernel a tiny bit smaller. <<
427 CPU might render the kernel unbootab <<
428 301
429 If unsure, say N. !! 302 config M53xx
>> 303 bool
430 304
431 config CPU_SUP_AMD !! 305 config M54xx
>> 306 select HAVE_PCI
>> 307 bool
>> 308
>> 309 config COLDFIRE_PIT_TIMER
>> 310 bool
>> 311
>> 312 config COLDFIRE_TIMERS
>> 313 bool
>> 314 select LEGACY_TIMER_TICK
>> 315
>> 316 config COLDFIRE_SLTIMERS
>> 317 bool
>> 318 select LEGACY_TIMER_TICK
>> 319
>> 320 endif # COLDFIRE
>> 321
>> 322 comment "Processor Specific Options"
>> 323
>> 324 config M68KFPU_EMU
>> 325 bool "Math emulation support"
>> 326 depends on M68KCLASSIC && FPU
>> 327 help
>> 328 At some point in the future, this will cause floating-point math
>> 329 instructions to be emulated by the kernel on machines that lack a
>> 330 floating-point math coprocessor. Thrill-seekers and chronically
>> 331 sleep-deprived psychotic hacker types can say Y now, everyone else
>> 332 should probably wait a while.
>> 333
>> 334 config M68KFPU_EMU_EXTRAPREC
>> 335 bool "Math emulation extra precision"
>> 336 depends on M68KFPU_EMU
>> 337 help
>> 338 The fpu uses normally a few bit more during calculations for
>> 339 correct rounding, the emulator can (often) do the same but this
>> 340 extra calculation can cost quite some time, so you can disable
>> 341 it here. The emulator will then "only" calculate with a 64 bit
>> 342 mantissa and round slightly incorrect, what is more than enough
>> 343 for normal usage.
>> 344
>> 345 config M68KFPU_EMU_ONLY
>> 346 bool "Math emulation only kernel"
>> 347 depends on M68KFPU_EMU
>> 348 help
>> 349 This option prevents any floating-point instructions from being
>> 350 compiled into the kernel, thereby the kernel doesn't save any
>> 351 floating point context anymore during task switches, so this
>> 352 kernel will only be usable on machines without a floating-point
>> 353 math coprocessor. This makes the kernel a bit faster as no tests
>> 354 needs to be executed whether a floating-point instruction in the
>> 355 kernel should be executed or not.
>> 356
>> 357 config ADVANCED
>> 358 bool "Advanced configuration options"
>> 359 depends on MMU
>> 360 help
>> 361 This gives you access to some advanced options for the CPU. The
>> 362 defaults should be fine for most users, but these options may make
>> 363 it possible for you to improve performance somewhat if you know what
>> 364 you are doing.
>> 365
>> 366 Note that the answer to this question won't directly affect the
>> 367 kernel: saying N will just cause the configurator to skip all
>> 368 the questions about these options.
>> 369
>> 370 Most users should say N to this question.
>> 371
>> 372 config RMW_INSNS
>> 373 bool "Use read-modify-write instructions"
>> 374 depends on ADVANCED && !CPU_HAS_NO_CAS
>> 375 help
>> 376 This allows to use certain instructions that work with indivisible
>> 377 read-modify-write bus cycles. While this is faster than the
>> 378 workaround of disabling interrupts, it can conflict with DMA
>> 379 ( = direct memory access) on many Amiga systems, and it is also said
>> 380 to destabilize other machines. It is very likely that this will
>> 381 cause serious problems on any Amiga or Atari Medusa if set. The only
>> 382 configuration where it should work are 68030-based Ataris, where it
>> 383 apparently improves performance. But you've been warned! Unless you
>> 384 really know what you are doing, say N. Try Y only if you're quite
>> 385 adventurous.
>> 386
>> 387 config SINGLE_MEMORY_CHUNK
>> 388 bool "Use one physical chunk of memory only" if ADVANCED && !SUN3
>> 389 depends on MMU
>> 390 default y if SUN3 || MMU_COLDFIRE
>> 391 help
>> 392 Ignore all but the first contiguous chunk of physical memory for VM
>> 393 purposes. This will save a few bytes kernel size and may speed up
>> 394 some operations.
>> 395 When this option os set to N, you may want to lower "Maximum zone
>> 396 order" to save memory that could be wasted for unused memory map.
>> 397 Say N if not sure.
>> 398
>> 399 config ARCH_FORCE_MAX_ORDER
>> 400 int "Order of maximal physically contiguous allocations" if ADVANCED
>> 401 depends on !SINGLE_MEMORY_CHUNK
>> 402 default "10"
>> 403 help
>> 404 The kernel page allocator limits the size of maximal physically
>> 405 contiguous allocations. The limit is called MAX_ORDER and it
>> 406 defines the maximal power of two of number of pages that can be
>> 407 allocated as a single contiguous block. This option allows
>> 408 overriding the default setting when ability to allocate very
>> 409 large blocks of physically contiguous memory is required.
>> 410
>> 411 For systems that have holes in their physical address space this
>> 412 value also defines the minimal size of the hole that allows
>> 413 freeing unused memory map.
>> 414
>> 415 Don't change if unsure.
>> 416
>> 417 config 060_WRITETHROUGH
>> 418 bool "Use write-through caching for 68060 supervisor accesses"
>> 419 depends on ADVANCED && M68060
>> 420 help
>> 421 The 68060 generally uses copyback caching of recently accessed data.
>> 422 Copyback caching means that memory writes will be held in an on-chip
>> 423 cache and only written back to memory some time later. Saying Y
>> 424 here will force supervisor (kernel) accesses to use writethrough
>> 425 caching. Writethrough caching means that data is written to memory
>> 426 straight away, so that cache and memory data always agree.
>> 427 Writethrough caching is less efficient, but is needed for some
>> 428 drivers on 68060 based systems where the 68060 bus snooping signal
>> 429 is hardwired on. The 53c710 SCSI driver is known to suffer from
>> 430 this problem.
>> 431
>> 432 config M68K_L2_CACHE
>> 433 bool
>> 434 depends on MAC
432 default y 435 default y
433 bool "Support AMD processors" if PROCE <<
434 help <<
435 This enables detection, tunings and <<
436 <<
437 You need this enabled if you want yo <<
438 AMD CPU. Disabling this option on ot <<
439 makes the kernel a tiny bit smaller. <<
440 CPU might render the kernel unbootab <<
441 436
442 If unsure, say N. !! 437 config CPU_HAS_NO_BITFIELDS
>> 438 bool
443 439
444 config CPU_SUP_HYGON !! 440 config CPU_HAS_NO_CAS
445 default y !! 441 bool
446 bool "Support Hygon processors" if PRO <<
447 select CPU_SUP_AMD <<
448 help <<
449 This enables detection, tunings and <<
450 442
451 You need this enabled if you want yo !! 443 config CPU_HAS_NO_MULDIV64
452 Hygon CPU. Disabling this option on !! 444 bool
453 makes the kernel a tiny bit smaller. <<
454 CPU might render the kernel unbootab <<
455 445
456 If unsure, say N. !! 446 config CPU_HAS_NO_UNALIGNED
457 !! 447 bool
458 config CPU_SUP_CENTAUR !! 448
459 default y !! 449 config CPU_HAS_ADDRESS_SPACES
460 bool "Support Centaur processors" if P !! 450 bool
>> 451 select ALTERNATE_USER_ADDRESS_SPACE
>> 452
>> 453 config FPU
>> 454 bool
>> 455
>> 456 config COLDFIRE_SW_A7
>> 457 bool
>> 458
>> 459 config HAVE_CACHE_SPLIT
>> 460 bool
>> 461
>> 462 config HAVE_CACHE_CB
>> 463 bool
>> 464
>> 465 config HAVE_MBAR
>> 466 bool
>> 467
>> 468 config HAVE_IPSBAR
>> 469 bool
>> 470
>> 471 config CLOCK_FREQ
>> 472 int "Set the core clock frequency"
>> 473 default "25000000" if M5206
>> 474 default "54000000" if M5206e
>> 475 default "166666666" if M520x
>> 476 default "140000000" if M5249
>> 477 default "150000000" if M527x || M523x
>> 478 default "90000000" if M5307
>> 479 default "50000000" if M5407
>> 480 default "266000000" if M54xx
>> 481 default "66666666"
>> 482 depends on COLDFIRE
>> 483 help
>> 484 Define the CPU clock frequency in use. This is the core clock
>> 485 frequency, it may or may not be the same as the external clock
>> 486 crystal fitted to your board. Some processors have an internal
>> 487 PLL and can have their frequency programmed at run time, others
>> 488 use internal dividers. In general the kernel won't setup a PLL
>> 489 if it is fitted (there are some exceptions). This value will be
>> 490 specific to the exact CPU that you are using.
>> 491
>> 492 config OLDMASK
>> 493 bool "Old mask 5307 (1H55J) silicon"
>> 494 depends on M5307
461 help 495 help
462 This enables detection, tunings and !! 496 Build support for the older revision ColdFire 5307 silicon.
>> 497 Specifically this is the 1H55J mask revision.
463 498
464 You need this enabled if you want yo !! 499 if HAVE_CACHE_SPLIT
465 Centaur CPU. Disabling this option o !! 500 choice
466 makes the kernel a tiny bit smaller. !! 501 prompt "Split Cache Configuration"
467 CPU might render the kernel unbootab !! 502 default CACHE_I
468 <<
469 If unsure, say N. <<
470 503
471 config CPU_SUP_TRANSMETA_32 !! 504 config CACHE_I
472 default y !! 505 bool "Instruction"
473 bool "Support Transmeta processors" if <<
474 depends on !64BIT <<
475 help 506 help
476 This enables detection, tunings and !! 507 Use all of the ColdFire CPU cache memory as an instruction cache.
477 508
478 You need this enabled if you want yo !! 509 config CACHE_D
479 Transmeta CPU. Disabling this option !! 510 bool "Data"
480 makes the kernel a tiny bit smaller. <<
481 CPU might render the kernel unbootab <<
482 <<
483 If unsure, say N. <<
484 <<
485 config CPU_SUP_UMC_32 <<
486 default y <<
487 bool "Support UMC processors" if PROCE <<
488 depends on M486SX || M486 || (EXPERT & <<
489 help 511 help
490 This enables detection, tunings and !! 512 Use all of the ColdFire CPU cache memory as a data cache.
491 <<
492 You need this enabled if you want yo <<
493 UMC CPU. Disabling this option on ot <<
494 makes the kernel a tiny bit smaller. <<
495 CPU might render the kernel unbootab <<
496 513
497 If unsure, say N. !! 514 config CACHE_BOTH
498 !! 515 bool "Both"
499 config CPU_SUP_ZHAOXIN <<
500 default y <<
501 bool "Support Zhaoxin processors" if P <<
502 help 516 help
503 This enables detection, tunings and !! 517 Split the ColdFire CPU cache, and use half as an instruction cache
504 !! 518 and half as a data cache.
505 You need this enabled if you want yo !! 519 endchoice
506 Zhaoxin CPU. Disabling this option o !! 520 endif # HAVE_CACHE_SPLIT
507 makes the kernel a tiny bit smaller. <<
508 CPU might render the kernel unbootab <<
509 521
510 If unsure, say N. !! 522 if HAVE_CACHE_CB
>> 523 choice
>> 524 prompt "Data cache mode"
>> 525 default CACHE_WRITETHRU
511 526
512 config CPU_SUP_VORTEX_32 !! 527 config CACHE_WRITETHRU
513 default y !! 528 bool "Write-through"
514 bool "Support Vortex processors" if PR <<
515 depends on X86_32 <<
516 help 529 help
517 This enables detection, tunings and !! 530 The ColdFire CPU cache is set into Write-through mode.
518 531
519 You need this enabled if you want yo !! 532 config CACHE_COPYBACK
520 Vortex CPU. Disabling this option on !! 533 bool "Copy-back"
521 makes the kernel a tiny bit smaller. !! 534 help
522 !! 535 The ColdFire CPU cache is set into Copy-back mode.
523 If unsure, say N. !! 536 endchoice
>> 537 endif # HAVE_CACHE_CB
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